[FAQ] AM625 / AM623 / AM625SIP / AM620-Q1 / AM625-Q1 Design Recommendations / Custom board hardware design – common queries for PMIC TPS65219

Kallikuppa Sreenivasa

Guru**** 168164 points

Part Number: AM625
Other Parts Discussed in Thread: TPS65219, TPS6521905, TPS65215, AM2434

Tool/software:

HI Board designers,

I am designing my board using TPS65219.

Are there some common recommendation or observations that i should be aware?

4 months ago

0 Kallikuppa Sreenivasa 4 months ago

TI__Guru**** 168164 points

HI Board designers,

Refer below, common queries and replies

Q.1

Our customer has a question about TPS65219. Customer thinks to use TPS6521901 for supplying AM64x power. Is the TPS6521901 programmable device? Or, Is TPS6521901 not programmable device and customer cannot change anything of the output voltage and power sequence? If customer wants to change the power sequence, does customer needs to use TPS6521905? Customer worries about the unintentional change of power sequence. So, customer is happy if TPS6521901

The TPS6521901 and TPS6521905 both have NVM that can be reprogrammed. It is not easy to accidentally reprogram the NVM, so I do not think the customer needs to worry about accidentally modifying the power sequence.

The TPS6521905 comes with default setting with all outputs disabled, so it is helpful if a customer wants to program the device on the PCB while keeping all of the outputs in a safe state.

Q.2

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1407703/am625-pmic_lpm_en0-connection

Connecting the PMIC_LPM_EN0 to the PMIC MODE/STBY pin is optional. The TPS6521904 NVM has the MODE/STBY pin configured to select the Bucks switching mode with the following polarity:

MODE/STBY High, Bucks operate in forced-PWM
MODE/STBY Low, Bucks operate in auto-PFM.

If you are planning to use an AM62x low power mode where internal processor domains are turned-OFF while all the PMIC rails stay ON, then driving the MODE/STBY pin low with the PMIC_LPM_EN0 will allow to increase efficiency at light load.

Q.3

(+) AM625: How to set correct VDD_CORE & VDDA_DDR_PLL0 for LPDDR4 - Processors forum - Processors - TI E2E support forums

TPS6521908 is another option for customers who want to supply VDD_CORE with 0.85V instead of 0.75V. As noted in the processor datasheet, VDD_CORE and VDDR_CORE are expected to be powered by the same source so they ramp together when VDD_CORE is operating at 0.85V. In this scenario, we don't need to configure an LDO in the PMIC to supply 0.85 because Buck1 can supply both. This is why LDO2 is disabled.

Q.4

(+) TPS65219: 3.3V no output - Power management forum - Power management - TI E2E support forums

The TPS65219 PMIC executes two residual voltage checks; the first one occurs before the power-up sequence is executed and a second occurs during the power-up sequence (right before each rail is turned ON).

The first check can be disabled by changing register field "Register field "BYPASS_RAILS_DISCHA RGED_CHECK" but the second one cannot be disabled. Please note that changing any register field would require to turn-ON the PMIC first and get the device in Active state to enable I2C communication.

we found out where the residual voltage is coming from. This is come from E-PHY

- Residual voltage VLDO4 , 2.5V line : 4~500mV / VDDIO, 3.3V line : 50mV.

If the backfeeding issue on VLDO4 exist before the PMIC executes the power-up sequence, then none of the rails will turn-ON. The reason is because as I mentioned in my previous message, the PMIC performs the first residual voltage check before executing the power-up sequence.

Do you see a voltage on VLDO4 before Buck2 is turned ON?

Regards,

Sreenivasa

0 Kallikuppa Sreenivasa 4 months ago in reply to Kallikuppa Sreenivasa

TI__Guru**** 168164 points

HI Board designers,

Refer additional inputs

Q.5

TPS6521905: NVM programing procedure

https://www.ti.com/lit/ug/slvucm5/slvucm5.pdf

Q.6

(+) TPS65219: Can the maximum load capacitance of the channels be exceeded? - Power management forum - Power management - TI E2E support forums

If the maximum output capacitance on the PMIC rails is exceeded, the phase margin starts to drop and stability gets affected.

Just for reference, the TPS65219 PMIC has an option for "multi-PMIC operation" that allows to fully synchronize the sequencing between multiple TPS65219 devices. This feature might help to split the load/POL capacitance across the PMIC rails. Is this a non-automotive application? The TPS65215 has a 4x4mm package option that helps to keep the overall power solution small even when using 2x TPS65219 devices.

Q.7

TPS65219: Share 3.3V rail for 2pcs AM2434 and peripherals

If the customer wants to use a single 3.3V rail to supply both MCUs and peripherals, then I would recommend using the TPS6521904 NVM instead.

Here are the two options when using TPS6521904:

Using 3.3V pre-regulator to supply the 2x TPS6521904 PMICs and an external 3.3V power-switch. The power-switch can be enabled by the PMIC GPO2. The output of the power-switch can supply the MCU 3.3V IO and peripherals.
Using a 5V pre-regulator to supply the 2x TPS6521904 PMICs and an external 3.3V BUCK. The external Buck can be enabled by the PMIC GPO2. The output of the external 3.3V buck can be used to supply the PMIC LDO1, MCU 3.3V IO and peripherals.

Regards,

Sreenivasa