TMS320C6748: Fail occurs at Vix of Clock line in Fast/Typ condition

Hello Masaki Takeuchi

Thank you for the query.

Help me understand if you are doing the analysis based on some failure or is this a new design that you are considering.

Masaki Takeuchi said:

We are performing SI analysis of the connection I/F between TMS320C6748EZWT4 and DDR2.

Could you please share additional information on the connection made for simulation.

Regards,

Sreenivasa

Hi Sreenivasa,

Sorry for the delay in contacting you.

This is a new design that I am considering.

Best Regards,

Masaki Takeuchi

Hello Masaki Takeuchi,

Please refer inputs i received from the expert:

Seems like they are having an issue meeting the JEDEC spec for VIX. My suggestion would be for them to closely inspect the routing of the DQS traces on their board. If the DQS is not routed as a pure differential pair and non-symmetry gets introduced in the routing, it can lead to VIX violations as they are observing.

Regards,

Sreenivasa

Hi Sreenivasa,

Actually, we have not yet resolved this issue.
There was indeed an asymmetric part of the pattern you pointed out, and we corrected it, but it did not improve.

For example, could it be improved by inserting a common mode coil in the CK+ and CK- lines of the DSP?
Also, is it OK to put a common mode coil in this line?

We apologize for the inconvenience, but we would appreciate it if you could confirm the above.

Best Regards,

Masaki Takeuchi

Hello Masaki Takeuchi

Thank you.

Masaki Takeuchi said:

For example, could it be improved by inserting a common mode coil in the CK+ and CK- lines of the DSP?
Also, is it OK to put a common mode coil in this line?

Do you have prior experience adding filters?

Regards,

Sreenivasa

I do not have any prior knowledge of using common mode coils to mitigate SI issues in DDR so I cannot comment on that. After reviewing some of the comments, I would suggest that they look into the below items: 

1. What is the differential impedance of the CK+/- traces? Even if there is no visible asymmetry in trace routing, there can be variations in the differential impedance.
2. What is the pkg and Ccomp capacitance for the CK+/- pins in the DRAM IBIS model?
3. What is the power supply noise on the DDR IO power? Excessive supply noise can also manifest in SI issues

Regards,

Sreenivasa

Hi Sreenivasa,

//Question1

-What is the differential impedance of the CK+/- traces? Even if there is no visible asymmetry in trace routing, there can be variations in the differential impedance.

//Answer

We have already sent you the results of the study we conducted here, and as mentioned there, a direct connection between the driver and memory resulted in an NG judgment.

If the driver and memory are directly connected, variations in the differential impedance of the wiring are irrelevant.

In other words, Vix failure occurs in situations where the influence of wiring is not relevant.

//Question2

-What is the pkg and Ccomp capacitance for the CK+/- pins in the DRAM IBIS model?

//Answer

The DDR2 memory data currently in question is as follows.

[Component] NT5TU64M16HG (NANYA)

[Package Model] nu88a1p80v11_cm_pkg_x16

[Manufacturer] NANYA Technology Corp.

[Pin]      signal_name       model_name      R_pin           L_pin             C_pin

J8     　  CLK             　　CLKRCV             468.5m         1.73nH          0.41pF

K8         CLKB              　CLKRCV             437.3m          2.08nH          0.33pF

[Model]          CLKRCV_Input_667

C_comp                      1.35pf(typ)              1.33pf(min)               1.38pf(max)

For reference, we also simulated DDR2 data from a completely different manufacturer.

The DDR2 data is as follows.

Even in this case, Vix NG occurred and did not improve.

[Component]     MT47H64M16NF (Micron)

[Package Model] u88b_84ball_pkg

[Manufacturer]  Micron Technology,Inc.

[Pin]  signal_name      model_name      R_pin             L_pin             C_pin

J8      CK                       CLKIN               169.5m          1.995nH         0.369pF

K8     CK#                    CLKIN                167.9m          2.073nH         0.360pF

[Model]        CLKIN_533

C_comp                      1.025pF(typ)             0.975pF(min)             1.075p(max)

//Question3

-What is the power supply noise on the DDR IO power? Excessive supply noise can also manifest in SI issues

//Answer

In this analysis, we use the ideal power supply voltage listed in IBIS.

Therefore, We think it should not be a problem.

Best Regards,

Masaki Takeuchi

Hi Kallikuppa,

Thank you for your support.

I appreciate it.

 Best Regards,

Masaki Takeuchi