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AM5706: PCIE Endpoint runtime failure.

Part Number: AM5706

Tool/software:

Hi

Thanks for the previous support.

Previous Link : e2e.ti.com/.../am5706-pcie-endpoint-runtime-failure

We resolved the PCIE run time link failure issue successfully for the system where only one controller is being used.

But Now we are facing the same issue with another LRU in which we are using both the PCIE controllers available. We are using both the controller as endpoint and both of them are connected to 2 different Intel processor. We have already disabled the NSR bit as discussed in previous thread. But now if the link failure is happening the default value is as below 

0x51800044 --> 0x8 (Default initial configuration) 

0x51800044 --> 0x0 (After Link Down)

Same state transition is observed here as before. We are trying to find out how the NSR bit is getting enabled where during initialization I m disabling this bit.

Can you please give some information for below registers

PCIECTRL_EP_DBICS2_PM_CSR RW                                   0x5100 1044

PCIECTRL_EP_DBICS_PM_CSR RW                                      0x5100 0044

So please help us resolve this issue.

Note : All the information regarding this is available in previous thread. If any further information is required please let me know.