Tool/software:
Hi,
We have a system in which COMe module having Intel atom 3930 processor is defined as Root Complex with Xilinx Artix 7 series FPGA (the COMe module is connected to the PCB with this FPGA), another 2 endpoints with Ti AM5706 processor and another card having Xilinx Artix 7 series FPGA (Total 4 endpoints). All the cards are connected onto a backplane which takes care of the intercommunication. We had a PCIe runtime link down issue and with further testing it came to our attention that RC to FPGA Endpoints didn't face any link down issues in none of the tests conducted. On the other hand PCIe link down issue occured in the TI side in all the test cases (the only difference is that either one of the Ti cards will fail randomly in each test iteration).
The Ti side PCIe controller was found to be reset after the link down issue. This issue was solved by setting NSR bit to 1 in the register addresses 0x5100 1044 and 0x5100 0044. After modifying with this change we faced no PCIe link down issues in any of the test iterations including continuous test time durations above 11hrs.
The cause for the reset is still unknown and yet to be solved.
In another system which has 1 more identical RC (COMe module having Intel atom 3930 processor) added to the same setup as in the previous case, where the 2 RCs RC1 and RC2 are connected to slot 1 and slot 2 of the TI processor respectively.
PCIe test failed with link down occurrence in all the test cases. PCIe link down failure occurred in RC1 and RC2 in different test iterations. All these tests had NSR bit set to 1. The register values after link down showed the NSR bit set to 0.
what is the cause and suggest a solution for this issue
Also is it possible to give different Slot Clock Configuration bit (default value is 0x1) values in 0x5100 1080 (SS1) and 0x5180 1080 (SS2) to 0 in the Ti processor wen set as endpoint.
