PROCESSOR-SDK-J784S4: PROCESSOR-SDK-J784S4: Implementing PCIE driver for the R5F - Inbound&Outbound

Tool/software:

Hello,

I have a configuration with a Sitara(am64xx) configured as PCIe Endpoint and a Jacinto (j784s4) configured as PCIe Root Complex.
To configure Sitara as an Endpoint, I followed the following guideline: https://software-dl.ti.com/processor-sdk-linux/esd/AM64X/08_06_00_42/exports/docs/linux/Foundational_Components/Kernel/Kernel_Drivers/PCIe/PCIe_End_Point.html.

On the Jacinto side, I implemented an application for the R5F with the aim of configuring and carrying out communication via PCIe. To develop this application, I used the Sitara SDK code as a base.

With this code, I can now establish the link up and, from Jacinto, access the vendor ID of the remote device, as well as consult other configuration registers.

Since I am using the same functions from the AM64x SDK to implement on the R5F of the J784S4, I also use the same structures to configure the input and output regions.

For example:

Outbound Configuration (obAtuConfigPcie1):

Pcie_ObAtuCfg obAtuConfigPcie1[] =
{
    {
        .regionIndex = 1,
        .tlpType = PCIE_TLP_TYPE_MEM,
        .lowerBaseAddr = <expected value>, 
        .upperBaseAddr = 0x0,
        .regionWindowSize = 4095,
        .lowerTargetAddr =  <expected value>,
        .upperTargetAddr = 0x0,
    },
};

Inbound Configuration (ibAtuConfigPcie1):

Pcie_IbAtuCfg ibAtuConfigPcie1[] =
{
    {
        .regionIndex = 0,
        .tlpType = PCIE_TLP_TYPE_MEM,
        .lowerBaseAddr = <expected value>, 
        .upperBaseAddr = 0x0,
        .regionWindowSize = 4095,
        .lowerTargetAddr = (uint32_t)dst_buf,
        .upperTargetAddr = 0x0,
        .barAperture = PCIE_RCBARA_4K,
        .barCfg = PCIE_BARC_32B_MEM_BAR_NON_PREFETCH,
    },
    {
        .regionIndex = 1,
        .tlpType = PCIE_TLP_TYPE_MEM,
        .lowerBaseAddr = <expected value>, 
        .upperBaseAddr = 0x0,
        .regionWindowSize = 255,
        .lowerTargetAddr = <expected value>, 
        .upperTargetAddr = 0x0,
        .barAperture = PCIE_RCBARA_4K,
        .barCfg = PCIE_BARC_32B_MEM_BAR_NON_PREFETCH,
    },
};

Now, considering that I want to configure one output region and two input regions in the root complex, I would like to confirm:

What values ​​are expected for the lowerTargetAddr and lowerBaseAddr fields? I'm not asking for absolute values, but an indication of whether addresses type should be, phys local or phys remote, if so.

Thank you.