TDA4VP-Q1: Digital Input configuration on TDA4VP

Hi,

Deepankar maithani said:

- Can this pin be configured to be directly connected to any core i.e the R5F cores in main domain, R5F core in safety domain or A72 core? How is the routing to a core actually configured?

- Also, in general can a GPIO pin be accessible from any core or there are some limitations? 

The connectivity matrix table in the technical reference manual (table 3-5 in SPRUJ52D) will show which initiators (ex: R5) can access different targets such as the GPIO module. 

Deepankar maithani said:

However there is no mention of interrupt capability. How can i find out  for sure that there is no interrupt capability on this pin.

GPIO supports interrupts. Section 12.1.2 of the technical reference manual describes the GPIO module. Listed in the GPIO features: "Interrupts can be triggered by rising and/or falling edge, specified for each interrupt capable GPIO signal"

Deepankar maithani said:

Finally, I would like to understand what are the different categories of GPIOs as mentioned in the sysconfig tool?

I am not familiar with this , but based on the names it looks like the GPIO pins are being distinguished by their associated power rail. For instance, VDDSHV0, VDDSHV2, and VDDSHV5 are all different power supplies. 

Regards,
Kevin

Thanks for the response kevin.

Kevin S said:

The connectivity matrix table in the technical reference manual (table 3-5 in SPRUJ52D) will show which initiators (ex: R5) can access different targets such as the GPIO module.

I checked the table you mentioned and found  that there are 4 GPIO banks and all of them can be accessed from any of the MCUs in the main domain as well as in the Safety domain.

I also checked in the sysconfig tool that the  the pin AE36 corresponds to GPIO0_24  that means to pin 24 of GPIO bank 0.

Now the next question is how do i get the memory address of this bank and  offsets to the DIR, SET_DATA, OUT_DATA, CLR_DATA and IN_Data registers for GPIO_24 pin in the bank so that i can manipulate it? Can you suggest where should i look for that?

Secondly, If a i/o pin is accessible by multiple MCUs for example in my case GPIO0_24, does that mean that it is upto the developer that he/she doesnot manipulate it using firmware running on different MCUs simultaneously or is there a mechanism internally available that restricts the usage of a GPIO pin if another MCU is using it?

I found an excel document with register values in it. But i am not sure how to make sense of it.   I would like to control GPIO0_24. As per my understanding there should be a base address for GPIO0 bank and an offset for each register corresponding to GPIO0_24. But from the document i am not able to make sense of it. I would like to access following registers so would like to understand the addresses and offsets for them.

GPIO bank 0  base Address

DIR Reg offset for GPIO0_24 

SET_DATA Reg offset for GPIO0_24 

OUT_DATA Reg offset for GPIO0_24

CLR_DATA Reg offset for GPIO0_24

IN_DATA Reg offset for GPIO0_24

How do i get this info from the table. Does the 24 represents GPIO0_24? What does Bits field represent. How to interpret it?

Still waiting for your inputs. :)

Yes, GPIO0_24 would reside in bank 1, so you would want to use registers ending in "01".

Example: bit 24 of register GPIO_DIR01 would set the input/output direction of GPIO0_24.

Regards,
Kevin