AM62A7-Q1: LPDDR4 bit swapping

Tool/software:

Hello,

for our current implementation of the AM62A74AUMS SoC with LPDDR4 (Micron MT53E1G32D2-046 - Dual-Channel, Dual-Rank) we are using bit swapping for easier routing. The TI appnote for AM62A-LPDDR4 states that bit swapping within a byte is allowed, but a custom configuration in SysConfig is required.

What kind of implications do come with bit swapping. Are there any restrictions with regard to the functions (CRC, self refresh, etc.)?
Can you verify that the following bit swaps are allowed:

Byte 0:

SoC     LPDDR4
DQ1  -  DQ0_A
DQ0  -  DQ1_A

Byte 1:

SoC       LPDDR4
DQ11  -  DQ10_A
DQ13  -  DQ11_A
DQ10  -  DQ13_A

Byte 2:

SoC       LPDDR4
DQ17  -  DQ0_B
DQ16  -  DQ1_B
DQ21  -  DQ4_B
DQ20  -  DQ5_B

Byte 3:

SoC       LPDDR4
DQ29  -  DQ10_B
DQ28  -  DQ11_B
DQ27  -  DQ12_B
DQ26  -  DQ13_B

Best regards,
Daniel