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VICP synchronization on DM6446

AndrewN
Prodigy 170 points
Other Parts Discussed in Thread: SPRC831, TMS320DM6446

 

Hi all,

First, I have learned many things about VICP when searched this forum and I wanted to thank all of the contributors.

Could you help me to find out how to synchronize with the VICP on DM6446 device.

I have been reading all available documents for VICP, but am still unsure how interrupts that are asserted by the VICP are getting to the C64+ side of the device. DM6446 data manual states that VICP events 9, 10, 11 are available only to the ARM interrupt controller.

On the VICPLIB library (sprc831) FAQ web page there are discussed the VICP interrupts only for DM648 device (Q.5 and Q.6), which does not have an ARM CPU, so the events 27, 28, 29 are directly mapped to the C64+ interrupt controller.

In any situation neither event is deliberately explained in the documentation, or (shame on me) I wasn't able to find any description.

On the other hand, the VICPLIB that I have to use, is targeted to run on the C64+ CPU side of the DM6446 device, but apparently without an option of getting an interrupt from the VICP, since the DSP interrupt controller does not get any of the VICP events. (I wonder though where gets the DSQINT (EDMA3) event? By mere name similarity with ASQINT (VICP Sqr ARM interrupt) I would guess that the DSQINT might be an unspecified VICP Sqr DSP interrupt, but of course, I wouldn't guess that.)

Does that mean that it is the job for e.g. Linux on the ARM side to catch the VICP interrupts and signal to DSP/BIOS threads?

What might be other options that would not include an interaction with the ARM side? Could it just be a completion interrupt from EDMA3 controller? If yes, then it must be the EDMA3 LLD that calls the CPIS_isr() function upon receiving EDMA3 events 8, 9, 10, 11. Is it correct?

Examples in the VICPLIB include a CPIS_isr() function, but I was unable to find out which event it is intended to service.

Thank you all who responded,

Andrew

 

 

  • 0
    Prodigy 170 points

    A little bit more words in order to make myself more clear and justified.

    Essentially, the SPRUGJ3E.pdf on page 6 states:

    "After the processing of the entire input buffer is over, the VICP notifies the DSP by triggering an interrupt."

    I assume that this clause equally applies to _both_ DM648 and DM6446.

    The question is which event corresponds to VICP interrupt on DM6446?

    In the SPRS283H / TMS320DM6446 data manual on page 112, section 6.7.2, table 6-22 "DSP Interrupts", does not list any event asserted by the VICP.

    So I beleive that I am missing something. Please help me to sort this out.

    Thanks and regards,

    Andrew

     

  • 0 in reply to AndrewN
    TI__Expert 6335 points

    Hi Andrew,

     

    On DM6446, the VICP DSQINT event mapped to DSP is event #20. 

     

    regards,

     

    Victor

  • 0 in reply to Victor Cheng
    TI__Expert 6335 points

    Note that the file: test/src/platform_support64xbios.c

    shows how the interrupt is hooked up to DSP/BIOS by the function intSetup().

     

    regards,

     

    Victor

  • 0 in reply to Victor Cheng
    Prodigy 170 points

    Hi Victor,

    Thanks for the information, I appreciate this very much. Let me ask a few more generic questions:

    Do the ASQINT and DSQINT stand for the VICP Sequencer interrupt?

    Are the other VICP events also routed to the DSP interrupt controller? 

    Regards,

    Andrew

  • 0 in reply to AndrewN
    TI__Expert 6335 points

    Hi Andrew,

    Yes ASQINT is sequencer interrupt to ARM and DSQINT is sequencer interrupt to DSP. However only DSQINT is used by the underlying scheduling library. In other words, it never trigers the ASQINT upon completion of VICP processing. The reason is that, by design, we chose to have DSP control the VICP, not ARM.

    The DSQINT is the only event routed to the DSP interrupt controller. 

    regards,

    Victor

     

  • 0 in reply to Victor Cheng
    Prodigy 170 points

    Hi Victor,

    I am hoping this information would be sufficient to try to work with VICP library.

    Thanks and best regards,

    Andrew

  • 0 in reply to AndrewN
    Prodigy 120 points

    Hi,

    I am developing an application on DM6446 EVM board with ARM9, DSP, VICP and some peripherals
    I got a problem and don't find any solution for that,
    Before please note my design details:

        1 - The ARM is master and control other parts of system
        2 - The boot process is executed from NAND (BTSEL == 00), So after power on, the RBL (ROM Boat Loader) copies
            second level boot loader from NAND to ARM IRAM and then my application is loaded to DDR
        3 - Based on "spraai4.pdf" and "sprue14c.pdf" documents, I used the ubl to load my own application to DDR
            (it is noted that my application does not use any linux so I dont use uboot, I developed specific application)
        4 - Binary file of my ARM application from .out was generated with tms470.exe in CCS v3.3
        5 - Settings for NAND is J4=NAND, S3[1..4] = 0000 (NAND boot, 8-bit AEMIF, ARM boots DSP)
        6 - In my application, first some peripherals of systems (PINMUX, UART, I2C, VPSS) are configured, then DSP and
            VICP codes are copied to DDR, then DSPBOOTADDR is programed and finally the ARM releases C64x+ DSP from reset,
        7 - The DSP&VICP codes are included in ARM binary file as a header
        8 - To program NAND flash I use flash_burn_utility based on following web site
            (http://wiki.davincidsp.com/index.php?title=Serial_Boot_and_Flash_Loading_Utility)
        9 - The value of PSC_MDSTAT_IMCOP register (0x01C418A0)is 0x1E03 and the value of PSC_MDCTL_IMCOP register (0x01C41AA0) is 0x0003
            (I tested them with 0x1F03 and 0x0103 respectively but there is no difference)

    All parts of my design works correctly except VICP (actually IMX does not generate interrupt for completion of procedure). for example, I checked above procedure with simple DSP example ("blinding a LED") and the DSP boots and works correctly

    Also I checked program with JTAG Emulator when DSP_BT == 1 (J4=NAND, S3[1..4] = 0001), and VICP works correctly in this condition,
    Under this circumstances, I flashed NAND but ARM does not boot when DSP_BT == 1(J4=NAND, S3[1..4] = 0001),

    I dont really know why VICP does not work when DSP_BT == 0, is it need to initialze EDMA, INTC, MCBSP, ...?
    Does EDMA3LLD configuration after system power on conflicts with VICP?
    (I dont initialze and configure EDMA3 in ARM application because I think the DSP program initializes it automatically before using VICP in CPIS_Init method)