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TDA3MV: Pin Delay data for all input pin / Memory Simulation Tool

Ted Huh
Intellectual 2780 points
Part Number: TDA3MV

Tool/software:

Hi Champs,

My customer has started the layout design with TDA3MV, and they want to get the information of pin delay of TDA3MV.

pin delay is the delay occurred by internal wire bonding.

Could you share the information to customer about this?

and do we have memory test simulator tool for TDA3MV? so customer can test the DDR3 connection before they get the real board.

Regards,

Ted

  • +1
    TI__Guru 52192 points

    Hello Ted,

    The customer should refer to the DDR3 Layout guidelines section of the device datasheet.  This documents the PCB level requirements, and although the package skew is not explicitly documented if the customer follows the layout guidelines (or copies EVM layout) then the interface will include the necessary margin for robust operation taking into account the package and die contribution.

    We do provide iBIS models that can be used for signal integrity checks.

    TDA3x IBIS Model

    Regards,

    Kyle