AM67: How to enable USB test mode for USB 2.0 and USB 3.0 respectively?

Have you tried to unlock the registers and try the commands again? If you were seeing the LFPS, then wouldn't it mean that it is the device is in compliance mode.

And have you followed the same process as described to not connect the scope initially and modifying the registers and then connecting the scope to switch the patterns?

I can follow up with them on this.

Shreyas, 

Please advice how to unlock the registers if it is because the registers are locked. 

I tried to modify the registers without connecting scope at all. 

BR, Rich

Lockkey0 0x68EF3490
Lockkey1 0xD172BC5A

To unlock the registers, write these values to the kick0 and Kick 1 registers. Refer to the TRM for the offset values of the different partition registers.

As received from IP vendor:

"Scope needs to send LFPS.Ping to Controller to switch the Compliance Patterns. 
Typically, scope supporting USB Compliance procedure provide tools to automatically run the whole USB Compliance procedure.
In such case, the scope controls sending LFPS.Ping and does appropriate checks for each of the Compliance Pattern.

Controller doesn't lock register access, if the clocks are enabled register access is possible."

Also, want to know if you have modified the board as suggested by Robert? 

Shreyas,

Are you referring below kick0 and kick1 with lockkey0 and lockey1 respectively? 

Lockkey0 0x68EF3490
Lockkey1 0xD172BC5A

I found key0 and key1 value are different from what you suggest here. 

Could you provide complete commend set to enable compliance test? 

• Key0 = 83E7 0B13h
• Key1 = 95A4 F1E0h
• Locked = Write protection enabled
• Unlocked = Write protection disabled

BR, Rich

Rich,

Please let me know where did you get the snip from.

From what I see, the AM67 registers all have the same lockey0, lockkey1 values.

Shreyas, 

The picture I attached is from AM67x TRM chapter 12.7.3.3.3.2.1

The Lockkey0 and Lockkey1 seems for PLL registers.  

Lockkey0 0x68EF3490
Lockkey1 0xD172BC5A

Are the key in the attached picture for MMR_CTRL registers? 

We need clear commend instructions and order (a script will be nice) to change register values in Linux. 

We cannot conduct compliance test for USB 3.0 on AM67x for long and we are seeking a way to achieve the goal. 

What's the exactly way AM67x USB3.0 compliance test mode been enabled in house? 

We would like to help our customers WW to be able to enter compliance test mode on their own board.  

Can we have simple commend in Linux like we do for USB 2.0? 

BR, Rich 

Hi Rich,

The Key0, and Key1 are for the CTRL_MMR registers.

As I have said before, our way of testing the USB3.0 compliance is not through Linux and register writes. I have used the CCS binaries for it. And according to  the IP vendor, this is the same way to enter USB3.0 compliance mode by modifying the registers as mentioned earlier.

Shreyas, 

The Key0, and Key1 are for the CTRL_MMR registers and I think all the registers we use for compliance test belongs CTRL_MMR registers. 

For USB 3.0 compliance test via CCS binaries, did you run this test on AM67x EVM or Beagle AI board? 

There is USB 3.0 HUB in between AM67x and USB 3.0 type A connector on AM67x EVM. Can the test be run on AM67x EVM?

Could you provide binaries to me so I can run same test on AM67x EVM? 

BR, Rich

Rich,

I did not use the EVM for the USB3.0 compliance test. I used the SVB which is made for the SERDES and high speed validation.

Would you want me to send out the binary (LFPS and CP1 pattern) to try out?

Shreyas, 

Are the binary also run on CCS via JTAG? 

We cannot do same test on AM67x EVM due to USB hub. 

On DRA821 (J7200) EVM, there is a USB3.1 Type C port. 

Do we have test program for DRA821 for USB3 compliance test? 

BR, Rich

Shreyas, 

I found the CTRL_MMR0 registers have been filled the keys you listed below when booting to Linux. 

The relate control registers still cannot be changed as expected. 

Lockkey0 0x68EF3490
Lockkey1 0xD172BC5A

To unlock the registers, write these values to the kick0 and Kick 1 registers.

root@am67-sk:~# devmem2 0x00101008
/dev/mem opened.
Memory mapped at address 0xffffac1f4000.
Read at address 0x00101008 (0xffffac1f4008): 0x68EF3491
root@am67-sk:~# devmem2 0x0010100C
/dev/mem opened.
Memory mapped at address 0xffffb369f000.
Read at address 0x0010100C (0xffffb369f00c): 0xD172BC5A

BR, Rich

Shreyas, 

TI EVM has USB hub on it so customer can only test on their own board. 

Secondary, JTAG is not available on customer board.  

We need a way to enable USB compliance test in customer side. 

A boot loader run on SD card or Linux script to enable it will be feasible.

BR, Rich  

Hi Rich,

We had done the testing internally on our specially built boards for USB compliance test and used CCS/JTAG for it.

I have attached 2 binaries that you can generate LFPS and CP1 on Serdes0 Lane0 for USB compliance.

If you can try it out and let me know?

K3_J7AEN_BER_USB_LFPS_S0L0.out

USB3_S0L0_UDD_CP1_INTSSC.out

Rich,

I want to revisit this USB3.0 compliance procedure again after talking through colleagues.

Initially, I provided the compliance procedure as follows:

0x31000420h, write 0x0A010340 - This register was for the USB0 (which only have USB2.0)

For USB1, you need 0x31210490 register to be modified.

And as mentioned before; you need to change these 3 fields.

Enable Compliance Mode in Host Controller 

- write USB3 PORTSC register setting the following bits:                                - PP [9]                                - LWS [16]                                - PLS [8:5] = 0xA

And you should not need any unlocking for the registers.

devmem2 0x31210490 w 0x0A010340h.

Please try this above and let me know.

Also, wanted to confirm if the schematic has now USB1 connected to the SERDES pins, right? Previously, USB0 was connected to SERDES.

Does this have customer developed Linux or is it from SDK?  If I need to replicate either PCIe or others, I need to know if any particular version is used.

I will also let you know if I have anything else.

Shreyas, 

This is a question I kept asking for USB3 compliance test. 

For USB3 compliance test, there should be only USB super speed signals and nothing with USB2.0 DP/DM signals. 

Why we need to configure USB0 or USB1 which supports USB2.0 only? 

And next is the limitation which USB3 need to be tied with USB1 but and CANNOT with USB0. 

From software side, is there any setting requirement for USB1 + SERDES0 (USB3.0)? 

Can USB1 + SERDES1 be used as USB3.0?

Customer original schematic use USB0 + SERDES0 and blue wire USB1 + SERDES0. Latest SDK 10.1 is used. 

We also want to know what specific config needs to be change for using USB1 + SERDES0 or it will be same as EVM but just USB3.0 been connected to USB 3.0 HUB. 

For the test commend, here I summarized as just write below commend to achieve

 write USB3 PORTSC register setting the following bits:                                - PP [9]                                - LWS [16]                                - PLS [8:5] = 0xA

devmem2 0x31210490 w 0x0A010340

BR, Rich

Shreyas,

From register, all registers in USB0 sections show USB2SS and all registers in USB1 show USB3p0SS.

We will take a try on customer board.   

USB0

3100 0420h -->  USB2SS_PORT_XHCI_PORT_20_PORTSC_20   

3100 0434h -->  USB2SS_PORT_XHCI_PORT_30_PORTPMSC_30  (This looks for PM only)

USB1

3121 0480h -->  usb3p0ss_ctrl_xhci_PORTSC1USB2

3121 0490h --> usb3p0ss_ctrl_xhci_PORTSC1USB3

BR, Rich

Hi Rich,

Shreyas and I did some experiments in the lab. We have not been able to enter compliance mode for USB yet, but sharing you updates.

We are going down 2 different paths for debugging the issue:

1. Compliance test using USB3.0 Electrical Test Fixture device. We have this piece of hardware here: https://www.usb.org/sites/default/files/documents/superspeedtesttopologies.pdf 
   1. Procedure:
      1. We have tried connecting to USB-C port on J7AHP 27x27 (aka, J742S2 or TDA4VPE)
      2. We boot Linux and run “echo compliance > /sys/kernel/debug/usb/xhci/xhci-hcd.10.auto/ports/port02/portsc” after verifying port02 is indeed USB3.0
      3. Nothing on the scope
   2. Suspicions/next steps
      1. We are missing USB3.0 Host Test Fixture board (aka, 5" Host Test Fixture 2) and we were substituting it with the USB3.0 Device Test Fixture board (aka, 11" Device Test Fixture 2) in conjunction with “Host Test Fixture 1“ in https://www.usb.org/sites/default/files/documents/superspeedtesttopologies.pdf
      2. We suspect the 5” Device Test Fixture 2 cannot be substituted by 11” Host Test Fixture 2
      3. We need to locate this missing piece of hardware
2. Triggering compliance test using register writes we have obtained from Cadence
   1. Procedure:
      1. Under Linux, run “devmem2 0x31210490 w 0x0A010340h” to set PP, LWS, and PLS fields
      2. Register is partially updated (aka, the most significant bits 0x0A portion is updated, but least significant bits 0x10340 do not get updated)
   2. Suspicions/next steps
      1. Maybe a limitation with devmem2? Some bits are protected from writes?
      2. Next step, experiment if we can directly change bits through CCS debugger

Bottomline is that USB compliance mode issue is in-progress, but above is the progress we have made.

Regards,

Takuma

Takuma,

I tried devmem2 0x31210490 w 0x0A010340 on AM67x SK EVM and got same result as you got. 

    a. Under Linux, run “devmem2 0x31210490 w 0x0A010340h” to set PP, LWS, and PLS fields.

    b. Register is partially updated (aka, the most significant bits 0x0A portion is updated, but least significant bits 0x10340 do not get updated)

root@am67-sk:~# lsusb
Bus 001 Device 001: ID 1d6b:0002 Linux Foundation 2.0 root hub
Bus 001 Device 002: ID 0451:8142 Texas Instruments, Inc. TUSB8041 4-Port Hub
Bus 002 Device 001: ID 1d6b:0003 Linux Foundation 3.0 root hub
Bus 002 Device 002: ID 0451:8140 Texas Instruments, Inc. TUSB8041 4-Port Hub
root@am67-sk:~# devmem2 0x31210490
/dev/mem opened.
Memory mapped at address 0xffff9162d000.
Read at address 0x31210490 (0xffff9162d490): 0x00001203
root@am67-sk:~# devmem2 0x31210490 w 0x0A010340
/dev/mem opened.
Memory mapped at address 0xffff7f7d8000.
Read at address 0x31210490 (0xffff7f7d8490): 0x00001203
Write at address 0x31210490 (0xffff7f7d8490): 0x0A010340, readback 0x0A010340
root@am67-sk:~# devmem2 0x31210490
/dev/mem opened.
Memory mapped at address 0xffffb2823000.
Read at address 0x31210490 (0xffffb2823490): 0x0A001203
root@am67-sk:~# Under Linux, run “devmem2

BR, Rich

Takuma, 

I took AM69x SK EVM to take a try, same result was observed.

I wonder if it is because there is also a USB Hub behind USB controller. 

root@am69a-sk:/opt/edgeai-gst-apps#
root@am69a-sk:/opt/edgeai-gst-apps# devmem2 0x06010490
/dev/mem opened.
Memory mapped at address 0xffffbb83f000.
Read at address 0x06010490 (0xffffbb83f490): 0x00001203
root@am69a-sk:/opt/edgeai-gst-apps# devmem2 0x06010490 w 0x0a010340
/dev/mem opened.
Memory mapped at address 0xffffbee2c000.
Read at address 0x06010490 (0xffffbee2c490): 0x00001203
Write at address 0x06010490 (0xffffbee2c490): 0x0A010340, readback 0x0A010340
root@am69a-sk:/opt/edgeai-gst-apps# devmem2 0x06010490
/dev/mem opened.
Memory mapped at address 0xffff9d002000.
Read at address 0x06010490 (0xffff9d002490): 0x0A001203
root@am69a-sk:/opt/edgeai-gst-apps#

BR, Rich

Rich,

As mentioned in the call, you need to connect the host test fixture after writing the devmem command to put the USB into compliance mode. Without the test fixture connected, the register writes wont be effective.

I have tried it here in the lab and see the same behavior if the test fixture is not connected; the writes wont stick.

Please try with the test fixture and let me know.

Shreyas, 

Thanks for your guideline and validation on J7AHP (SK-AM69) and confirm same procedure work on DRA821 (J7200) EVM too. 

These two chips use same USB3 IP and same register set to use.   

I had verified on DRA821 EVM in lab today by devmem2 commend and confirm work. 

For AM67x, may you specify whether devmem2 0x31210490 w 0x0A010340 the correct register for CP0? 

Second, what's the next register for entering CP1?  

devmem2 0x06010490 w 0x0a010340

devmem2 0x0601812c w 0x18230c10 ( CP1 pattern)

Third, I don't check echo compliance mode today but it looks only can enable CP0 but no sure how to switch to CP1. 

Is there continue commend to switch from CP0 to CP1? 

BR, Rich

---------------------------------------------------------------------------------------------------------------------------------------------------------------

J7AHP:

Host test fixture board OR USB 3.1 Compliance load board procedure.

Enter compliance mode using devmem2 command:

Ensure that the EVM is setup to USB host mode using the DIP switches – refer to the EVM guide for the switch settings.

EVM is not connected to host test fixture (a typeC to typeA connector is left plugged in to the typeC port)

Boot up Linux

‘devmem2 0x06010490 w 0x0a010340’

Connect host test fixture to EVM

(‘devmem2 0x06010490’ command should read back 0x0a000340 to ensure compliance mode entry)

Observation:

CP0 pattern continuously – Measure CP0 on USB test suite

For CP1:

Disconnect and reboot the EVM

Enter compliance mode:

devmem2 0x06010490 w 0x0a010340

devmem2 0x0601812c w 0x18230c10 ( CP1 pattern)

Reconnect the test fixture to EVM

Observation:

Cp1 pattern (at the Nyquist frequency 2.5GHz clock) but SSC has to be enabled internally within the SERDES. Switches from CP0 to CP1 (no BERT controlling the Ping.LFPS). The SSC is not enabled by the USB controller. Measure on USB test suite.

Echo compliance mode:

EVM is not connected to test fixture.

Boot up Linux

echo compliance > /sys/kernel/debug/usb/xhci/xhci-hcd.x.auto/ports/port02/portsc' – x = after ../usb/xhci/ <tab> and it will auto populate.

Check compliance command: cat /sys/kernel/debug/usb/xhci/xhci-hcd.x.auto/ports/port02/portsc

Connect the test fixture

Observation:

Bursts of LFPS ( and CP0) pattern repeating

Measure the LFPS using the USB test suite.

Rich,

For AM67, please use the following:

devmem2 0x31210490 w 0x0a010340 - Host TX compliance mode.

And to switch from CP0 to CP1, please enter this after entering the compliance mode.
devmem2 0x3121812c w 0x18230c10 (CP1).

and then connect the test fixture back to the slot.

Please let me know.

Would you also want to enable RX loopback mode?

Shreyas,

Do you mean USB also have RX loopback mode if customer side have BERT? 

BR, Rich 

Hi Shreyas & Rich,

Sorry I didn't closely follow this thread and don't know where exactly you are now on this compliance test work, but I am not sure if the following note would help you.

Back in 2021, we did USB3.0 compliance test on AM64x, and here are some notes I found on my computer for that work.

1. When entering compliance mode using command 'echo compliance > /..../portsc', the xhci driver check if HCC2_CTC is enabled before entering compliance. See the following code in kernel drivers/usb/host/xhci-debugfs.c, function xhci_port_write():

        if (!strncmp(buf, "compliance", 10)) {
                /* If CTC is clear, compliance is enabled by default */
                if (!HCC2_CTC(xhci->hcc_params2))
                        return count;

while on AM64x, the variable xhci->hcc_params2 is not populated, due to drivers/usb/host/xhci.c, function xhci_gen_setup(), becuase of the xhci version on AM64x is v1.00 though it does have hcc_params2:

        if (xhci->hci_version > 0x100)
                xhci->hcc_params2 = readl(&xhci->cap_regs->hcc_params2);

So we added the following hack to ensure the AM64x USB can enter compliance mode:

diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
index a8d97e23f601..5579d50158e1 100644
--- a/drivers/usb/host/xhci.c
+++ b/drivers/usb/host/xhci.c
@@ -5234,7 +5234,7 @@ int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks)
        xhci->hcc_params = readl(&xhci->cap_regs->hc_capbase);
        xhci->hci_version = HC_VERSION(xhci->hcc_params);
        xhci->hcc_params = readl(&xhci->cap_regs->hcc_params);
-       if (xhci->hci_version > 0x100)
+       if (xhci->hci_version >= 0x100)
                xhci->hcc_params2 = readl(&xhci->cap_regs->hcc_params2);

2. The kernel devicetree binding doc Documentation/devicetree/bindings/phy/phy-cadence-sierra.yaml and phy-cadence-torrent.yaml have:

      cdns,ssc-mode:
        description:
          Specifies the Spread Spectrum Clocking mode used. It can be NO_SSC,
          EXTERNAL_SSC or INTERNAL_SSC.

So we used the following kernel devicetree patch to enable SSC on AM64x USB:

diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts
index a1fc366df82e..1844c2f7cc4f 100644
--- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts
+++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts
@@ -702,6 +702,7 @@ serdes0_usb_link: phy@0 {
                #phy-cells = <0>;
                cdns,phy-type = <PHY_TYPE_USB3>;
                resets = <&serdes_wiz0 1>;
+               cdns,ssc-mode = <TORRENT_SERDES_INTERNAL_SSC>;
        };
 };

Bin, 

Thanks for the sharing. 

These more like driver implementation and I am asking more from a user what the order and commend/instruction need to be used to complete Compliance test in customer lab. 

For the Echo compliance mode, assuming the steps show below can start CP0 pattern, how to switch to CP1 after CP0?

Is there similar comment to set? 

BR, Rich 

----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

Echo compliance mode:

EVM is not connected to test fixture.

Boot up Linux

echo compliance > /sys/kernel/debug/usb/xhci/xhci-hcd.x.auto/ports/port02/portsc' – x = after ../usb/xhci/ <tab> and it will auto populate.

Check compliance command: cat /sys/kernel/debug/usb/xhci/xhci-hcd.x.auto/ports/port02/portsc

Connect the test fixture

Observation:

Bursts of LFPS ( and CP0) pattern repeating

Measure the LFPS using the USB test suite.

Hi Bin,

Thanks for all the wealth of information provided on the Linux driver setup.

So it looks like the SERDES phy is also setup to enable the SSC. Would the SSC always enabled once in compliance mode or is it only enabled if the CP1 pattern is output on the TX? Because the CP1 pattern requires SSC to be enabled but not the CP0 pattern. It looks like if SSC is enabled, then all TX output would have SSC on it?

Rich,

For CP1 pattern, for enabling CP1 pattern, please enter this after entering the compliance mode.
devmem2 0x31210490 w 0x0a010340- Compliance mode

devmem2 0x3121812c w 0x18230c10 - outputs Nyquist freq clock signal (2.5GHz -CP1 pattern)

Hi Shreya,

Sorry but I don't know the answer. I was only helping hardware folks in setting up compliance test, but I don't know how the hardware module works internally.

Thanks Bin.

Bottom line is that the SSC is enabled by the SERDES phy and not the USB controller.