Tool/software:
Hi,
i have problem to connect to the device. I use ccs 10.4.0.00006.
The emulator is correctly connected to my PC. If i run the Bh560V2config, the emulator is listet. So the connection is working.
[Start]
Execute the command:
%ccs_base%/common/uscif/dbgjtag.exe -f %boarddatafile% -rv -o -F inform,logfile=yes -S pathlength -S integrity
[Result]
-----[Print the board config pathname(s)]------------------------------------
C:\Users\DEVELO~1\AppData\Local\TEXASI~1\
CCS\ccs1040\0\0\BrdDat\testBoard.dat
-----[Print the reset-command software log-file]-----------------------------
This utility has selected a 560/2xx-class product.
This utility will load the program 'bh560v2u.out'.
Loaded FPGA Image: C:\ti\ccs1040\ccs\ccs_base\common\uscif\dtc_top.jbc
The library build date was 'Jun 25 2021'.
The library build time was '16:06:55'.
The library package version is '9.4.0.00129'.
The library component version is '35.35.0.0'.
The controller does not use a programmable FPGA.
The controller has a version number of '6' (0x00000006).
The controller has an insertion length of '0' (0x00000000).
The cable+pod has a version number of '8' (0x00000008).
The cable+pod has a capability number of '7423' (0x00001cff).
This utility will attempt to reset the controller.
This utility has successfully reset the controller.
-----[Print the reset-command hardware log-file]-----------------------------
The scan-path will be reset by toggling the JTAG TRST signal.
The controller is the Nano-TBC VHDL.
The link is a 560-class second-generation-560 cable.
The software is configured for Nano-TBC VHDL features.
The controller will be software reset via its registers.
The controller has a logic ONE on its EMU[0] input pin.
The controller has a logic ONE on its EMU[1] input pin.
The controller will use falling-edge timing on output pins.
The controller cannot control the timing on input pins.
The scan-path link-delay has been set to exactly '2' (0x0002).
The utility logic has not previously detected a power-loss.
The utility logic is not currently detecting a power-loss.
Loaded FPGA Image: C:\ti\ccs1040\ccs\ccs_base\common\uscif\dtc_top.jbc
An error occurred while hard opening the controller.
-----[An error has occurred and this utility has aborted]--------------------
This error is generated by TI's USCIF driver or utilities.
The value is '-231' (0xffffff19).
The title is 'SC_ERR_PATH_IR_MEASURE'.
The explanation is:
The measured length of the JTAG IR instruction path is invalid.
This indicates that an error exists in the link-delay or scan-path.
[End]
Attached also the configuration from the Target
