[FAQ] AM625 / AM623 / AM62A / AM62P / AM62D-Q1 / AM64x / AM243x Design Recommendations / Custom board hardware design - List of errors observed during customer schematics review

Hi Board designers, 

Please refer below

General

• Processor

1. Not following the data sheet recommendations
2. Not following the processor specific design guidelines
3. Not reviewing the design with respect to the schematics review check list
4. Not reviewing and following the D-Notes and R-Notes added to the schematics
5. Not reviewing the FAQs and following the FAQ recommendations during design
6. Copying schematic sections partially (missing or deleted information) 

• Schematics

1. Block diagram added on the schematics is updated to match the updated schematics
2. Ordering part numbers not updated for Key components including processor
3. Adding too many sections (functional) block in a single page
4. Check all symbol pinouts against the datasheet, even if you have used the IC before or trust the symbol source.
5. Missing page names or page names does not match the sections in the schematics
6. Title block completed for each sheet?
7. All components have reference designators and right values?
8. Dot on each wire connection?
9. Tolerance not enabled for resistor that have 1% requirements – recommend enabling
10. Processor symbol net names different from the data sheet names
11. Missing symbols for processor sections that are not used
12. Mis-placed comments and error in the reference designators mentioned
13. Schematics reference designator not sequenced or aligned
14. All DNI components populated due to schematics reuse and resetting of the DNI configuration
15. GPIO mapping errors due to deletion of IO expander used on the SK
16. PMIC supply rails not connecting to processor supply rails since the net names are different due to deletion of shunts provided on the SK
17. Mating connectors on different assemblies checked for same pinout?
18. Test points on PCBs for critical circuits
19. Bypass (decoupling) capacitor not provided for each IC
20. Place a decoupling capacitor adjacent to each power pin on connectors to mitigate power supply noise
21. Orientation of diodes and LEDs to ensure proper functionality. Value of the LED current limit resistor to ensure minimum current (~2mA)
22. Have all the current limiting resistors been correctly calculated for each LED's forward voltage?
23. All components have reference designators, values, voltage rating and tolerance enabled
24. Schematics printed at a readable scale and searchable 

• Data Sheet

1. Not following the Pin connectivity requirements as per the device specific data sheet for peripherals that are used and peripherals that are not used
2. Using older revision and not using the latest revision of the data sheet and TRM
3. Not reading the revision history of the data sheet and making updates to the design as required 

• Component selection

1. Voltage rating of the caps not following general derating guidelines
2. Voltage rating of 6.3V used for 3.3V (use 10V) and 5V (use 16V) supply rails
3. Tolerance 0.1% or 5% used for resistors that have 1% tolerance requirements
4. 1% tolerance used for series and parallel pulls - ok to use 5%
5. Resistor value R used for pullup or pulldown
6. Polarized components checked?
7. Ensure resistors are operating within their specified power rating plus safety.
8. Evaluate if any component values across the design can be standardized to reduce the number of unique items on the BOM 

• Collaterals

1. Using older version/revision and not using the latest revision and version of SK/EVM design files on TI.com
2. Not reviewing the Errata for any possible updates during design and after design
3. Not reviewing the available FAQs (Master list available Sitara family wise and Sitara families) and following the FAQs during custom board design
4. Performing Self-review of the custom board schematics
5. Reviewing Design Package Content Overview on specific EVM/SK, reviewing the available files and reuse as required 

• Circuit optimization

1. Deleted required sections or not copying all the required sections when SK or EVM design schematics is reused
2. Make sure the newly added schematic is properly simulated or logically evaluated for proper functionality
3. Optimization of the circuit sections done without detailed analysis of the circuit function
4. IO level compatibility issues due to circuit optimization
5. Alternate approaches used - D-Notes and R-Notes added on the schematics not reviewed before optimizing the SK implementation
6. Memory or peripheral reset logic not implemented or implement following alternate approaches - this needs to be verified by customer
7. Check the datasheet fine print and app notes before optimizing 

Board Power

• Power Estimation

1. Has the power distribution network been analyzed for a total load? Can the regulators supply this load?
2. Have you referenced to the available collaterals and tools?
3. Should any subsystems have isolated supplies?
4. Should any subsystems have separately regulated supplies?
5. Does each voltage regulator’s output meet the precision requirements for the subsystems connected to it?
6. Is the total capacitance connected to each regulator within its ability to supply?
7. Is there sufficient input capacitance on each regulator to prevent reverse supply under changing loads?
8. Are any input voltages to regulators able to drop below the regulator’s minimum operating voltage?
9. Is there a LDO between attached devices (loads) that need filtered supply and a switched mode regulator power source? 

• PMIC

1. Selection of the PMIC part number and updating the OPN in the schematics
2. PMIC input connected as SOC IO input - this is not allowed or recommended as the other supplies may not be available for a long duration
3. Not following the processor IO supply power sequencing - load switch enabled by PMIC IO
4. Connection of RESETSTATz to Mode/Reset input - this is optional and can be isolated
5. Connection of the DC/DC Output feedback
6. DC/DC output Bulk capacitors value not as per the recommendation
7. DC/DC output supply rails and the SOC or IO supply rails name mis-match
8. Capacitor voltage rating - 6.3V used for 5V or 6.3V used for 3.3V or 10V used for 5V
9. Slow slew open drain PMIC nRSTOUT connected directly to MCU_PORz input
10. Missing provision to isolate the output rails (0Ω or Jumper)
11. Package size selection of the isolation resistor (output rails (0Ω) based on the current capability of the supply rail
12. Missing test points on all supply rails  

• Discrete

1. Not following the processor power sequencing including the 9.5 ms delay for the MCU_PORz low->high after all the supplies ramp
2. DC/DC output configuration errors - resistor divider values and tolerance
3. DC/DC output feedback configuration
4. DC/DC output slew rate vs processor slew rate requirement
5. Output Bulk capacitors value
6. DC/DC output supply rails and the SOC or IO supply rails name mismatch
7. Capacitor voltage rating - 6.3V used for 5V or 6.3V used for 3.3V or 10V used for 5V
8. Pullups added for the PG outputs and a TP provided for testing
9. Missing provision to isolate the output rails (0Ω or Jumper)
10. Package size selection of the isolation resistor (output rails (0Ω) based on the current capability of the supply rail 

Processor

• Power

1. Supply voltage connected is out of the range of the processor ROC
2. Verify power sequencing requirements for processor and attached devices
3. A different supply voltage rail is connected to the processor supply rails
4. Supply slew rate when discrete power solution is used
5. Power supply connections not following the pin connectivity requirements for peripherals that are not used
6. Connection of core supplies when VDDR_CORE is 0.75V or 0.85V
7. Using separate power sources for VDD_CORE and VDDR_CORE when core is operating at 0.85V
8. Ferrite filters note used for peripheral cores and analog supplies
9. Adequate bulk and decoupling capacitors not provided - followed SK or simulation performed
10. 3-T caps not used
11. 4V caps used for 3.3V supply rail when 3-T caps are used
12. Check maximum power dissipation at worst-case operating temperatures? 

• VPP

1. Supply voltage 1.8V connected permanently to VPP pin
2. Load transient response outside the processor ROC
3. Cap 2.2uF + 0.1uF not used near to the VPP when external supply option is used
4. FET or load switch used to control power to the VPP pin
5. Timing of the external supply not controlled by the SOC IO
6. Provision to isolate the LDO output connected to VPP supply pin not provided
7. VPP supply LDO EN does not have a pulldown to disable during reset
8. Output protection Zener not provided when variable LDO is used
9. FAQ not reviewed during design 

• User interface

1. Not following the pin connectivity requirements when CSI0 interface is not used
2. Connection of the CSI0 RXRCALIB DSI0 TXRCALIB resistor including value and tolerance
3. Connection of series resistor 0Ω (not provided) for the DPI PCLK
4. Not following the pin connectivity requirements when OLDI0 is not used
5. Not following the pin connectivity requirements when DSI0 is not used
6. Reversal of differential data pairs (Example OLDI0 connects to OLDI3)
7. polarity reversal of differential signals (P and N interchanged) 

• Peripherals

1. Check for input voltages applied with board or processor being powered off
2. Pullups on all open drain outputs (4.7K, adjust after testing). A pullup is recommended for the MCU_I2C0 and WKUP_I2C0 I2C open-drain output interfaces irrespective of the IO configuration
3. Open-drain output I2C interfaces, when pull to 3.3V IO level have slew rate requirements specified. An external RC is recommended to limit the slew rate.
4. Pullups not added when emulated I2C interface signals are configured as I2C interface (4.7K, adjust after testing)
5. Series resistor to limit the fall time not added when emulated I2C interface signals are configured as I2C interface
6. Series resistor 22Ω not added for the McSPI or McASP clock output signal near to the processor pin
7. Parallel pulls not added for McSPI or McASP interface signals that could float (processor or attached device)
8. No series resistor added on the UART interface signals for isolation
9. No parallel pulls added on the UART interface signals that could float
10. External inputs are available on the UART interface before the processor supply ramps causing residual voltage
11. Fail-safe operation and IO level compatibility when attached devices on the carrier board are interfaced to the SOC
12. Using 0Ω as pullup or pulldown including configuring the address (Could cause supply short)
13. All unused inputs terminated as per the recommendations
14. Decoupling capacitors added for all the ICs close to the device
15. Have all pins on each integrated circuit (IC) been accounted for in the design?
16. Verify the target I2C interface clock rates. The I2C bus can only be operated as fast as the slowest peripheral on the bus. If faster operation is required, move the slow devices to another I2C port.
17. Verify that there are no I2C address conflicts on any of the I2C interface utilized. There are multiple I2C ports available on the processor, so if a conflict is seen, move the conflicting devices to a different I2C bus. If this is not possible, use an I2C bus switch
18. Do not place more than one set of pull-up resistors on the I2C lines. This could result in excessive loading and potential incorrect operation. Choose the pull-up value as per the bus speed being used.
19. Ensure that the supply rail powering the processor I2C IO supply group matches the supply voltage used for the pull-up resistors and the attached I2C devices. Proper pullup can prevent device damage or incorrect operation due to voltage mismatch                            

• Debug

1. Provision for UART debug provided without external ESD protection or parallel pulls
2. JTAG interface provided without pullups and pulldowns added
3. Pulls added near to the connector (place near to the SOC)
4. External ESD protection provision not provided near to the interface connector
5. Capacitor filter not added on the JTAG interface for the supply pin                            

• GPIO interface

1. SOC IO buffers are off during reset. Parallel pulls not provided for SOC or attached device that could float
2. Capacitance and fan out limits checked for IOs
3. Connection of capacitors at the LVCMOS input causing the input signal slew to increase (slew should be <1000ns)
4. Connection of capacitors at the LVCMOS output - Perform simulation when value of >22pF is used
5. Fail-safe operation - External inputs applied before the SOC supply ramps
6. External inputs connected directly - without external ESD protection. All outside world I/O lines protected against static discharge?
7. External input slew (<1000 ns)
8. External input pullup IO supply mismatch with the processor IO supply group voltage level
9. GPIOs - TPs or Traces connected to a connector and not being driven
10. When not used, leave the GPIOs or the pads unconnected
11. Pullup value of 100K used compared to 10K or similar (Consider IO leakage current and effect on the IO level)
12. Is there a provision for breaking out extra pins from ICs or subsystems for future expansion or testing?
13. Ensure I/O pins include pullup or pulldown resistors to define a default state when disconnected, enhancing circuit stability. 

• Clock

1. WKUP_LFOSC0 connections when not used
2. WKUP_LFOSC0 load cap and crystal load selection and configuration
3. WKUP_LFOSC0 Series and parallel resistors not connected as per data sheet recommendations
4. MCU_OSC0 crystal connected through series or parallel resistor – connecting directly is recommended
5. MCU_OSC0 load cap and crystal load selection
6. MCU_OSC0 XO connection when LVCMOS clock is used
7. Crystal frequency other than 25M used (Ex 24Mhz) – this is not supported currently
8. External oscillator supply caps (bulk + decoupling capacitors)
9. Series resistor added at the output of the clock
10. Capacitor added at the output of the clock – this is not recommended
11. Clock output series resistor not added
12. Clock output not buffered when connected to multiple loads
13. Pull not provided near to the attached device clock input that could float when the processor clock output is not configured (CLKOUT0)
14. Connection of WKUP_CLKOUT0 to attached devices – AM625 and AM62A WKUP_CLKOUT0 provides a 25MHz clock output during reset and this could affect the functionality.                           

• Bootmode

1. Shorting of bootmode inputs directly to ground or supply
2. Leaving unused bootmode inputs open (not connected)
3. Bootmode resistor divider configuration and values
4. External ESD protection not provided when dip switches are used for configuration
5. Connection of bootmode configuration resistor divider to valid supply
6. Bootmode buffer from the SK schematics are reused – optional. This is required to implement test automation.
7. Separate pullup/Pulldown for all bootmode pins with configuration capability not provided (to allow modes to be changed if needed?                            

• Reset

1. Slew rate of the cold reset input MCU_PORz when PMIC output or external input is connected
2. SOC Reset inputs glitch-free during power-up
3. 22pF filter cap not added as a provision for MCU_PORz input
4. Connection of warm reset inputs when not used
5. RESET behavior if power cycles before the circuit is fully operational? (Residual voltage check)
6. Implementation of Schmitt trigger based debouncing logic when manual reset is implemented through a push-button
7. Connection of warm reset RESETSTATz for resetting the peripherals - recommended
8. Pull down added at the output of Cold and warm reset output to hold the attached device in reset during power-up and reset
9. Addition of pullups for reset status output (not recommended)
10. Are the external reset input signals properly filtered to avoid unintentional resets due to noise?             

• Diagnostics

1. Implementation of VMON_VSYS using external resistor divider and a filter cap
2. Connection of 5V or higher voltage to implement VMON_VSYS
3. Connection of voltage monitor pins when not used as per pin connectivity requirements
4. Filter cap connected to VMON_3P3_SOC and VMON_1P8_SOC - recommendation is to connect directly             

• Reserved Pins

1. Internal names used for reserved pins
2. TPs and Trace connected to reserved pins - follow data sheet recommendations 

Memory

• DDRSS

1. Connection of reset pulldown including value and placement - for LPDDR4 and DDR4
2. Connection of Cal0 resistor including value, tolerance and placement - for LPDDR4 and DDR4
3. Connection of ZQ0..1 resistor including value, tolerance and placement - for LPDDR4 and DDR4
4. Differential clock termination resistor and filter capacitor values different for DDR4
5. DDR4 REFCA voltage generation resistor divider value and tolerance different (1K, 1%) when VTT termination LDO is not used
6. VTT termination resistor divider value, tolerance (1K, 1%, recommended) and filter cap values different when VTT terminations are used including number of filter caps - EVM or SK not followed
7. VTT termination LDO configuration as per the device data sheet recommendations not followed including addition of capacitors
8. Parallel busses haven’t been reversed? For buses, ensure processor bus order matches device order?                            

• eMMC

1. Series resistor OR not provided for clock output near to the SOC pin
2. Pulldown resistor 10K close to the memory device clock input not provided for processor implementing soft eMMC PHY
3. Errors in Implementation of the reset logic and IO level compatibility
4. Pullups for D0 and CMD for processor implementing soft eMMC PHY not provided.
5. Pullups for D1..D7 enabled.
6. Resistors 49.9K 1% used for pullups. Use standard resistor values 47K or similar for pullups
7. Supply source different for attached device (Memory) and processor IO
8. Adequate bulk and decoupling capacitors not added
9. Parallel busses (lines) haven’t been reversed? For buses, ensure processor bus order matches device order? 

• OSPI

1. Addition of series resistor 0Ω for clock output near to the SOC pin
2. Addition of pulldown resistor 10K close to the memory device clock input
3. Pullups not provided for the data signals.
4. Implementation of the reset logic and IO level compatibility
5. Same supply source connected to Memory and processor IO
6. Connection of loopback clock and DQS
7. Addition of adequate bulk and decoupling capacitors
8. Connection to multiple attached devices – this is not recommended
9. Attached device chosen without hardware reset pin – choosing memory device with reset pin is recommended
10. Parallel busses haven’t been reversed? For buses, ensure processor bus order matches device order? 

• SD card

1. Addition of pulldown resistor 10K close to the memory device clock input
2. Addition of series resistor OR for clock output near to the SOC pin
3. Addition of pullup 47K and IO supply connection based on the SD card speed
4. Processor IO supply group supply for SD card (VDDSHV5) and SD card supply connected to 1.8V (3.3V recommended for legacy and 1.8V/3.3V for VDDSHV5, SD card supply always connects to 3.3V)
5. SD card UHS-I implementation - IO voltage switching (3.3V/1.8V) provision not provided or implemented wrongly
6. IO voltage switching implemented using load switches vs LDO
7. SD card UHS-I implementation - SD card power supply power switch
8. SD card UHS-I implementation - SD card power supply power switch reset logic
9. Using a level shifter and connecting the SD card interface IO pullup supply and SD card supply to 3.3V
10. Addition of adequate bulk and decoupling capacitors
11. SD card power switch slew rate control configuration
12. SDCD ground not connected on the SOC side
13. SDCD ground connected directly (add a series resistor)
14. Parallel busses haven’t been reversed? For buses, ensure processor bus order matches device order? 

Attached devices

• Ethernet

1. EPHY MAC interface implementation including series resistor not provided
2. EPHY PHY address configuration not done when more than 1 EPHY is used
3. Pullup for MDIO interfaced not placed near to the EPHY and for each of the EPHY
4. EPHY clock spec not matched with the processor clock
5. EPHY reset not provided for individual EPHYs
6. Pulldown not provided near to the EPHY reset input
7. The required bulk and decoupling capacitors have not been added
8. Buffering of the clock when RMII interface is used
9. MDIO MDC pullup provided (Verify the EPHY recommendations)
10. Parallel busses haven’t been reversed? For buses, ensure processor bus order matches device order?                            

• USB

1. Configuration of USB interface - Host or Device
2. Provision for USB over load protection switch when USB is configured for Host
3. Power switch with OC indication not used
4. Power switch OC output not connected to processor IO
5. VBUS divider added when the USB interface is configured for host - this is optional
6. Recommended capacitor value not connected near to the USB connector in host mode
7. VBUS divider as per the data sheet provided when the USB interface is configured as device
8. VBUS divider resistor value and tolerance as per data sheet recommendations
9. 0Ω used on the USB interface signals - this is not recommended
10. Provision to bypass the common mode choke not provided
11. External ESD protection for the USB interface signals not added
12. ESD protection should be implemented at the connector pins. Choose a ESD protection device with low-capacitance
13. recommended for high-speed interfaces.
14. Mounting of USBx_RCALIB resistor and value when USB interface is used
15. Mounting of USBx_RCALIB resistor when USB interface is not used and USB IO, core and analog supplies are connected 
16. Mounting of USBx_RCALIB resistor when USB interface is not used and USB IO, core and analog supplies are connected to VSS
17. Polarity reversal of D+ and D- vs design requirements 

• SERDES0

1. Connection of SERDES0 REXT resistor and SERDES0 supplies when boundary scan is required and SERDES0 is not used
2. The differential transmitters from the processor must be AC coupled. Connection of coupling capacitors for TX and location
3. The differential receiver is expected to have the AC coupling capacitor near to the source.
4. Connection of clock parallel terminations when processor is sourcing the clock. The reference clock source should have a HCSL (High-Speed Current-Steering Logic) differential      output. Resistors of approximately 50 Ω are required to terminate both traces to GND. Do not AC couple the clock. 

Additional guidelines for reference

• Final Review and Documentation

1. Check if all the requirements (high-level documentation) are translated into design
2. Functional Grouping: Place components that are functionally related close to each other.
3. Reset circuit design checked (glitch-free, timing and consistent operation) including pull (pulkup or pulldown)
4. Check slew rates of the inputs connected to SOC inputs and loading for the SOC outputs
5. Voltage ratings of capacitors and power rating for resistors
6. All unused inputs as per the recommendations
7. Unpopulated parts annotated in the schematics
8. Avoid direct connect of address configuration pins, SOC IO, mode configuration pins
9. Add necessary TPs for the SOC signals used for debug, testing or characterization
10. Schematics Name, revision, changes, filename on each sheet updated
11. Consistent character size for readability on the schematics
12. Block diagram is available and consistent with the schematic (characteristics and signals flow)
13. Perform a final design rule check (DRC) to identify any layout errors, verifying design rules and constraints.
14. Bill of Materials (BOM) for accuracy (populate, no-populate, tolerance, package, each component has quantity, reference designator and description) and completeness, ensuring that all components including description are correctly specified including availability
15. Generate and review Gerber files for manufacturing readiness, verifying that all layers, drill files, and assembly drawings are correct and complete.
16. Create detailed assembly drawings (reference designators searchable), includes dimensions, and instructions including providing clear guidance for assembly, inspection and testing
17. Conduct a design review with the team to verify all aspects of the board design, including schematic, layout, DFM, and compliance with standards and adhering to best practices. 

• Simulations

1. Follow general High-Speed Routing Guidelines available on the product folder or other documents
2. PCB Stackup design includes reference planes for high speed routing layers
3. Trace width, Trace clearance guidelines followed
4. Impedance Control during PCB Design (marked on the schematics)
5. Power integrity checks including addition of adequate Bulk and high frequency cap, filters. voltage rating and current rating
6. Signal Integrity and Power Integrity simulations performed on the custom board
7. Compliance to Standards and Best Practices

Regards,

Sreenivasa

Hi TI experts,

Is there an excel version of the List of errors observed during customer schematics review

Hi Board designers, 

Please refer below

Common_Errors_Customer_Schematics_02_24_2025.xlsx

Regards,

Sreenivasa