TDA4VM-Q1: Does J721e Support SGMII MAC Port in Native Ethernet Driver?

Update Question :
For the J721e native Linux SDK, does it support configuring three SGMII ports on the CPSW9G Ethernet Switch?

Hi,

Jay Sun said:

For the J721e native Linux SDK, does it support configuring three SGMII ports on the CPSW9G Ethernet Switch?

Yes, SDK support CPSW Driver am65-cpsw-nuss for SGMII Mode but, device tree overlay is not present in SDK for configuring cpsw ports & SerDes in SGMII.

If you want to enable SGMII, need to update CPSW ports & Serdes for SGMII.

Best Regards,
Sudheer

Hi Sudheer,

Yes, I want to enable three SGMII ports, as shown in the topology below. Could you please share how to complete the update of CPSW ports & Serdes for SGMII?

BR
Jay

Hi,

Please refer to the other SerDes nodes, how thay are configured in j721e-common-proc-board.dts file.

Please refer to below as reference to enable SerDes4 for SGMII on Lane-0,1,2.

&serdes_ln_ctrl {
	idle-states = <J721E_SERDES0_LANE0_QSGMII_LANE1>, <J721E_SERDES0_LANE1_QSGMII_LANE2>,	/* port1, port2 */
		      <J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>,
		      <J721E_SERDES2_LANE0_IP1_UNUSED>, <J721E_SERDES2_LANE1_USB3_1>,
		      <J721E_SERDES3_LANE0_IP1_UNUSED>, <J721E_SERDES3_LANE1_IP1_UNUSED>,
		      <J721E_SERDES4_LANE0_QSGMII_LANE5>, <J721E_SERDES4_LANE1_QSGMII_LANE6>,
		      <J721E_SERDES4_LANE2_QSGMII_LANE7>, <J721E_SERDES4_LANE3_QSGMII_LANE8>;	/* port 8 */
};


&serdes4 {
	status = "okay";
	assigned-clocks = <&serdes4 CDNS_SIERRA_PLL_CMNLC>;
	assigned-clock-parents = <&wiz4_pll0_refclk>;
	
	serdes4_sgmii_link: phy@0 {
		reg = <0>;
		cdns,num-lanes = <3>;
		#phy-cells = <0>;
		cdns,phy-type = <PHY_TYPE_SGMII>;
		resets = <&serdes_wiz4 1>, <&serdes_wiz4 2>, <&serdes_wiz4 3>;
	};
};

CPSW Port-8 enabled in SGMII for reference, please configure the required ports as similar.

&cpsw0_port8 {
	phy-handle = <&cpsw9g_phy6>;
    phy-mode = "sgmii";
	mac-address = [00 00 00 00 00 00];
	phys = <&cpsw0_phy_gmii_sel 8>, <&serdes4_sgmii_link>;
	phy-names = "portmode", "serdes";
};

SerDes4 by default support SGMII configuration no need to make any changes to SerDes driver
But, need to update device tree for SerDes4 i.e. take care of below.

You need to change the compatible name and parent-clock for SerDes4 as below from "k3-j721e-main.dtsi" file.

1. Make the compatible string forserdes_wiz4 node as : "ti,j721e-wiz-10g"
2. Make the compatible string for serdes as : "ti,j721e-serdes-10g"
3. Change assigned clock parent as "assigned-clock-parents = <&k3_clks 297 13>;"
4. Comment out "assigned-clock-rates = <19200000>;" from "serdes_wiz4" node.

Update SerDes4 as below.

	serdes_wiz4: wiz@5050000 {
		compatible = "ti,j721e-wiz-10g";
		#address-cells = <1>;
		#size-cells = <1>;
		power-domains = <&k3_pds 297 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 297 1>, <&k3_clks 297 9>, <&cmn_refclk>;
		clock-names = "fck", "core_ref_clk", "ext_ref_clk";
		assigned-clocks = <&k3_clks 297 9>;
		assigned-clock-parents = <&k3_clks 297 13>;
		num-lanes = <4>;
		#reset-cells = <1>;
		ranges = <0x5050000 0x0 0x5050000 0x10000>,
			<0xa030a00 0x0 0xa030a00 0x40>;

		wiz4_pll0_refclk: pll0-refclk {
			clocks = <&k3_clks 297 9>, <&cmn_refclk>;
			clock-output-names = "wiz4_pll0_refclk";
			#clock-cells = <0>;
			assigned-clocks = <&wiz4_pll0_refclk>;
			assigned-clock-parents = <&k3_clks 297 9>;
		};

		wiz4_pll1_refclk: pll1-refclk {
			clocks = <&k3_clks 297 9>, <&cmn_refclk>;
			clock-output-names = "wiz4_pll1_refclk";
			#clock-cells = <0>;
			assigned-clocks = <&wiz4_pll1_refclk>;
			assigned-clock-parents = <&k3_clks 297 9>;
		};

		wiz4_refclk_dig: refclk-dig {
			clocks = <&k3_clks 297 9>, <&cmn_refclk>;
			clock-output-names = "wiz4_refclk_dig";
			#clock-cells = <0>;
			assigned-clocks = <&wiz4_refclk_dig>;
			assigned-clock-parents = <&k3_clks 297 9>;
		};

		wiz4_cmn_refclk_dig_div: cmn-refclk-dig-div {
			clocks = <&wiz4_refclk_dig>;
			#clock-cells = <0>;
		};

		wiz4_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
			clocks = <&wiz4_pll1_refclk>;
			#clock-cells = <0>;
		};

		serdes4: serdes@5050000 {
			/*
			 * Note: we also map DPTX PHY registers as the Torrent
			 * needs to manage those.
			 */
			compatible = "ti,j721e-serdes-10g";
			reg = <0x5050000 0x10000>,
			      <0xa030a00 0x40>; /* DPTX PHY */
			reg-names = "torrent_phy", "dptx_phy";

			resets = <&serdes_wiz4 0>;
			reset-names = "torrent_reset";
			clocks = <&wiz4_pll0_refclk>;
			clock-names = "refclk";
			#address-cells = <1>;
			#size-cells = <0>;
		};

Best Regards,
Sudheer

Hi Sudheer,

After I modify "j721e-common-proc-board.dts" and "k3-j721e-main.dtsi" according to the steps you mentioned, could I confirm whether my configuration is correct on the J721e EVM? Currently, I can only see eth0 show.
Also, do I need to enable overlay in uEnv.txt?

Best Regards,

Jay.

Hi,

Jay Sun said:

Also, do I need to enable overlay in uEnv.txt?

Yes, if you have enabled CPSW node and Port configuration from overlay.

Best Regards,
Sudheer