[FAQ] AM625 / AM623 / AM62A / AM62P / AM62D-Q1 / AM64x / AM243x Design Recommendations / Custom board hardware design - Data sheet Pin Attributes and Pin connectivity related queries

Part Number: AM625

Tool/software:

Hi TI Experts,

I have the below query regarding the data sheet

Pin attributes

Pin attributes

I have a number of IOs that are not used, is there a connection recommendation

Is there a recommendation for the supply rails connection?

Description of different columns of the pin attributes table

Is there a connection recommendation when traces are connected to the SOC IOs (pads)

Is there a recommended value to be used?

Pin connectivity

In the pin connectivity table there are recommendations to connect separate external pull resistors for different IOs, is there a recommended value

  • Hi Board designers, 

    Refer below:

    Pin attributes

    I have a number of IOs that are not used, is there a connection recommendation

    Peripherals that have a dedicated function have connectivity requirements when not used. Refer to the Pin Connectivity Requirements section of processor-specific data sheet for connecting unused peripherals. The connectivity requirements include recommendations to connect the power supplies and the interface signals.

    Peripherals (processor IOs) that have alternate functions, when not used can be left unconnected when there are no connectivity requirements specified. The pad configurations can be the reset state configuration.

    Additionally, refer Note at the end of Connectivity Requirements section.

    Is there a recommendation for the supply rails connection?

    Refer to the Note at the start of Pin Connectivity Requirements section.

    Description of different columns of the pin attributes table

    Refer to the description list at the start of Pin Attributes section.

    Is there a connection recommendation when traces are connected to the SOC IOs (pads)

    When a trace is connected to the processor pads and is not actively driven, a parallel pull is recommended. Pull polarity is design use case dependent. During power-up, processor IO buffers are off and the IOs are in a high impedance state, effectively serving as an antenna that picks up noise. Without any termination, the IOs are high impedance. High impedance means, easy for noise to couple energy on the floating signal trace and develop a potential that can exceed the recommended operating conditions, which creates an electrical over-stress (EOS) on the IOs. Electrostatic discharge (ESD) protection circuits inside the processor are designed to protect the device from handling before being installed on a PCB assembly.

    The recommendation is to add external pulls for any IO that has a trace connected

    If there are few IO that have test points (TPs) and adding external parallel pulls are not feasible, place and route them away from noisy signals

    Is there a recommended pull value to be used?

    Refer below.

    Pin connectivity

    In the pin connectivity table, there are recommendations to connect separate external pull resistors for different IOs, is there a recommended value

    The IO cells associated with these pins are always configured as inputs and there is no internal pull option, so they must always be pulled or driven to a valid logic level by an external source.

    The value of the pull will depend on the trace length connected to the input and the worst-case electrical noise environment expected for the product.  The customer needs to select a resistor value that will not allow noise to change the logic state of the signal.  They may be able to use a 47k pull if they keep the signal trace short and placing the resistor near the processor. The only disadvantage to using a smaller value like 10k or even lower would be the additional power consumption required if it were ever pulled to the other logic state.  However, the smaller value should not have any negative impact if it was simply being used as a permanent tie-off.

    Regards,

    Sreenivasa