TDA3MV: Please confirm whether the sampled data from the AFE5401 can be correctly interfaced with and processed by the TDA3.

HI,

  I greatly appreciate your response.

  We connect DSYNC1 with the HS (horizontal synchronization) signal and DSYNC2 with the VS (vertical synchronization) signal, and they work at different frequencies.

  Best Regards

  Tom

Tom,

Couple of questions, 

- Both DSYNCs are toggling at the same time, same clock cycle, Can you try to delay it by atleast a clock cycle? 

- what is delay phase? Can it be considered as blanking period? 

- are there only two lines in sample phase? 

- there is no line toggling in the blanking line? 

Regards,

Brijesh

Brijesh,

  Both DSYNCx signals are triggered simultaneously, and no provision for adjusting the delay between them is found in the AFE5401 manual.

  The delay phase can be configured to set the delay cycle time, and in addition to this, it also has a blanking phase.

  TRIG serves as the trigger for sampling.

  There are only two lines in sample phase, the DSYNCx signals are used for channel data identification.

  Yes, there is no line toggling in the blanking line.

  Regards

  Tom

Hi Tom,

Tom Zhang said:

  Both DSYNCx signals are triggered simultaneously, and no provision for adjusting the delay between them is found in the AFE5401 manual.

This can potentially create problem in detecting sync signals. 

TRIG will not be used by VIP, VIP uses only two input signals (VS and HS) for capturing the data, so you need to select two signals our of above list. 

Regards,

Brijesh

Hi Brijesh,
If DSYNC1 and DSYNC2 are used as input signals (VS and HS), is it required to delay one cycle between them to capture the data?

Regards

Tom

Hi Tom,

Yes, please keep few cycles of delay between them.

Regards,

Brijesh