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[FAQ] What Ethernet pinmux combinations are valid on AM64x processors?

Daolin Qiu
Genius 11385 points
Part Number: AM6421
Other Parts Discussed in Thread: SYSCONFIG

Tool/software:

The AM64x processor family is able to support a total of 4 PRU_ICSSG Ethernet ports and 2 CPSW Ethernet ports. However, due to pinmux restrictions, only a maximum of 5 Ethernet ports can be configured at a given time. This, in theory, can be any combination of PRU_ICSSG or CPSW Ethernet ports. However, there are potentially additional pinmux restrictions depending on the MAC interface mode that is being used since the number of pins required for each interface mode is different.

For AM64x, the PRU_ICSSG Ethernet ports can be configured in RGMII or MII interface mode and the CPSW Ethernet ports can be configured in RGMII or RMII interface mode. What combination of these interface modes are valid (i.e. do not introduce a pinmux error)?

  • +1
    TI__Genius 11385 points

    What combinations DO NOT work?

    EtherCAT Ethernet ports with a OPCUA port

    • 2 Industrial Ports (MII): PRU_ICSSG1
    • 1 OPCUA Port (RMII): CPSW

    Pinmux Conflict

    The ICSSG1 MDIO only has the option of using "PRG1_MDIO0_MDC" and "PRG1_MDIO0_MDIO"

    The CPSW MDIO has two options 

    MDC: "PRG1_MDIO0_MDC" or "PRG0_PRU1_GPO19"

    MDIO: "PRG1_MDIO0_MDIO" or "PRG0_PRU1_GPO18"

    However, "PRG0_PRU1_GPO19" is already used by CPSW's "RMII1_CRS_DV" signal and "PRG0_PRU1_GPO18" is already used by CPSW's "RMII1_TX_EN" signal.

    "RMII1_CRS_DV" cannot be changed to "PRG1_PRU1_GPO19" and "RMII1_TX_EN" cannot be changed to "PRG1_PRU1_GPO18" because these signals are part of IOSET1 and all other CPSW signals are part of IOSET2.

    According to the datasheet 7.10.5.1 CPSW3G,

    "CPSW3G MDIO0, CPSW3G RMII1, CPSW3G RMII2, and CPSW3G RGMII1 have one or more
    signals which can be multiplexed to more than one pin. Timing requirements and switching
    characteristics defined in this section are only valid for specific pin combinations known as IOSETs.
    Valid pin combinations or IOSETs for these interfaces can be found in the tables of the CPSW3G
    IOSETs section."

    The specifications reported in the datasheet are only valid for the given IOSET configurations. If you choose to mix IOSETs for a given interface, we cannot guarantee the timing requirements and switching characteristics you would expect from the datasheet.

    Note About EtherCAT example

    Just to note, in the EtherCAT example (in Industrial Comms SDK), the SysConfig tool does not show or allow CRS and COL to be associated with PRU_ICSSG1_MII_G_RT. Instead, they are displayed under PRU_ICSSG1_IEP. In other words, the signals PRG1_PRU0_GPO9, PRG1_PRU0_GPO10, PRG1_PRU1_GPO9, and PRG1_PRU1_GPO10 associated with CRS and COL pins are simply labeled "PRU_ICSSG1_IEP.EDIO_DATA_IN_OUT28, PRU_ICSSG1_IEP.EDIO_DATA_IN_OUT29, PRU_ICSSG1_IEP.EDIO_DATA_IN_OUT30, PRU_ICSSG1_IEP.EDIO_DATA_IN_OUT31" in the EtherCAT example.

  • 0 in reply to Daolin Qiu
    TI__Genius 11385 points

    What combinations DO work?

    *Note: Below is not a comprehensive list of all the possible combinations, it is simply listing the most common Ethernet combinations used depending on the use case. More combinations can be added in the future.

    EtherCAT Ethernet ports with a OPCUA port

    Option1:

    • Industrial Port (MII): PRU_ICSSG1
    • OPCUA Port (RGMII): PRU_ICSSG0

    Option 2:

    • Industrial Port (MII): PRU_ICSSG1 (omitting the CRS and COL pins)
    • OPCUA Port (RGMII): CPSW

    On the TI AM64x EVMs, we have the ability to change the ICSSG1 interface mode between MII and RGMII through multiplexing. Specifically, this is enabled in our Linux SDK through a device tree overlay. See this link for the overlay file: https://git.ti.com/cgit/ti-linux-kernel/ti-linux-kernel/tree/arch/arm64/boot/dts/ti/k3-am642-evm-icssg1-dualemac-mii.dtso?h=ti-rt-linux-6.6.y 

    On the TI AM64x EVMs, CPSW RGMII is also enabled at the same time. When using sysconfig tool to check this combination (ICSSG1 MII + CPSW RGMII), the only conflict is the CRS and COL pins on the ICSSG1 MII interface.

    Looking into the device tree overlay pinmux configuration, if ICSSG1 MII was configured, the CRS and COL pins that were causing a conflict with the CPSW RGMII pins were actually not configured at all. After some research, it appears that CRS and COL pins are only really required for half-duplex mode, so that may be the reason why CRS and COL are not configured in the device tree overlay pinmux configuration.

    This indicates that it's possible to configure your setup with the this combination if it can be guaranteed that half-duplex mode will not be used for the ICSSG1 MII interface. This would need to involve changing the Ethernet PHY driver so that it does not advertise half-duplex mode as an option to the link partner as well.