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AM68A: Configure DSI0 For MIPI LCD Display

Part Number: AM68A
Other Parts Discussed in Thread: SK-AM68

Tool/software:

Hello,

We are trying to get a MIPI LCD touchscreen working on a custom board using the AM68A on its DSI0 interface. We're using the Linux SDK v 10.00.08. The LCD touchscreen is a Winstar WF101JSYAHMNB0. So far, we have the backlight working but we see no image on the screen. As a starting point, we modify the kernel driver drivers/gpu/drm/panel/panel-feiyang-fy07024di26a30d.c to include info from manufacturer datasheet and datasheet from output driver (things like timings, power on sequence, and MIPI commands init commands). Linux creates a framebuffer at /dev/fb0 and thinks a panel is connected, however, we are still unable to get even a test image to display. We can run tools like kmstest or run cat /dev/urandom > /dev/fb0 but is has no real effect.

I used my scope and probed the DSI0 clock and data lines. I found no clock and the data lines were floating at about 1V. It was like the DSI0 interface was not properly initialized or something. So now I am back to looking at my device tree and wondering if it is correct with respect to the dss, dsi , and panel nodes. Below is the device tree:

// SPDX-License-Identifier: GPL-2.0
/*
 *
 * Based on SK-AM68 from Texas Instruments.
 * See arch/arm64/boot/dts/ti/k3-am68-sk-board.dts
 */

/dts-v1/;

#include "arm64/ti/k3-j721s2.dtsi"
#include "memory.dtsi"
#include <dt-bindings/net/ti-dp83867.h>
#include <dt-bindings/phy/phy-cadence.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/gpio/gpio.h>

#include "arm64/ti/k3-serdes.h"

/ {
	compatible = "company,product";
	model = "Company Name Product Name";

	chosen {
		stdout-path = "serial3:115200n8";
	};

	aliases {
		serial1 = &main_uart1;
		serial3 = &main_uart3;
	};

	vsys_5v0: regulator-vsys5v0 {
		/* main supply */
		compatible = "regulator-fixed";
		regulator-name = "vsys_5v0";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		regulator-always-on;
		regulator-boot-on;
	};

	vsys_3v3: regulator-vsys3v3 {
		/* Output of LM1086 */
		compatible = "regulator-fixed";
		regulator-name = "vsys_3v3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		vin-supply = <&vsys_5v0>;
		regulator-always-on;
		regulator-boot-on;
	};

	vdd_mmc1: regulator-sd {
		/* Output of TPS22918 */
		compatible = "regulator-fixed";
		regulator-name = "vdd_mmc1";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-boot-on;
		enable-active-high;
		vin-supply = <&vsys_3v3>;
		gpio = <&main_gpio0 50 GPIO_ACTIVE_HIGH>;
	};

	vdd_sd_dv: regulator-tlv71033 {
		/* Output of TLV71033 */
		compatible = "regulator-gpio";
		regulator-name = "tlv71033";
		pinctrl-names = "default";
		pinctrl-0 = <&vdd_sd_dv_pins_default>;
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <3300000>;
		regulator-boot-on;
		vin-supply = <&vsys_3v3>;
		gpios = <&main_gpio0 49 GPIO_ACTIVE_HIGH>;
		states = <1800000 0x0>, <3300000 0x1>;
	};

	vsys_io_1v8: regulator-vsys-io-1v8 {
		compatible = "regulator-fixed";
		regulator-name = "vsys_io_1v8";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
		regulator-always-on;
		regulator-boot-on;
	};

	vsys_io_1v2: regulator-vsys-io-1v2 {
		compatible = "regulator-fixed";
		regulator-name = "vsys_io_1v2";
		regulator-min-microvolt = <1200000>;
		regulator-max-microvolt = <1200000>;
		regulator-always-on;
		regulator-boot-on;
	};

	backlight: lcd-backlight {
		status = "okay";
		compatible = "pwm-backlight";
		pinctrl-names = "default";
		pinctrl-0 = <&backlight_pins_default>;
		pwms = <&main_ehrpwm3 1 1000000 0>;
		brightness-levels = <0 32 64 96 128 160 192 224 255>;
		default-brightness-level = <6>;
	};

};

&main_ehrpwm3 {				// for LCD backlight
	status = "okay";
};

&dphy_tx0 {
	status = "okay";
};

&dss {
	status = "okay";

	assigned-clocks = <&k3_clks 158 2>,
			  <&k3_clks 158 5>,
			  <&k3_clks 158 14>,
			  <&k3_clks 158 18>;
	assigned-clock-parents = <&k3_clks 158 3>,
				 <&k3_clks 158 7>,
				 <&k3_clks 158 16>,
				 <&k3_clks 158 22>;
};

&dss_ports {
    #address-cells = <1>;
    #size-cells = <0>;

    /* DSI */
    port@2 {
        reg = <2>;

        dpi2_out: endpoint {
            remote-endpoint = <&dsi0_in>;
        };
    };
};

&dsi0 {
	status = "okay";

	#address-cells = <1>;
	#size-cells = <0>;
	mipi_panel: panel@0 {
		reg = <0>;
		compatible = "feiyang,fy07024di26a30d";
		avdd-supply = <&vsys_io_1v8>;
		dvdd-supply = <&vsys_io_1v8>;

		reset-gpios = <&main_gpio0 27 GPIO_ACTIVE_LOW>;

		port {
			panel_in: endpoint {
				remote-endpoint = <&dsi0_out>;
			};
		};
	};
};

&dsi0_ports {
	#address-cells = <1>;
	#size-cells = <0>;
	port@0 {
		reg = <0>;
		dsi0_out: endpoint {
			remote-endpoint = <&panel_in>;
		};
	};
	port@1 {
		reg = <1>;
		dsi0_in: endpoint {
			remote-endpoint = <&dpi2_out>;
		};
	};
};

&main_pmx0 {
	//	MIDI
	main_uart3_pins_default: main-uart3-default-pins {
        pinctrl-single,pins = <
            J721S2_IOPAD(0x074, PIN_INPUT, 11) /* (R28) MCAN2_TX.UART3_RXD */
            J721S2_IOPAD(0x078, PIN_OUTPUT, 11) /* (Y25) MCAN2_RX.UART3_TXD */
        >;
    };

	//	TOUCHSCREEN
	main_i2c0_pins_default: main-i2c0-default-pins {
		pinctrl-single,pins = <
			J721S2_IOPAD(0x0e0, PIN_OUTPUT_PULLUP, 0) /* (AH25) I2C0_SCL */
			J721S2_IOPAD(0x0e4, PIN_OUTPUT_PULLUP, 0) /* (AE24) I2C0_SDA */
		>;
	};

	lcd_pins_default: lcd-pins-default {
		pinctrl-single,pins = <
			J721S2_IOPAD(0x06c, PIN_OUTPUT_PULLDOWN, 7) /* (T24) GPIO0_27 - LCD_RST */
		>;
	};

	backlight_pins_default: backlight-pins-default {
		pinctrl-single,pins = <
			J721S2_IOPAD(0x09c, PIN_OUTPUT_PULLUP, 9) /* (T24) ESRPWM3_B */
		>;
	};

	//	FOOTSWITCH BD
	main_i2c1_pins_default: main-i2c1-default-pins {
		pinctrl-single,pins = <
			J721S2_IOPAD(0x0ac, PIN_INPUT, 13) /* (AC25) MCASP0_AXR15.I2C1_SCL */
			J721S2_IOPAD(0x0b0, PIN_INPUT, 13) /* (AD26) MCASP1_AXR3.I2C1_SDA */
		>;
	};

	//	FRONT PANEL
	main_i2c4_pins_default: main-i2c4-default-pins {
		pinctrl-single,pins = <
			J721S2_IOPAD(0x010, PIN_INPUT_PULLUP, 8) /* (AF28) MCAN13_RX.I2C4_SDA */
			J721S2_IOPAD(0x014, PIN_INPUT_PULLUP, 8) /* (AD25) MCAN14_TX.I2C4_SCL */
		>;
	};

	//	SDCARD V_SEL
	vdd_sd_dv_pins_default: vdd-sd-dv-default-pins {
		pinctrl-single,pins = <
			J721S2_IOPAD(0x0c4, PIN_INPUT, 7) /* (AB26) ECAP0_IN_APWM_OUT.GPIO0_49 */
		>;
	};

	//	SDCARD
	main_mmc1_pins_default: main-mmc1-default-pins {
		pinctrl-single,pins = <
			J721S2_IOPAD(0x104, PIN_INPUT, 0) /* (P23) MMC1_CLK */
			J721S2_IOPAD(0x108, PIN_INPUT, 0) /* (N24) MMC1_CMD */
			J721S2_IOPAD(0x100, PIN_INPUT, 0) /* (###) MMC1_CLKLB */
			J721S2_IOPAD(0x0fc, PIN_INPUT, 0) /* (M23) MMC1_DAT0 */
			J721S2_IOPAD(0x0f8, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */
			J721S2_IOPAD(0x0f4, PIN_INPUT, 0) /* (R24) MMC1_DAT2 */
			J721S2_IOPAD(0x0f0, PIN_INPUT, 0) /* (R22) MMC1_DAT3 */
			J721S2_IOPAD(0x0e8, PIN_INPUT, 8) /* (AE25) TIMER_IO0.MMC1_SDCD */
		>;
	};

	//	ATWILC300
	main_wifi_pins_default: main-wifi-default-pins {
        pinctrl-single,pins = <
            J721S2_IOPAD(0x0a0, PIN_OUTPUT_PULLDOWN, 10) /* (AB25) MCASP0_AXR12.SPI2_CLK */
            J721S2_IOPAD(0x0a4, PIN_OUTPUT_PULLUP, 10) /* (T23) MCASP0_AXR13.SPI2_CS0 */
            J721S2_IOPAD(0x0a8, PIN_OUTPUT_PULLDOWN, 10) /* (U24) MCASP0_AXR14.SPI2_D0 */
            J721S2_IOPAD(0x0ac, PIN_INPUT_PULLDOWN, 10) /* (AC25) MCASP0_AXR15.SPI2_D1 */
			J721S2_IOPAD(0x004, PIN_OUTPUT, 7) /* (W25) MCAN12_TX.GPIO0_1 RADIO_RSTN */
            J721S2_IOPAD(0x008, PIN_OUTPUT, 7) /* (AC24) MCAN12_RX.GPIO0_2 RADIO_EN */
            J721S2_IOPAD(0x024, PIN_INPUT_PULLUP, 7) /* (Y28) MCAN16_TX.GPIO0_9 RADIO_INTN */
			J721S2_IOPAD(0x05c, PIN_INPUT, 11) /* (AA26) MCASP2_AXR0.UART1_CTSn */
            J721S2_IOPAD(0x060, PIN_OUTPUT, 11) /* (AC27) MCASP2_AXR1.UART1_RTSn */
            J721S2_IOPAD(0x054, PIN_INPUT, 11) /* (Y27) MCASP2_ACLKX.UART1_RXD */
            J721S2_IOPAD(0x058, PIN_OUTPUT, 11) /* (AA27) MCASP2_AFSX.UART1_TXD */
        >;
    };
	//	DAT/EEPROM SPI
	spi0_dat_eeprom_pins_default: spi0_dat_eeprom-default-pins {
        pinctrl-single,pins = <
            J721S2_IOPAD(0x0d4, PIN_OUTPUT_PULLDOWN, 0) /* (AH27) SPI0_CLK */
            J721S2_IOPAD(0x0cc, PIN_OUTPUT_PULLUP, 0) /* (AE27) SPI0_CS0 */
            J721S2_IOPAD(0x0d0, PIN_OUTPUT_PULLUP, 0) /* (AF26) SPI0_CS1 */
            J721S2_IOPAD(0x0d8, PIN_OUTPUT_PULLDOWN, 0) /* (AG26) SPI0_D0 */
            J721S2_IOPAD(0x0dc, PIN_INPUT_PULLDOWN, 0) /* (AH26) SPI0_D1 */
        >;
    };

	gpio0_pins_default: gpio0-default-pins {
        pinctrl-single,pins = <
			/*	---DAT GPIOS---	*/
            J721S2_IOPAD(0x028, PIN_INPUT, 7) /* (AB24) MCAN16_RX.GPIO0_10 DIT_INT */
            J721S2_IOPAD(0x048, PIN_OUTPUT, 7) /* (AB27) MCASP0_AXR2.GPIO0_18 DIT_RSTN */
            J721S2_IOPAD(0x050, PIN_OUTPUT, 7) /* (W27) MCASP1_AXR2.GPIO0_20 DIT_VAID */
        >;
    };

	//	Analog Board Header SPI
	spi5_analog_board_pins_default: spi5_analog_board-default-pins {
        pinctrl-single,pins = <
            J721S2_IOPAD(0x07c, PIN_OUTPUT_PULLDOWN, 8) /* (T27) MCASP0_AXR3.SPI5_CLK */
            J721S2_IOPAD(0x068, PIN_OUTPUT_PULLUP, 8) /* (U28) MCAN0_RX.SPI5_CS0 */
            J721S2_IOPAD(0x070, PIN_OUTPUT_PULLDOWN, 8) /* (R27) MCAN1_RX.SPI5_D0 */
        >;
    };

};

&wkup_pmx2 {
	//	ETHERNET
	mcu_cpsw_pins_default: mcu-cpsw-default-pins {
		pinctrl-single,pins = <
			J721S2_WKUP_IOPAD(0x02C, PIN_INPUT, 0) /* (B22) MCU_RGMII1_RD0 */
			J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (B21) MCU_RGMII1_RD1 */
			J721S2_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (C22) MCU_RGMII1_RD2 */
			J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D23) MCU_RGMII1_RD3 */
			J721S2_WKUP_IOPAD(0x01C, PIN_INPUT, 0) /* (D22) MCU_RGMII1_RXC */
			J721S2_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (E23) MCU_RGMII1_RX_CTL */
			J721S2_WKUP_IOPAD(0x014, PIN_OUTPUT, 0) /* (F23) MCU_RGMII1_TD0 */
			J721S2_WKUP_IOPAD(0x010, PIN_OUTPUT, 0) /* (G22) MCU_RGMII1_TD1 */
			J721S2_WKUP_IOPAD(0x00C, PIN_OUTPUT, 0) /* (E21) MCU_RGMII1_TD2 */
			J721S2_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (E22) MCU_RGMII1_TD3 */
			J721S2_WKUP_IOPAD(0x018, PIN_OUTPUT, 0) /* (F21) MCU_RGMII1_TXC */
			J721S2_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (F22) MCU_RGMII1_TX_CTL */
		>;
	};

	//	ETHERNET
	mcu_mdio_pins_default: mcu-mdio-default-pins {
		pinctrl-single,pins = <
			J721S2_WKUP_IOPAD(0x034, PIN_OUTPUT, 0) /* (A21) MCU_MDIO0_MDC */
			J721S2_WKUP_IOPAD(0x030, PIN_INPUT, 0) /* (A22) MCU_MDIO0_MDIO */
		>;
	};

	//	PMIC
	wkup_i2c0_pins_default: wkup-i2c0-default-pins {
		pinctrl-single,pins = <
			J721S2_WKUP_IOPAD(0x098, PIN_INPUT, 0) /* (H24) WKUP_I2C0_SCL */
			J721S2_WKUP_IOPAD(0x09c, PIN_INPUT, 0) /* (H27) WKUP_I2C0_SDA */
		>;
	};
};

&main_uart1 {
	status = "okay";
	dmas = <&main_udmap 0xc701>, <&main_udmap 0x4701>;
	dma-names = "tx", "rx"; 
};

&main_spi0 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&spi0_dat_eeprom_pins_default>;
	ti,pindir-d0-out-d1-in;
	ti,spi-num-cs = <4>;

	//	EEPROM
	spidev@0 {
		spi-max-frequency = <24000000>;
		reg = <0>;
		compatible = "rohm,dh2228fv";
	};

	//	DAT
	spidev@1 {
		spi-max-frequency = <24000000>;
		reg = <1>;
		compatible = "rohm,dh2228fv";
	};
};

&main_spi2 {
	status = "okay";
	ti,pindir-d0-out-d1-in;
	ti,spi-num-cs = <1>;
	dmas = <&main_udmap 0xc608>, <&main_udmap 0x4608>;
	dma-names = "tx0", "rx0";

	wilc_spi@0 {
		compatible = "microchip,wilc3000";
		pinctrl-names = "default";
		pinctrl-0 = <&main_wifi_pins_default>;
		spi-max-frequency = <48000000>;
		reg = <0>;
		reset-gpios = <&main_gpio0 1 GPIO_ACTIVE_LOW>;
		chip_en-gpios = <&main_gpio0 2 GPIO_ACTIVE_HIGH>;
		interrupt-parent = <&main_gpio0>;
		interrupts = <9 0>;
		status = "okay";
	};
};

&main_spi5 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&spi5_analog_board_pins_default>;
	ti,pindir-d0-out-d1-in;
	ti,spi-num-cs = <1>;

	//	Analog Board
	spidev@0 {
		spi-max-frequency = <24000000>;
		reg = <0>;
		compatible = "rohm,dh2228fv";
	};
};

&main_gpio0 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&gpio0_pins_default>, <&lcd_pins_default>; //, <&main_i2c0_pins_default>;
};

// Touchscreen comm interface
&main_i2c0 {
	status = "okay";
    pinctrl-names = "default";
    pinctrl-0 = <&main_i2c0_pins_default>;
    clock-frequency = <400000>;

	ili2511: touch@41 {
        compatible = "ilitek,ili2511";
        reg = <0x41>; /* I2C address */
		interrupt-parent = <&main_gpio0>;
        //interrupts = <0 0 IRQ_TYPE_EDGE_FALLING>;
        interrupts = <0 0>;
        reset-gpios = <&main_gpio0 25 GPIO_ACTIVE_LOW>; /* reset GPIO */
        touchscreen-size-x = <1024>;
        touchscreen-size-y = <600>;
        //touchscreen-inverted-x;
        //touchscreen-inverted-y;
        //touchscreen-swapped-x-y;
    };
};

&wkup_i2c0 {
	bootph-all;
	clock-frequency = <400000>;
	pinctrl-names = "default";
	pinctrl-0 = <&wkup_i2c0_pins_default>;
	status = "okay";

	lp8733: pmic@60 {
		compatible = "ti,lp8733";
		reg = <0x60>;
		buck0-in-supply = <&vsys_3v3>;
		buck1-in-supply = <&vsys_3v3>;
		ldo0-in-supply = <&vsys_3v3>;
		ldo1-in-supply = <&vsys_3v3>;

		lp8733_regulators: regulators {
			lp8733_buck0_reg: buck0 {
				/* FB_B0 -> LP8733-BUCK1 - VDD_MCU_0V85 */
				regulator-name = "lp8733-buck0";
				regulator-min-microvolt = <850000>;
				regulator-max-microvolt = <850000>;
				regulator-always-on;
				regulator-boot-on;
			};

			lp8733_buck1_reg: buck1 {
				/* FB_B1 -> LP8733-BUCK2 - VDD_DDR_1V1 */
				regulator-name = "lp8733-buck1";
				regulator-min-microvolt = <1100000>;
				regulator-max-microvolt = <1100000>;
				regulator-always-on;
				regulator-boot-on;
			};

			lp8733_ldo0_reg: ldo0 {
				/* LDO0 -> LP8733-LDO1 - VDA_DLL_0V8 */
				regulator-name = "lp8733-ldo0";
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <800000>;
				regulator-boot-on;
				regulator-always-on;
			};

			lp8733_ldo1_reg: ldo1 {
				/* LDO1 -> LP8733-LDO2 - VDA_LN_1V8 */
				regulator-name = "lp8733-ldo1";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
				regulator-always-on;
				regulator-boot-on;
			};
		};
	};

	tps62873a: regulator@40 {
		compatible = "ti,tps62873";
		reg = <0x40>;
		bootph-pre-ram;
		regulator-name = "VDD_CPU_AVS";
		regulator-min-microvolt = <600000>;
		regulator-max-microvolt = <900000>;
		regulator-boot-on;
		regulator-always-on;
	};

	tps62873b: regulator@43 {
		compatible = "ti,tps62873";
		reg = <0x43>;
		regulator-name = "VDD_CORE_0V8";
		regulator-min-microvolt = <800000>;
		regulator-max-microvolt = <800000>;
		regulator-boot-on;
		regulator-always-on;
	};
};

&main_uart3 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&main_uart3_pins_default>;
	/* Shared with TFA on this platform */
	power-domains = <&k3_pds 352 TI_SCI_PD_SHARED>;
};

&main_sdhci1 {
	/* SD card */
	status = "okay";
	pinctrl-0 = <&main_mmc1_pins_default>;
	pinctrl-names = "default";
	disable-wp;
	vmmc-supply = <&vdd_mmc1>;
	//vqmmc-supply = <&vdd_sd_dv>;
	no-1-8-v;
};

&mcu_cpsw {
	pinctrl-names = "default";
	pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>;
};

&davinci_mdio {
	phy0: ethernet-phy@0 {
		reg = <0>;
		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
		ti,min-output-impedance;
	};
};

&cpsw_port1 {
	phy-mode = "rgmii-rxid";
	phy-handle = <&phy0>;
};

&serdes_ln_ctrl {
	idle-states = <J721S2_SERDES0_LANE0_PCIE1_LANE0>, <J721S2_SERDES0_LANE1_PCIE1_LANE1>,
		      <J721S2_SERDES0_LANE2_USB_SWAP>, <J721S2_SERDES0_LANE3_USB>;
};

&serdes_refclk {
	clock-frequency = <100000000>;
};

&serdes0 {
	status = "okay";

	serdes0_pcie_link: phy@0 {
		reg = <0>;
		cdns,num-lanes = <2>;
		#phy-cells = <0>;
		cdns,phy-type = <PHY_TYPE_PCIE>;
		resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>;
	};

	serdes0_usb_link: phy@2 {
		status = "okay";
		reg = <2>;
		cdns,num-lanes = <1>;
		#phy-cells = <0>;
		cdns,phy-type = <PHY_TYPE_USB3>;
		resets = <&serdes_wiz0 3>;
	};
};

&usb_serdes_mux {
	idle-states = <0>; /* USB0 to SERDES lane 2 */
};

&usbss0 {
	status = "okay";
	ti,vbus-divider;
};

&usb0 {
	dr_mode = "peripheral";
	maximum-speed = "high-speed";
	phys = <&serdes0_usb_link>;
	phy-names = "cdns3,usb3-phy";
};

&mailbox0_cluster0 {
	status = "okay";
	interrupts = <436>;
	mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
		ti,mbox-rx = <0 0 0>;
		ti,mbox-tx = <1 0 0>;
	};

	mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
		ti,mbox-rx = <2 0 0>;
		ti,mbox-tx = <3 0 0>;
	};
};

&mailbox0_cluster1 {
	status = "okay";
	interrupts = <432>;
	mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
		ti,mbox-rx = <0 0 0>;
		ti,mbox-tx = <1 0 0>;
	};

	mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
		ti,mbox-rx = <2 0 0>;
		ti,mbox-tx = <3 0 0>;
	};
};

&mailbox0_cluster2 {
	status = "okay";
	interrupts = <428>;
	mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
		ti,mbox-rx = <0 0 0>;
		ti,mbox-tx = <1 0 0>;
	};

	mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
		ti,mbox-rx = <2 0 0>;
		ti,mbox-tx = <3 0 0>;
	};
};

&mailbox0_cluster4 {
	status = "okay";
	interrupts = <420>;
	mbox_c71_0: mbox-c71-0 {
		ti,mbox-rx = <0 0 0>;
		ti,mbox-tx = <1 0 0>;
	};

	mbox_c71_1: mbox-c71-1 {
		ti,mbox-rx = <2 0 0>;
		ti,mbox-tx = <3 0 0>;
	};
};

&mcu_r5fss0_core0 {
	mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
	memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
			<&mcu_r5fss0_core0_memory_region>;
};

&mcu_r5fss0_core1 {
	mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>;
	memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
			<&mcu_r5fss0_core1_memory_region>;
};

&main_r5fss0_core0 {
	mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>;
	memory-region = <&main_r5fss0_core0_dma_memory_region>,
			<&main_r5fss0_core0_memory_region>;
};

&main_r5fss0_core1 {
	mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>;
	memory-region = <&main_r5fss0_core1_dma_memory_region>,
			<&main_r5fss0_core1_memory_region>;
};

&main_r5fss1_core0 {
	mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>;
	memory-region = <&main_r5fss1_core0_dma_memory_region>,
			<&main_r5fss1_core0_memory_region>;
};

&main_r5fss1_core1 {
	mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>;
	memory-region = <&main_r5fss1_core1_dma_memory_region>,
			<&main_r5fss1_core1_memory_region>;
};

&c71_0 {
	status = "disable";
	mboxes = <&mailbox0_cluster4 &mbox_c71_0>;
	memory-region = <&c71_0_dma_memory_region>,
			<&c71_0_memory_region>;
};

&c71_1 {
	status = "disable";
	mboxes = <&mailbox0_cluster4 &mbox_c71_1>;
	memory-region = <&c71_1_dma_memory_region>,
			<&c71_1_memory_region>;
};

&main_r5fss0 {
	status = "disable";
};

&main_r5fss1 {
	status = "disable";
};

Would you please review and comment if this looks correct? I'm not sure what the purpose of connecting ports from dss <--> dsi <-->dsi<-->panel but I copied that approach from other examples I've seen. Is the the dsi0 node an internal bridge? Is the native output of the dss dpi and so if you want dsi output you must route it through the dsi ports as shown?

Any advice you can give would be much appreciated, thanks!

  • Hi,

    This issue has been assigned to our DSI expert on travel. Please expect a delay in getting back to you regarding your query.

    Thanks.

  • Hi Amandio,

    Could you share the logs from "dmesg" so that I can compare with your devicetree?

    Also, could you dump the following registers:

    • 0F08 0108h
    • 0480 00F0h
    • 0480 0140h
    • 0480 0180h

    For reason for why the above registers, so far, I suspect HSYNC miss, since framebuffer is created, but no clock or data lines are coming.

    If you have a scope set to trigger on detecting an edge or a voltage level, there should be one line of the frame that gets transmitted before the clock and data lines go silent if it is a HSYNC issue.

    Regards,

    Takuma

  • Thank you for your response! I'll gather the info you asked for and send it over asap.

    Thanks again!

  • Hi Takuma,

    I keep getting an error when I paste the dmesg log into a code/text window so I've attached it as a text file instead:

    dmesg_out.txt
    [    0.000000] Booting Linux on physical CPU 0x0000000000 [0x411fd080]
    [    0.000000] Linux version 6.6.32-g0315e03d99a0-dirty (amandio@DESKTOP-UJC140B) (aarch64-oe-linux-gcc (GCC) 13.3.0, GNU ld (GNU Binutils) 2.42.0.20240620) #9 SMP PREEMPT Fri Jan 31 14:03:46 EST 2025
    [    0.000000] KASLR disabled due to lack of seed
    [    0.000000] Machine model: Company Name Product Name
    [    0.000000] earlycon: ns16550a0 at MMIO32 0x0000000002830000 (options '')
    [    0.000000] printk: bootconsole [ns16550a0] enabled
    [    0.000000] efi: UEFI not found.
    [    0.000000] Reserved memory: created CMA memory pool at 0x0000000bc8000000, size 896 MiB
    [    0.000000] OF: reserved mem: initialized node linux,cma, compatible id shared-dma-pool
    [    0.000000] OF: reserved mem: 0x0000000bc8000000..0x0000000bffffffff (917504 KiB) map reusable linux,cma
    [    0.000000] OF: reserved mem: 0x000000009e800000..0x000000009fffffff (24576 KiB) nomap non-reusable optee@9e800000
    [    0.000000] Reserved memory: created DMA memory pool at 0x00000000a0000000, size 1 MiB
    [    0.000000] OF: reserved mem: initialized node r5f-dma-memory@a0000000, compatible id shared-dma-pool
    [    0.000000] OF: reserved mem: 0x00000000a0000000..0x00000000a00fffff (1024 KiB) nomap non-reusable r5f-dma-memory@a0000000
    [    0.000000] Reserved memory: created DMA memory pool at 0x00000000a0100000, size 15 MiB
    [    0.000000] OF: reserved mem: initialized node r5f-memory@a0100000, compatible id shared-dma-pool
    [    0.000000] OF: reserved mem: 0x00000000a0100000..0x00000000a0ffffff (15360 KiB) nomap non-reusable r5f-memory@a0100000
    [    0.000000] Reserved memory: created DMA memory pool at 0x00000000a1000000, size 1 MiB
    [    0.000000] OF: reserved mem: initialized node r5f-dma-memory@a1000000, compatible id shared-dma-pool
    [    0.000000] OF: reserved mem: 0x00000000a1000000..0x00000000a10fffff (1024 KiB) nomap non-reusable r5f-dma-memory@a1000000
    [    0.000000] Reserved memory: created DMA memory pool at 0x00000000a1100000, size 15 MiB
    [    0.000000] OF: reserved mem: initialized node r5f-memory@a1100000, compatible id shared-dma-pool
    [    0.000000] OF: reserved mem: 0x00000000a1100000..0x00000000a1ffffff (15360 KiB) nomap non-reusable r5f-memory@a1100000
    [    0.000000] Reserved memory: created DMA memory pool at 0x00000000a2000000, size 1 MiB
    [    0.000000] OF: reserved mem: initialized node r5f-dma-memory@a2000000, compatible id shared-dma-pool
    [    0.000000] OF: reserved mem: 0x00000000a2000000..0x00000000a20fffff (1024 KiB) nomap non-reusable r5f-dma-memory@a2000000
    [    0.000000] Reserved memory: created DMA memory pool at 0x00000000a2100000, size 15 MiB
    [    0.000000] OF: reserved mem: initialized node r5f-memory@a2100000, compatible id shared-dma-pool
    [    0.000000] OF: reserved mem: 0x00000000a2100000..0x00000000a2ffffff (15360 KiB) nomap non-reusable r5f-memory@a2100000
    [    0.000000] Reserved memory: created DMA memory pool at 0x00000000a3000000, size 1 MiB
    [    0.000000] OF: reserved mem: initialized node r5f-dma-memory@a3000000, compatible id shared-dma-pool
    [    0.000000] OF: reserved mem: 0x00000000a3000000..0x00000000a30fffff (1024 KiB) nomap non-reusable r5f-dma-memory@a3000000
    [    0.000000] Reserved memory: created DMA memory pool at 0x00000000a3100000, size 15 MiB
    [    0.000000] OF: reserved mem: initialized node r5f-memory@a3100000, compatible id shared-dma-pool
    [    0.000000] OF: reserved mem: 0x00000000a3100000..0x00000000a3ffffff (15360 KiB) nomap non-reusable r5f-memory@a3100000
    [    0.000000] Reserved memory: created DMA memory pool at 0x00000000a4000000, size 1 MiB
    [    0.000000] OF: reserved mem: initialized node r5f-dma-memory@a4000000, compatible id shared-dma-pool
    [    0.000000] OF: reserved mem: 0x00000000a4000000..0x00000000a40fffff (1024 KiB) nomap non-reusable r5f-dma-memory@a4000000
    [    0.000000] Reserved memory: created DMA memory pool at 0x00000000a4100000, size 15 MiB
    [    0.000000] OF: reserved mem: initialized node r5f-memory@a4100000, compatible id shared-dma-pool
    [    0.000000] OF: reserved mem: 0x00000000a4100000..0x00000000a4ffffff (15360 KiB) nomap non-reusable r5f-memory@a4100000
    [    0.000000] Reserved memory: created DMA memory pool at 0x00000000a5000000, size 1 MiB
    [    0.000000] OF: reserved mem: initialized node r5f-dma-memory@a5000000, compatible id shared-dma-pool
    [    0.000000] OF: reserved mem: 0x00000000a5000000..0x00000000a50fffff (1024 KiB) nomap non-reusable r5f-dma-memory@a5000000
    [    0.000000] Reserved memory: created DMA memory pool at 0x00000000a5100000, size 15 MiB
    [    0.000000] OF: reserved mem: initialized node r5f-memory@a5100000, compatible id shared-dma-pool
    [    0.000000] OF: reserved mem: 0x00000000a5100000..0x00000000a5ffffff (15360 KiB) nomap non-reusable r5f-memory@a5100000
    [    0.000000] Reserved memory: created DMA memory pool at 0x00000000a6000000, size 1 MiB
    [    0.000000] OF: reserved mem: initialized node c71-dma-memory@a6000000, compatible id shared-dma-pool
    [    0.000000] OF: reserved mem: 0x00000000a6000000..0x00000000a60fffff (1024 KiB) nomap non-reusable c71-dma-memory@a6000000
    [    0.000000] Reserved memory: created DMA memory pool at 0x00000000a6100000, size 15 MiB
    [    0.000000] OF: reserved mem: initialized node c71-memory@a6100000, compatible id shared-dma-pool
    [    0.000000] OF: reserved mem: 0x00000000a6100000..0x00000000a6ffffff (15360 KiB) nomap non-reusable c71-memory@a6100000
    [    0.000000] Reserved memory: created DMA memory pool at 0x00000000a7000000, size 1 MiB
    [    0.000000] OF: reserved mem: initialized node c71-dma-memory@a7000000, compatible id shared-dma-pool
    [    0.000000] OF: reserved mem: 0x00000000a7000000..0x00000000a70fffff (1024 KiB) nomap non-reusable c71-dma-memory@a7000000
    [    0.000000] Reserved memory: created DMA memory pool at 0x00000000a7100000, size 15 MiB
    [    0.000000] OF: reserved mem: initialized node c71-memory@a7100000, compatible id shared-dma-pool
    [    0.000000] OF: reserved mem: 0x00000000a7100000..0x00000000a7ffffff (15360 KiB) nomap non-reusable c71-memory@a7100000
    [    0.000000] OF: reserved mem: 0x00000000a8000000..0x00000000a9bfffff (28672 KiB) nomap non-reusable ipc-memories@a8000000
    [    0.000000] Zone ranges:
    [    0.000000]   DMA      [mem 0x0000000080000000-0x00000000ffffffff]
    [    0.000000]   DMA32    empty
    [    0.000000]   Normal   [mem 0x0000000100000000-0x0000000bffffffff]
    [    0.000000] Movable zone start for each node
    [    0.000000] Early memory node ranges
    [    0.000000]   node   0: [mem 0x0000000080000000-0x000000009e7fffff]
    [    0.000000]   node   0: [mem 0x000000009e800000-0x00000000a9bfffff]
    [    0.000000]   node   0: [mem 0x00000000a9c00000-0x00000000ffffffff]
    [    0.000000]   node   0: [mem 0x0000000880000000-0x0000000bffffffff]
    [    0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x0000000bffffffff]
    [    0.000000] psci: probing for conduit method from DT.
    [    0.000000] psci: PSCIv1.1 detected in firmware.
    [    0.000000] psci: Using standard PSCI v0.2 function IDs
    [    0.000000] psci: Trusted OS migration not required
    [    0.000000] psci: SMC Calling Convention v1.4
    [    0.000000] percpu: Embedded 20 pages/cpu s43112 r8192 d30616 u81920
    [    0.000000] pcpu-alloc: s43112 r8192 d30616 u81920 alloc=20*4096
    [    0.000000] pcpu-alloc: [0] 0 [0] 1 
    [    0.000000] Detected PIPT I-cache on CPU0
    [    0.000000] CPU features: detected: GIC system register CPU interface
    [    0.000000] CPU features: detected: Spectre-v3a
    [    0.000000] CPU features: detected: Spectre-BHB
    [    0.000000] CPU features: detected: ARM erratum 1742098
    [    0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
    [    0.000000] alternatives: applying boot alternatives
    [    0.000000] Kernel command line: console=ttyS3,115200n8 earlycon=ns16550a,mmio32,0x02830000 mtdparts=47040000.spi.0:512k(ospi.tiboot3),2m(ospi.tispl),4m(ospi.u-boot),256k(ospi.env),256k(ospi.env.backup),57088k@8m(ospi.rootfs),256k(ospi.phypattern);spi-nand0:512k(ospi_nand.tiboot3),2m(ospi_nand.tispl),4m(ospi_nand.u-boot),256k(ospi_nand.env),256k(ospi_nand.env.backup),98048k@32m(ospi_nand.rootfs),256k@130816k(ospi_nand.phypattern) root=PARTUUID=9dadd190-02 rw rootfstype=ext4 rootwait
    [    0.000000] Dentry cache hash table entries: 2097152 (order: 12, 16777216 bytes, linear)
    [    0.000000] Inode-cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
    [    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 4128768
    [    0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
    [    0.000000] software IO TLB: area num 2.
    [    0.000000] software IO TLB: mapped [mem 0x00000000fbfff000-0x00000000fffff000] (64MB)
    [    0.000000] Memory: 15267576K/16777216K available (12352K kernel code, 1442K rwdata, 4400K rodata, 2752K init, 506K bss, 592136K reserved, 917504K cma-reserved)
    [    0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1
    [    0.000000] rcu: Preemptible hierarchical RCU implementation.
    [    0.000000] rcu: 	RCU event tracing is enabled.
    [    0.000000] rcu: 	RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=2.
    [    0.000000] 	Trampoline variant of Tasks RCU enabled.
    [    0.000000] 	Tracing variant of Tasks RCU enabled.
    [    0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
    [    0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=2
    [    0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
    [    0.000000] GICv3: GIC: Using split EOI/Deactivate mode
    [    0.000000] GICv3: 960 SPIs implemented
    [    0.000000] GICv3: 0 Extended SPIs implemented
    [    0.000000] Root IRQ handler: gic_handle_irq
    [    0.000000] GICv3: GICv3 features: 16 PPIs
    [    0.000000] GICv3: CPU0: found redistributor 0 region 0:0x0000000001900000
    [    0.000000] ITS [mem 0x01820000-0x0182ffff]
    [    0.000000] GIC: enabling workaround for ITS: Socionext Synquacer pre-ITS
    [    0.000000] ITS@0x0000000001820000: Devices Table too large, reduce ids 20->19
    [    0.000000] ITS@0x0000000001820000: allocated 524288 Devices @880800000 (flat, esz 8, psz 64K, shr 0)
    [    0.000000] ITS: using cache flushing for cmd queue
    [    0.000000] GICv3: using LPI property table @0x0000000880040000
    [    0.000000] GIC: using cache flushing for LPI property table
    [    0.000000] GICv3: CPU0: using allocated LPI pending table @0x0000000880050000
    [    0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
    [    0.000000] arch_timer: cp15 timer(s) running at 200.00MHz (phys).
    [    0.000000] clocksource: arch_sys_counter: mask: 0x3ffffffffffffff max_cycles: 0x2e2049d3e8, max_idle_ns: 440795210634 ns
    [    0.000000] sched_clock: 58 bits at 200MHz, resolution 5ns, wraps every 4398046511102ns
    [    0.008407] Console: colour dummy device 80x25
    [    0.012984] Calibrating delay loop (skipped), value calculated using timer frequency.. 400.00 BogoMIPS (lpj=800000)
    [    0.023676] pid_max: default: 32768 minimum: 301
    [    0.028448] LSM: initializing lsm=capability,integrity
    [    0.033793] Mount-cache hash table entries: 32768 (order: 6, 262144 bytes, linear)
    [    0.041584] Mountpoint-cache hash table entries: 32768 (order: 6, 262144 bytes, linear)
    [    0.050787] RCU Tasks: Setting shift to 1 and lim to 1 rcu_task_cb_adjust=1.
    [    0.058061] RCU Tasks Trace: Setting shift to 1 and lim to 1 rcu_task_cb_adjust=1.
    [    0.065932] rcu: Hierarchical SRCU implementation.
    [    0.070842] rcu: 	Max phase no-delay instances is 1000.
    [    0.076558] Platform MSI: msi-controller@1820000 domain created
    [    0.082787] PCI/MSI: /bus@100000/interrupt-controller@1800000/msi-controller@1820000 domain created
    [    0.092217] EFI services will not be available.
    [    0.097002] smp: Bringing up secondary CPUs ...
    [    0.110129] Detected PIPT I-cache on CPU1
    [    0.110178] GICv3: CPU1: found redistributor 1 region 0:0x0000000001920000
    [    0.110193] GICv3: CPU1: using allocated LPI pending table @0x0000000880060000
    [    0.110227] CPU1: Booted secondary processor 0x0000000001 [0x411fd080]
    [    0.110297] smp: Brought up 1 node, 2 CPUs
    [    0.139703] SMP: Total of 2 processors activated.
    [    0.144517] CPU features: detected: 32-bit EL0 Support
    [    0.149782] CPU features: detected: CRC32 instructions
    [    0.155072] CPU: All CPU(s) started at EL2
    [    0.159263] alternatives: applying system-wide alternatives
    [    0.165929] devtmpfs: initialized
    [    0.176686] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
    [    0.186688] futex hash table entries: 512 (order: 3, 32768 bytes, linear)
    [    0.205524] pinctrl core: initialized pinctrl subsystem
    [    0.211235] DMI not present or invalid.
    [    0.215519] NET: Registered PF_NETLINK/PF_ROUTE protocol family
    [    0.222268] DMA: preallocated 2048 KiB GFP_KERNEL pool for atomic allocations
    [    0.229936] DMA: preallocated 2048 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
    [    0.238289] DMA: preallocated 2048 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
    [    0.246527] audit: initializing netlink subsys (disabled)
    [    0.252173] audit: type=2000 audit(0.160:1): state=initialized audit_enabled=0 res=1
    [    0.252389] thermal_sys: Registered thermal governor 'step_wise'
    [    0.260112] thermal_sys: Registered thermal governor 'power_allocator'
    [    0.266285] cpuidle: using governor menu
    [    0.277054] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
    [    0.284038] ASID allocator initialised with 65536 entries
    [    0.297139] platform 4800000.dsi: Fixed dependency cycle(s) with /bus@100000/dss@4a00000
    [    0.305456] platform 4800000.dsi: Fixed dependency cycle(s) with /bus@100000/dsi@4800000/panel@0
    [    0.314723] platform 4800000.dsi: Fixed dependency cycle(s) with /bus@100000/dss@4a00000
    [    0.323046] platform 4a00000.dss: Fixed dependency cycle(s) with /bus@100000/dsi@4800000
    [    0.332198] Modules: 27360 pages in range for non-PLT usage
    [    0.332203] Modules: 518880 pages in range for PLT usage
    [    0.338398] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
    [    0.350788] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
    [    0.357203] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
    [    0.364151] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
    [    0.370563] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
    [    0.377510] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
    [    0.383923] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
    [    0.390871] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
    [    0.398132] k3-chipinfo 43000014.chipid: Family:J721S2 rev:SR1.0 JTAGID[0x0bb7502f] Detected
    [    0.407254] iommu: Default domain type: Translated
    [    0.412181] iommu: DMA domain TLB invalidation policy: strict mode
    [    0.418658] SCSI subsystem initialized
    [    0.422604] libata version 3.00 loaded.
    [    0.422689] usbcore: registered new interface driver usbfs
    [    0.428326] usbcore: registered new interface driver hub
    [    0.433783] usbcore: registered new device driver usb
    [    0.439184] pps_core: LinuxPPS API ver. 1 registered
    [    0.444265] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
    [    0.453623] PTP clock support registered
    [    0.457731] EDAC MC: Ver: 3.0.0
    [    0.461203] scmi_core: SCMI protocol bus registered
    [    0.466360] FPGA manager framework
    [    0.469880] Advanced Linux Sound Architecture Driver Initialized.
    [    0.476595] vgaarb: loaded
    [    0.479531] clocksource: Switched to clocksource arch_sys_counter
    [    0.485926] VFS: Disk quotas dquot_6.6.0
    [    0.489966] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
    [    0.500374] NET: Registered PF_INET protocol family
    [    0.505737] IP idents hash table entries: 262144 (order: 9, 2097152 bytes, linear)
    [    0.518619] tcp_listen_portaddr_hash hash table entries: 8192 (order: 5, 131072 bytes, linear)
    [    0.527557] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
    [    0.535503] TCP established hash table entries: 131072 (order: 8, 1048576 bytes, linear)
    [    0.544200] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
    [    0.552837] TCP: Hash tables configured (established 131072 bind 65536)
    [    0.559747] UDP hash table entries: 8192 (order: 6, 262144 bytes, linear)
    [    0.566885] UDP-Lite hash table entries: 8192 (order: 6, 262144 bytes, linear)
    [    0.574577] NET: Registered PF_UNIX/PF_LOCAL protocol family
    [    0.580756] RPC: Registered named UNIX socket transport module.
    [    0.586831] RPC: Registered udp transport module.
    [    0.591644] RPC: Registered tcp transport module.
    [    0.596457] RPC: Registered tcp-with-tls transport module.
    [    0.602068] RPC: Registered tcp NFSv4.1 backchannel transport module.
    [    0.608662] NET: Registered PF_XDP protocol family
    [    0.613575] PCI: CLS 0 bytes, default 64
    [    0.618280] Initialise system trusted keyrings
    [    0.622969] workingset: timestamp_bits=46 max_order=22 bucket_order=0
    [    0.629761] squashfs: version 4.0 (2009/01/31) Phillip Lougher
    [    0.635894] NFS: Registering the id_resolver key type
    [    0.641089] Key type id_resolver registered
    [    0.645369] Key type id_legacy registered
    [    0.649481] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
    [    0.656343] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
    [    0.677669] Key type asymmetric registered
    [    0.681862] Asymmetric key parser 'x509' registered
    [    0.686888] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 244)
    [    0.694550] io scheduler mq-deadline registered
    [    0.699197] io scheduler kyber registered
    [    0.703317] io scheduler bfq registered
    [    0.709040] pinctrl-single 4301c000.pinctrl: 13 pins, size 52
    [    0.715031] pinctrl-single 4301c038.pinctrl: 11 pins, size 44
    [    0.721011] pinctrl-single 4301c068.pinctrl: 72 pins, size 288
    [    0.727110] pinctrl-single 4301c190.pinctrl: 1 pins, size 4
    [    0.732933] pinctrl-single 11c000.pinctrl: 72 pins, size 288
    [    0.739026] pinctrl-single 104200.pinctrl: 20 pins, size 80
    [    0.744804] pinctrl-single 104280.pinctrl: 8 pins, size 32
    [    0.753904] Serial: 8250/16550 driver, 12 ports, IRQ sharing enabled
    [    0.765694] loop: module loaded
    [    0.769576] megasas: 07.725.01.00-rc1
    [    0.775156] tun: Universal TUN/TAP device driver, 1.6
    [    0.780968] VFIO - User Level meta-driver version: 0.3
    [    0.786808] usbcore: registered new interface driver usb-storage
    [    0.793300] i2c_dev: i2c /dev entries driver
    [    0.798289] sdhci: Secure Digital Host Controller Interface driver
    [    0.804622] sdhci: Copyright(c) Pierre Ossman
    [    0.809182] sdhci-pltfm: SDHCI platform and OF driver helper
    [    0.815275] ledtrig-cpu: registered to indicate activity on CPUs
    [    0.821586] SMCCC: SOC_ID: ARCH_SOC_ID not implemented, skipping ....
    [    0.828588] usbcore: registered new interface driver usbhid
    [    0.834299] usbhid: USB HID core driver
    [    0.839049] hw perfevents: enabled with armv8_cortex_a72 PMU driver, 7 counters available
    [    0.847681] optee: probing for conduit method.
    [    0.852244] optee: revision 4.2 (12d7c4ee)
    [    0.868741] optee: dynamic shared memory is enabled
    [    0.878391] random: crng init done
    [    0.881936] optee: initialized driver
    [    0.887006] Initializing XFRM netlink socket
    [    0.891412] NET: Registered PF_PACKET protocol family
    [    0.896628] Key type dns_resolver registered
    [    0.904569] registered taskstats version 1
    [    0.908836] Loading compiled-in X.509 certificates
    [    0.920242] ti-sci 44083000.system-controller: ABI: 4.0 (firmware rev 0x000a '10.0.8--v10.00.08 (Fiery Fox)')
    [    0.972501] omap_i2c 42120000.i2c: bus 0 rev0.12 at 400 kHz
    [    0.978874] omap_i2c 2000000.i2c: bus 1 rev0.12 at 400 kHz
    [    0.984654] ti-sci-intr 42200000.interrupt-controller: Interrupt Router 125 domain created
    [    0.993218] ti-sci-intr bus@100000:interrupt-controller@a00000: Interrupt Router 148 domain created
    [    1.002581] ti-sci-intr 310e0000.interrupt-controller: Interrupt Router 227 domain created
    [    1.011274] ti-sci-inta 33d00000.msi-controller: Interrupt Aggregator domain 265 created
    [    1.021752] ti-udma 311a0000.dma-controller: Number of rings: 48
    [    1.028730] ti-udma 311a0000.dma-controller: Channels: 24 (bchan: 0, tchan: 8, rchan: 16)
    [    1.038134] k3-ringacc 2b800000.ringacc: Ring Accelerator probed rings:286, gp-rings[96,20] sci-dev-id:272
    [    1.048038] k3-ringacc 2b800000.ringacc: dma-ring-reset-quirk: disabled
    [    1.054817] k3-ringacc 2b800000.ringacc: RA Proxy rev. 66349100, num_proxies:64
    [    1.064253] k3-ringacc 3c000000.ringacc: Ring Accelerator probed rings:1024, gp-rings[878,128] sci-dev-id:259
    [    1.074453] k3-ringacc 3c000000.ringacc: dma-ring-reset-quirk: disabled
    [    1.081225] k3-ringacc 3c000000.ringacc: RA Proxy rev. 66349100, num_proxies:64
    [    1.089434] 2810000.serial: ttyS1 at MMIO 0x2810000 (irq = 228, base_baud = 3000000) is a 8250
    [    1.098991] 2830000.serial: ttyS3 at MMIO 0x2830000 (irq = 229, base_baud = 3000000) is a 8250
    [    1.107904] printk: console [ttyS3] enabled
    [    1.116391] printk: bootconsole [ns16550a0] disabled
    [    1.127088] davinci_mdio 46000f00.mdio: Configuring MDIO in manual mode
    [    1.171536] davinci_mdio 46000f00.mdio: davinci mdio revision 9.7, bus freq 1000000
    [    1.181567] davinci_mdio 46000f00.mdio: phy[0]: device 46000f00.mdio:00, driver TI DP83867
    [    1.189846] am65-cpsw-nuss 46000000.ethernet: initializing am65 cpsw nuss version 0x6BA02102, cpsw version 0x6BA82102 Ports: 2 quirks:00000000
    [    1.202712] am65-cpsw-nuss 46000000.ethernet: initialized cpsw ale version 1.4
    [    1.209920] am65-cpsw-nuss 46000000.ethernet: ALE Table size 64
    [    1.216239] am65-cpsw-nuss 46000000.ethernet: CPTS ver 0x4e8a010b, freq:500000000, add_val:1 pps:0
    [    1.226723] am65-cpts 310d0000.cpts: CPTS ver 0x4e8a010c, freq:200000000, add_val:4 pps:0
    [    1.235380] omap-mailbox 31f80000.mailbox: omap mailbox rev 0x66fca100
    [    1.242235] omap-mailbox 31f81000.mailbox: omap mailbox rev 0x66fca100
    [    1.249153] omap-mailbox 31f82000.mailbox: omap mailbox rev 0x66fca100
    [    1.255966] omap-mailbox 31f84000.mailbox: omap mailbox rev 0x66fca100
    [    1.265954] ti-udma 285c0000.dma-controller: Channels: 26 (tchan: 13, rchan: 13, gp-rflow: 8)
    [    1.276345] ti-udma 31150000.dma-controller: Channels: 60 (tchan: 30, rchan: 30, gp-rflow: 16)
    [    1.286658] davinci_mdio 46000f00.mdio: Configuring MDIO in manual mode
    [    1.331537] davinci_mdio 46000f00.mdio: davinci mdio revision 9.7, bus freq 1000000
    [    1.341574] davinci_mdio 46000f00.mdio: phy[0]: device 46000f00.mdio:00, driver TI DP83867
    [    1.349855] am65-cpsw-nuss 46000000.ethernet: initializing am65 cpsw nuss version 0x6BA02102, cpsw version 0x6BA82102 Ports: 2 quirks:00000000
    [    1.362722] am65-cpsw-nuss 46000000.ethernet: initialized cpsw ale version 1.4
    [    1.369930] am65-cpsw-nuss 46000000.ethernet: ALE Table size 64
    [    1.376219] am65-cpsw-nuss 46000000.ethernet: CPTS ver 0x4e8a010b, freq:500000000, add_val:1 pps:0
    [    1.391195] am65-cpsw-nuss 46000000.ethernet: set new flow-id-base 48
    [    1.401087] mmc0: CQHCI version 5.10
    [    1.403192] clk: Disabling unused clocks
    [    1.415461] ALSA device list:
    [    1.418431]   No soundcards found.
    [    1.442157] mmc0: SDHCI controller on 4fb0000.mmc [4fb0000.mmc] using ADMA 64-bit
    [    1.449798] Waiting for root device PARTUUID=9dadd190-02...
    [    1.484847] mmc0: new high speed SDHC card at address aaaa
    [    1.490763] mmcblk0: mmc0:aaaa SC16G 14.8 GiB
    [    1.499906]  mmcblk0: p1 p2
    [    1.531589] EXT4-fs (mmcblk0p2): mounted filesystem d88879a7-aaa7-46a6-ab32-21f4d3c680cd r/w with ordered data mode. Quota mode: none.
    [    1.543700] VFS: Mounted root (ext4 filesystem) on device 179:2.
    [    1.559810] devtmpfs: mounted
    [    1.563863] Freeing unused kernel memory: 2752K
    [    1.568567] Run /sbin/init as init process
    [    1.572663]   with arguments:
    [    1.572667]     /sbin/init
    [    1.572670]   with environment:
    [    1.572672]     HOME=/
    [    1.572675]     TERM=linux
    [    2.130327] systemd[1]: System time before build time, advancing clock.
    [    2.230176] NET: Registered PF_INET6 protocol family
    [    2.235818] Segment Routing with IPv6
    [    2.239479] In-situ OAM (IOAM) with IPv6
    [    2.308769] systemd[1]: systemd 255.4^ running in system mode (+PAM -AUDIT -SELINUX -APPARMOR +IMA -SMACK +SECCOMP -GCRYPT -GNUTLS -OPENSSL +ACL +BLKID -CURL -ELFUTILS -FIDO2 -IDN2 -IDN -IPTC +KMOD -LIBCRYPTSETUP +LIBFDISK -PCRE2 -PWQUALITY -P11KIT -QRENCODE -TPM2 -BZIP2 -LZ4 -XZ -ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
    [    2.340554] systemd[1]: Detected architecture arm64.
    [    2.373155] systemd[1]: Hostname set to <am68-sk>.
    [    2.501045] systemd-sysv-generator[86]: SysV service '/etc/init.d/edgeai-launcher.sh' lacks a native systemd unit file. ~ Automatically generating a unit file for compatibility. Please update package to include a native systemd unit file, in order to make it safe, robust and future-proof. ! This compatibility logic is deprecated, expect removal soon. !
    [    2.682228] systemd[1]: /usr/lib/systemd/system/bt-enable.service:9: Standard output type syslog is obsolete, automatically updating to journal. Please update your unit file, and consider removing the setting altogether.
    [    2.754798] systemd[1]: /etc/systemd/system/sync-clocks.service:11: Standard output type syslog is obsolete, automatically updating to journal. Please update your unit file, and consider removing the setting altogether.
    [    2.817419] systemd[1]: Queued start job for default target Graphical Interface.
    [    2.854874] systemd[1]: Created slice Slice /system/getty.
    [    2.876939] systemd[1]: Created slice Slice /system/modprobe.
    [    2.900825] systemd[1]: Created slice Slice /system/serial-getty.
    [    2.924547] systemd[1]: Created slice User and Session Slice.
    [    2.947804] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
    [    2.971707] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
    [    2.995634] systemd[1]: Expecting device /dev/ttyS3...
    [    3.011657] systemd[1]: Reached target Path Units.
    [    3.027604] systemd[1]: Reached target Remote File Systems.
    [    3.047592] systemd[1]: Reached target Slice Units.
    [    3.063604] systemd[1]: Reached target Swaps.
    [    3.106820] systemd[1]: Listening on RPCbind Server Activation Socket.
    [    3.131733] systemd[1]: Reached target RPC Port Mapper.
    [    3.157175] systemd[1]: Listening on Process Core Dump Socket.
    [    3.179839] systemd[1]: Listening on initctl Compatibility Named Pipe.
    [    3.216272] systemd[1]: Listening on Journal Audit Socket.
    [    3.239953] systemd[1]: Listening on Journal Socket (/dev/log).
    [    3.263964] systemd[1]: Listening on Journal Socket.
    [    3.280056] systemd[1]: Listening on Network Service Netlink Socket.
    [    3.311308] systemd[1]: Listening on udev Control Socket.
    [    3.331910] systemd[1]: Listening on udev Kernel Socket.
    [    3.351902] systemd[1]: Listening on User Database Manager Socket.
    [    3.403788] systemd[1]: Mounting Huge Pages File System...
    [    3.422068] systemd[1]: Mounting POSIX Message Queue File System...
    [    3.447961] systemd[1]: Mounting Kernel Debug File System...
    [    3.467920] systemd[1]: Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
    [    3.491789] systemd[1]: Mounting Temporary Directory /tmp...
    [    3.513285] systemd[1]: Starting Create List of Static Device Nodes...
    [    3.600260] systemd[1]: Starting Load Kernel Module configfs...
    [    3.628255] systemd[1]: Starting Load Kernel Module drm...
    [    3.688197] systemd[1]: Starting Load Kernel Module fuse...
    [    3.714726] systemd[1]: Starting Start psplash boot splash screen...
    [    3.751715] fuse: init (API version 7.39)
    [    3.776302] systemd[1]: Starting RPC Bind...
    [    3.795864] systemd[1]: File System Check on Root Device was skipped because of an unmet condition check (ConditionPathIsReadWrite=!/).
    [    3.812885] systemd[1]: Starting Journal Service...
    [    3.867206] systemd[1]: Starting Load Kernel Modules...
    [    3.888725] systemd-journald[104]: Collecting audit messages is enabled.
    [    3.895762] systemd[1]: Starting Generate network units from Kernel command line...
    [    3.923780] systemd[1]: Starting Remount Root and Kernel File Systems...
    [    3.969950] systemd[1]: Starting Coldplug All udev Devices...
    [    4.035956] EXT4-fs (mmcblk0p2): re-mounted d88879a7-aaa7-46a6-ab32-21f4d3c680cd r/w. Quota mode: none.
    [    4.050792] systemd[1]: Started RPC Bind.
    [    4.068135] systemd[1]: Started Journal Service.
    [    4.527734] systemd-journald[104]: Received client request to flush runtime journal.
    [    4.773262] audit: type=1334 audit(1709054766.640:2): prog-id=6 op=LOAD
    [    4.780344] audit: type=1334 audit(1709054766.648:3): prog-id=7 op=LOAD
    [    5.003404] audit: type=1334 audit(1709054766.868:4): prog-id=8 op=LOAD
    [    5.050261] audit: type=1334 audit(1709054766.916:5): prog-id=9 op=LOAD
    [    5.254201] audit: type=1334 audit(1709054767.120:6): prog-id=10 op=LOAD
    [    5.266701] audit: type=1334 audit(1709054767.128:7): prog-id=11 op=LOAD
    [    5.279613] audit: type=1334 audit(1709054767.128:8): prog-id=12 op=LOAD
    [    5.880404] omap_rng 4e10000.rng: Random Number Generator ver. 241b34c
    [    6.030621] audit: type=1334 audit(1737637390.874:9): prog-id=13 op=LOAD
    [    6.123282] mc: Linux media interface: v0.10
    [    6.131161] platform 41000000.r5f: R5F core may have been powered on by a different host, programmed state (0) != actual state (1)
    [    6.170105] cdns-dsi 4800000.dsi: Fixed dependency cycle(s) with /bus@100000/dsi@4800000/panel@0
    [    6.179071] mipi-dsi 4800000.dsi.0: Fixed dependency cycle(s) with /bus@100000/dsi@4800000
    [    6.181119] platform 41000000.r5f: configured R5F for IPC-only mode
    [    6.215317] platform 41000000.r5f: assigned reserved memory node r5f-dma-memory@a0000000
    [    6.225921] remoteproc remoteproc0: 41000000.r5f is available
    [    6.231869] remoteproc remoteproc0: attaching to 41000000.r5f
    [    6.239164] platform 41000000.r5f: R5F core initialized in IPC-only mode
    [    6.246571] rproc-virtio rproc-virtio.0.auto: assigned reserved memory node r5f-dma-memory@a0000000
    [    6.256447] virtio_rpmsg_bus virtio0: rpmsg host is online
    [    6.262059] rproc-virtio rproc-virtio.0.auto: registered virtio0 (type 7)
    [    6.268980] virtio_rpmsg_bus virtio0: creating channel ti.ipc4.ping-pong addr 0xd
    [    6.276687] virtio_rpmsg_bus virtio0: creating channel rpmsg_chrdev addr 0xe
    [    6.284004] remoteproc remoteproc0: remote processor 41000000.r5f is now attached
    [    6.330934] videodev: Linux video capture interface: v2.00
    [    6.477546] [drm] Initialized tidss 1.0.0 20180215 for 4a00000.dss on minor 0
    [    6.502249] pvrsrvkm: loading out-of-tree module taints kernel.
    [    6.533512] PVR_K:  184: Device: 4e20000000.gpu
    [    6.537447] PVR_K:  184: Read BVNC 36.53.104.796 from HW device registers
    [    6.537495] PVR_K:  184: RGX Device registered BVNC 36.53.104.796 with 1 core in the system
    [    6.540392] [drm] Initialized pvr 24.1.6554834 20170530 for 4e20000000.gpu on minor 1
    [    6.636921] vdec 4210000.video-codec: Added wave5 driver with caps: 'ENCODE' 'DECODE'
    [    6.636933] vdec 4210000.video-codec: Product Code:      0x521c
    [    6.636936] vdec 4210000.video-codec: Firmware Revision: 320127
    [    6.719229] dbus-broker-lau[270]: memfd_create() called without MFD_EXEC or MFD_NOEXEC_SEAL set
    [    7.107563] mipi write return: 0
    [    7.315606] Console: switching to colour frame buffer device 128x37
    [    7.401104] tidss 4a00000.dss: [drm] fb0: tidssdrmfb frame buffer device
    [    7.689498] audit: type=1334 audit(1737637392.534:10): prog-id=14 op=LOAD
    [    7.707692] audit: type=1334 audit(1737637392.542:11): prog-id=15 op=LOAD
    [    7.715922] audit: type=1334 audit(1737637392.542:12): prog-id=16 op=LOAD
    [    7.841619] audit: type=1334 audit(1737637392.686:13): prog-id=17 op=LOAD
    [    8.230023] cfg80211: Loading compiled-in X.509 certificates for regulatory database
    [    8.249792] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
    [    8.261130] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
    [    8.589735] Bluetooth: Core ver 2.22
    [    8.593855] NET: Registered PF_BLUETOOTH protocol family
    [    8.599384] Bluetooth: HCI device and connection manager initialized
    [    8.605945] Bluetooth: HCI socket layer initialized
    [    8.611004] Bluetooth: L2CAP socket layer initialized
    [    8.616166] Bluetooth: SCO socket layer initialized
    [    8.744720] am65-cpsw-nuss 46000000.ethernet eth0: PHY [46000f00.mdio:00] driver [TI DP83867] (irq=POLL)
    [    8.799490] am65-cpsw-nuss 46000000.ethernet eth0: configuring for phy/rgmii-rxid link mode
    [    9.984042] audit: type=1006 audit(1737637394.830:14): pid=458 uid=0 old-auid=4294967295 auid=1000 tty=(none) old-ses=4294967295 ses=1 res=1
    [    9.997433] audit: type=1300 audit(1737637394.830:14): arch=c00000b7 syscall=64 success=yes exit=4 a0=8 a1=ffffd3ed94a8 a2=4 a3=1 items=0 ppid=1 pid=458 auid=1000 uid=0 gid=0 euid=0 suid=0 fsuid=0 egid=0 sgid=0 fsgid=0 tty=(none) ses=1 comm="(systemd)" exe="/usr/lib/systemd/systemd-executor" key=(null)
    [   10.024257] audit: type=1327 audit(1737637394.830:14): proctitle="(systemd)"
    [   10.551994] audit: type=1006 audit(1737637395.394:15): pid=450 uid=0 old-auid=4294967295 auid=1000 tty=tty7 old-ses=4294967295 ses=2 res=1
    [   10.566285] audit: type=1300 audit(1737637395.394:15): arch=c00000b7 syscall=64 success=yes exit=4 a0=8 a1=ffffcf1cdef8 a2=4 a3=1 items=0 ppid=1 pid=450 auid=1000 uid=0 gid=0 euid=0 suid=0 fsuid=0 egid=0 sgid=0 fsgid=0 tty=tty7 ses=2 comm="(weston)" exe="/usr/lib/systemd/systemd-executor" key=(null)
    [   11.803452] PVR_K:  450: RGX Firmware image 'rgx.fw.36.53.104.796' loaded
    [   11.838591] PVR_K:  450: Shader binary image 'rgx.sh.36.53.104.796' loaded
    [   12.898266] am65-cpsw-nuss 46000000.ethernet eth0: Link is Up - 1Gbps/Full - flow control rx/tx
    [   15.195265] kauditd_printk_skb: 1 callbacks suppressed
    [   15.195274] audit: type=1701 audit(1737637400.038:16): auid=4294967295 uid=0 gid=0 ses=4294967295 pid=602 comm="edgeai-gui-app" exe="/usr/bin/edgeai-gui-app" sig=11 res=1
    [   15.241333] audit: type=1334 audit(1737637400.086:17): prog-id=18 op=LOAD
    [   15.248437] audit: type=1334 audit(1737637400.094:18): prog-id=19 op=LOAD
    [   15.255626] audit: type=1334 audit(1737637400.102:19): prog-id=20 op=LOAD
    [   15.640476] audit: type=1334 audit(1737637400.486:20): prog-id=20 op=UNLOAD
    [   15.647696] audit: type=1334 audit(1737637400.494:21): prog-id=19 op=UNLOAD
    [   15.654835] audit: type=1334 audit(1737637400.494:22): prog-id=18 op=UNLOAD
    [   25.969929] audit: type=1006 audit(1737637410.814:23): pid=1115 uid=0 old-auid=4294967295 auid=0 tty=(none) old-ses=4294967295 ses=3 res=1
    [   25.982546] audit: type=1300 audit(1737637410.814:23): arch=c00000b7 syscall=64 success=yes exit=1 a0=8 a1=ffffc3f26cf8 a2=1 a3=1 items=0 ppid=1 pid=1115 auid=0 uid=0 gid=0 euid=0 suid=0 fsuid=0 egid=0 sgid=0 fsgid=0 tty=(none) ses=3 comm="(systemd)" exe="/usr/lib/systemd/systemd-executor" key=(null)
    [   26.009502] audit: type=1327 audit(1737637410.814:23): proctitle="(systemd)"
    [   26.016768] audit: type=1334 audit(1737637410.858:24): prog-id=21 op=LOAD
    [   26.023672] audit: type=1300 audit(1737637410.858:24): arch=c00000b7 syscall=280 success=yes exit=8 a0=5 a1=ffffedacb808 a2=90 a3=0 items=0 ppid=1 pid=1115 auid=0 uid=0 gid=0 euid=0 suid=0 fsuid=0 egid=0 sgid=0 fsgid=0 tty=(none) ses=3 comm="systemd" exe="/usr/lib/systemd/systemd" key=(null)
    [   26.049484] audit: type=1327 audit(1737637410.858:24): proctitle="(systemd)"
    [   26.056667] audit: type=1334 audit(1737637410.862:25): prog-id=21 op=UNLOAD
    [   26.063684] audit: type=1300 audit(1737637410.862:25): arch=c00000b7 syscall=57 success=yes exit=0 a0=8 a1=1 a2=0 a3=ffffba86cc60 items=0 ppid=1 pid=1115 auid=0 uid=0 gid=0 euid=0 suid=0 fsuid=0 egid=0 sgid=0 fsgid=0 tty=(none) ses=3 comm="systemd" exe="/usr/lib/systemd/systemd" key=(null)
    [   26.089335] audit: type=1327 audit(1737637410.862:25): proctitle="(systemd)"
    [   26.096438] audit: type=1334 audit(1737637410.862:26): prog-id=22 op=LOAD

    Here are the value of the registers at these addresses:

    • 0F08 0108h = 0
    • 0480 00F0h = 4
    • 0480 0140h = 0
    • 0480 0180h = 5

    I read these values using my Blackhawk emulator in Code Composer. When I try to read these addresses in Linux using /dev/mem or devmem2, the kernel crashes completely.

    If you have a scope set to trigger on detecting an edge or a voltage level, there should be one line of the frame that gets transmitted before the clock and data lines go silent if it is a HSYNC issue.

    This is great info, thank you! I didn't realize the clock would go silent. I readjusted my scope settings to catch and hold something on the clock and data lane 0 positive signals when the board boots. On the clock signal I see a single pulse (not even a full clock cycle) before going completely silent. On data lane 0, I can see what looks like transmission of a couple "packets" (if that's what they're called - I'm not familiar with the DSI protocol). Afterwards it that line floats high. All of the other data lines just float high after the system boots. Refer to the pictures I took of my scope below:

    This is the clock positive line pulse before going low:

    This is data lane 0 positive. I tried to fit as much as possible on my scope without losing resolution, but from observation it seemed like there were about 2 or 3 sequences of data being sent:

    I know you didn't ask for it but here are the loaded modules:

    Module                  Size  Used by
    overlay               151552  0
    bluetooth             765952  2
    ecdh_generic           16384  1 bluetooth
    ecc                    36864  1 ecdh_generic
    cfg80211              421888  0
    rfkill                 28672  3 bluetooth,cfg80211
    wave5                 126976  0
    videobuf2_dma_contig    24576  1 wave5
    videobuf2_memops       16384  1 videobuf2_dma_contig
    v4l2_mem2mem           40960  1 wave5
    rpmsg_ctrl             12288  0
    videobuf2_v4l2         32768  2 v4l2_mem2mem,wave5
    rpmsg_char             20480  1 rpmsg_ctrl
    pvrsrvkm             1269760  0
    cdns3                  45056  0
    crct10dif_ce           12288  1
    videobuf2_common       57344  5 videobuf2_dma_contig,videobuf2_v4l2,v4l2_mem2mem,wave5,videobuf2_memops
    panel_feiyang_fy07024di26a30d    12288  0
    tidss                  86016  0
    spidev                 24576  0
    cdns_usb_common        24576  1 cdns3
    videodev              270336  3 videobuf2_v4l2,v4l2_mem2mem,wave5
    cdns_dsi               16384  0
    mc                     77824  4 videodev,videobuf2_v4l2,videobuf2_common,v4l2_mem2mem
    ti_k3_r5_remoteproc    36864  0
    drm_dma_helper         20480  3 tidss
    pwm_bl                 16384  0
    k3_j72xx_bandgap       16384  0
    drm_kms_helper        208896  3 drm_dma_helper,cdns_dsi,tidss
    cdns_dphy              12288  0
    cdns3_ti               12288  0
    sa2ul                  36864  0
    pwm_tiehrpwm           12288  1
    rti_wdt                12288  0
    spi_omap2_mcspi        24576  0
    fuse                  135168  1
    drm                   602112  7 drm_kms_helper,drm_dma_helper,panel_feiyang_fy07024di26a30d,pvrsrvkm,cdns_dsi,tidss
    drm_panel_orientation_quirks    24576  1 drm
    backlight              28672  2 pwm_bl,drm
    ipv6                  495616  34
    

    Thanks for looking into this. Let me know what other suggestions you have.

    Thanks again and have a great weekend!

  • Hi Amandio,

    The scope signals and register dumps both seem to indicate a HSYNC. 0480 0180h bit 2 is ERR_MISSING_HSYNC_FLAG. 

    This could happen if the timing parameters are slightly wrong for the display panel. 

    • What model of display panel is in use? Is it FY07024DI26A30-D, or a similar but different panel? If it is a similar panel, what is the model? Nevermind, I see in your first post
    • What is the resolution and frequency supported by the monitor?

    Could you:

    • Run "k3conf dump clock" to check clocks

    Regards,

    Takuma

  • Hi Takuma,

    The panel supports a resolution of 1024x600 at 60Hz. At the mode we are trying to run, the DCLK is supposed to be 51.2MHz. Here is the output of k3conf dump clock:

    |------------------------------------------------------------------------------|
    | VERSION INFO                                                                 |
    |------------------------------------------------------------------------------|
    | K3CONF | (version 0.3-nogit built Thu Jul 25 14:13:02 UTC 2024)              |
    | SoC    | J721S2 SR1.0                                                        |
    | SYSFW  | ABI: 4.0 (firmware version 0x000a '10.0.8--v10.00.08 (Fiery Fox))') |
    |------------------------------------------------------------------------------|
    
    |--------------------------------------------------------------------------------------------------------------------------------------------------|
    | Device ID | Clock ID | Clock Name                                                                        | Status              | Clock Frequency |
    |--------------------------------------------------------------------------------------------------------------------------------------------------|
    |     4     |     0    | DEV_A72SS0_ARM_CLK_CLK                                                            | CLK_STATE_READY     | 2000000000      |
    |     4     |     1    | DEV_A72SS0_MSMC_CLK                                                               | CLK_STATE_READY     | 1000000000      |
    |     4     |     2    | DEV_A72SS0_PLL_CTRL_CLK                                                           | CLK_STATE_READY     | 500000000       |
    |     4     |     6    | DEV_A72SS0_A72_DIVH_CLK8_OBSCLK_OUT_CLK                                           | CLK_STATE_READY     | 0               |
    |   202     |     0    | DEV_A72SS0_CORE0_ARM_CLK_CLK                                                      | CLK_STATE_READY     | 2000000000      |
    |   203     |     0    | DEV_A72SS0_CORE1_ARM_CLK_CLK                                                      | CLK_STATE_READY     | 2000000000      |
    |   134     |     0    | DEV_AGGR_ATB0_DBG_CLK                                                             | CLK_STATE_READY     | 250000000       |
    |     2     |     0    | DEV_ATL0_ATL_IO_PORT_ATCLK_OUT                                                    | CLK_STATE_READY     | 0               |
    |     2     |     1    | DEV_ATL0_ATL_IO_PORT_ATCLK_OUT_1                                                  | CLK_STATE_READY     | 0               |
    |     2     |     2    | DEV_ATL0_ATL_IO_PORT_ATCLK_OUT_2                                                  | CLK_STATE_READY     | 0               |
    |     2     |     3    | DEV_ATL0_ATL_IO_PORT_ATCLK_OUT_3                                                  | CLK_STATE_READY     | 0               |
    |     2     |     4    | DEV_ATL0_ATL_CLK                                                                  | CLK_STATE_READY     | 294912000       |
    |     2     |     5    | DEV_ATL0_ATL_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT1_CLK                         | CLK_STATE_READY     | 294912000       |
    |     2     |     6    | DEV_ATL0_ATL_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK                         | CLK_STATE_READY     | 200000000       |
    |     2     |     9    | DEV_ATL0_ATL_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT7_CLK                       | CLK_STATE_READY     | 200000000       |
    |     2     |    10    | DEV_ATL0_ATL_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                               | CLK_STATE_READY     | 0               |
    |     2     |    11    | DEV_ATL0_ATL_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT                                   | CLK_STATE_READY     | 0               |
    |     2     |    13    | DEV_ATL0_VBUS_CLK                                                                 | CLK_STATE_READY     | 250000000       |
    |     2     |    14    | DEV_ATL0_ATL_IO_PORT_AWS                                                          | CLK_STATE_READY     | 0               |
    |     2     |    15    | DEV_ATL0_ATL_IO_PORT_AWS_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT                      | CLK_STATE_READY     | 0               |
    |     2     |    16    | DEV_ATL0_ATL_IO_PORT_AWS_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT                      | CLK_STATE_READY     | 0               |
    |     2     |    17    | DEV_ATL0_ATL_IO_PORT_AWS_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT_DUP0                 | CLK_STATE_READY     | 0               |
    |     2     |    18    | DEV_ATL0_ATL_IO_PORT_AWS_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT_DUP0                 | CLK_STATE_READY     | 0               |
    |     2     |    19    | DEV_ATL0_ATL_IO_PORT_AWS_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT_DUP0                 | CLK_STATE_READY     | 0               |
    |     2     |    27    | DEV_ATL0_ATL_IO_PORT_AWS_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT_DUP0                 | CLK_STATE_READY     | 0               |
    |     2     |    28    | DEV_ATL0_ATL_IO_PORT_AWS_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT_DUP0                 | CLK_STATE_READY     | 0               |
    |     2     |    29    | DEV_ATL0_ATL_IO_PORT_AWS_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT                      | CLK_STATE_READY     | 0               |
    |     2     |    30    | DEV_ATL0_ATL_IO_PORT_AWS_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT                      | CLK_STATE_READY     | 0               |
    |     2     |    31    | DEV_ATL0_ATL_IO_PORT_AWS_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT                      | CLK_STATE_READY     | 0               |
    |     2     |    39    | DEV_ATL0_ATL_IO_PORT_AWS_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT                     | CLK_STATE_READY     | 0               |
    |     2     |    40    | DEV_ATL0_ATL_IO_PORT_AWS_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT                     | CLK_STATE_READY     | 0               |
    |     2     |    47    | DEV_ATL0_ATL_IO_PORT_AWS_1                                                        | CLK_STATE_READY     | 0               |
    |     2     |    48    | DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT                    | CLK_STATE_READY     | 0               |
    |     2     |    49    | DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT                    | CLK_STATE_READY     | 0               |
    |     2     |    50    | DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT_DUP0               | CLK_STATE_READY     | 0               |
    |     2     |    51    | DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT_DUP0               | CLK_STATE_READY     | 0               |
    |     2     |    52    | DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT_DUP0               | CLK_STATE_READY     | 0               |
    |     2     |    60    | DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT_DUP0               | CLK_STATE_READY     | 0               |
    |     2     |    61    | DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT_DUP0               | CLK_STATE_READY     | 0               |
    |     2     |    62    | DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT                    | CLK_STATE_READY     | 0               |
    |     2     |    63    | DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT                    | CLK_STATE_READY     | 0               |
    |     2     |    64    | DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT                    | CLK_STATE_READY     | 0               |
    |     2     |    72    | DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT                   | CLK_STATE_READY     | 0               |
    |     2     |    73    | DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT                   | CLK_STATE_READY     | 0               |
    |     2     |    80    | DEV_ATL0_ATL_IO_PORT_AWS_2                                                        | CLK_STATE_READY     | 0               |
    |     2     |    81    | DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT                    | CLK_STATE_READY     | 0               |
    |     2     |    82    | DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT                    | CLK_STATE_READY     | 0               |
    |     2     |    83    | DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT_DUP0               | CLK_STATE_READY     | 0               |
    |     2     |    84    | DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT_DUP0               | CLK_STATE_READY     | 0               |
    |     2     |    85    | DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT_DUP0               | CLK_STATE_READY     | 0               |
    |     2     |    93    | DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT_DUP0               | CLK_STATE_READY     | 0               |
    |     2     |    94    | DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT_DUP0               | CLK_STATE_READY     | 0               |
    |     2     |    95    | DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT                    | CLK_STATE_READY     | 0               |
    |     2     |    96    | DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT                    | CLK_STATE_READY     | 0               |
    |     2     |    97    | DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT                    | CLK_STATE_READY     | 0               |
    |     2     |   105    | DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT                   | CLK_STATE_READY     | 0               |
    |     2     |   106    | DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT                   | CLK_STATE_READY     | 0               |
    |     2     |   113    | DEV_ATL0_ATL_IO_PORT_AWS_3                                                        | CLK_STATE_READY     | 0               |
    |     2     |   114    | DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT                    | CLK_STATE_READY     | 0               |
    |     2     |   115    | DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT                    | CLK_STATE_READY     | 0               |
    |     2     |   116    | DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT_DUP0               | CLK_STATE_READY     | 0               |
    |     2     |   117    | DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT_DUP0               | CLK_STATE_READY     | 0               |
    |     2     |   118    | DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT_DUP0               | CLK_STATE_READY     | 0               |
    |     2     |   126    | DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT_DUP0               | CLK_STATE_READY     | 0               |
    |     2     |   127    | DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT_DUP0               | CLK_STATE_READY     | 0               |
    |     2     |   128    | DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT                    | CLK_STATE_READY     | 0               |
    |     2     |   129    | DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT                    | CLK_STATE_READY     | 0               |
    |     2     |   130    | DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT                    | CLK_STATE_READY     | 0               |
    |     2     |   138    | DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT                   | CLK_STATE_READY     | 0               |
    |     2     |   139    | DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT                   | CLK_STATE_READY     | 0               |
    |     2     |   146    | DEV_ATL0_ATL_IO_PORT_BWS                                                          | CLK_STATE_READY     | 0               |
    |     2     |   147    | DEV_ATL0_ATL_IO_PORT_BWS_PARENT_MCASP_MAIN_0_MCASP_AFSR_POUT                      | CLK_STATE_READY     | 0               |
    |     2     |   148    | DEV_ATL0_ATL_IO_PORT_BWS_PARENT_MCASP_MAIN_1_MCASP_AFSR_POUT                      | CLK_STATE_READY     | 0               |
    |     2     |   149    | DEV_ATL0_ATL_IO_PORT_BWS_PARENT_MCASP_MAIN_2_MCASP_AFSR_POUT                      | CLK_STATE_READY     | 0               |
    |     2     |   150    | DEV_ATL0_ATL_IO_PORT_BWS_PARENT_MCASP_MAIN_3_MCASP_AFSR_POUT                      | CLK_STATE_READY     | 0               |
    |     2     |   151    | DEV_ATL0_ATL_IO_PORT_BWS_PARENT_MCASP_MAIN_4_MCASP_AFSR_POUT                      | CLK_STATE_READY     | 0               |
    |     2     |   159    | DEV_ATL0_ATL_IO_PORT_BWS_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT                      | CLK_STATE_READY     | 0               |
    |     2     |   160    | DEV_ATL0_ATL_IO_PORT_BWS_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT                      | CLK_STATE_READY     | 0               |
    |     2     |   161    | DEV_ATL0_ATL_IO_PORT_BWS_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT                      | CLK_STATE_READY     | 0               |
    |     2     |   162    | DEV_ATL0_ATL_IO_PORT_BWS_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT                      | CLK_STATE_READY     | 0               |
    |     2     |   163    | DEV_ATL0_ATL_IO_PORT_BWS_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT                      | CLK_STATE_READY     | 0               |
    |     2     |   171    | DEV_ATL0_ATL_IO_PORT_BWS_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT                     | CLK_STATE_READY     | 0               |
    |     2     |   172    | DEV_ATL0_ATL_IO_PORT_BWS_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT                     | CLK_STATE_READY     | 0               |
    |     2     |   179    | DEV_ATL0_ATL_IO_PORT_BWS_1                                                        | CLK_STATE_READY     | 0               |
    |     2     |   180    | DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_MCASP_MAIN_0_MCASP_AFSR_POUT                    | CLK_STATE_READY     | 0               |
    |     2     |   181    | DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_MCASP_MAIN_1_MCASP_AFSR_POUT                    | CLK_STATE_READY     | 0               |
    |     2     |   182    | DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_MCASP_MAIN_2_MCASP_AFSR_POUT                    | CLK_STATE_READY     | 0               |
    |     2     |   183    | DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_MCASP_MAIN_3_MCASP_AFSR_POUT                    | CLK_STATE_READY     | 0               |
    |     2     |   184    | DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_MCASP_MAIN_4_MCASP_AFSR_POUT                    | CLK_STATE_READY     | 0               |
    |     2     |   192    | DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT                    | CLK_STATE_READY     | 0               |
    |     2     |   193    | DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT                    | CLK_STATE_READY     | 0               |
    |     2     |   194    | DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT                    | CLK_STATE_READY     | 0               |
    |     2     |   195    | DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT                    | CLK_STATE_READY     | 0               |
    |     2     |   196    | DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT                    | CLK_STATE_READY     | 0               |
    |     2     |   204    | DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT                   | CLK_STATE_READY     | 0               |
    |     2     |   205    | DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT                   | CLK_STATE_READY     | 0               |
    |     2     |   212    | DEV_ATL0_ATL_IO_PORT_BWS_2                                                        | CLK_STATE_READY     | 0               |
    |     2     |   213    | DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_MCASP_MAIN_0_MCASP_AFSR_POUT                    | CLK_STATE_READY     | 0               |
    |     2     |   214    | DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_MCASP_MAIN_1_MCASP_AFSR_POUT                    | CLK_STATE_READY     | 0               |
    |     2     |   215    | DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_MCASP_MAIN_2_MCASP_AFSR_POUT                    | CLK_STATE_READY     | 0               |
    |     2     |   216    | DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_MCASP_MAIN_3_MCASP_AFSR_POUT                    | CLK_STATE_READY     | 0               |
    |     2     |   217    | DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_MCASP_MAIN_4_MCASP_AFSR_POUT                    | CLK_STATE_READY     | 0               |
    |     2     |   225    | DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT                    | CLK_STATE_READY     | 0               |
    |     2     |   226    | DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT                    | CLK_STATE_READY     | 0               |
    |     2     |   227    | DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT                    | CLK_STATE_READY     | 0               |
    |     2     |   228    | DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT                    | CLK_STATE_READY     | 0               |
    |     2     |   229    | DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT                    | CLK_STATE_READY     | 0               |
    |     2     |   237    | DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT                   | CLK_STATE_READY     | 0               |
    |     2     |   238    | DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT                   | CLK_STATE_READY     | 0               |
    |     2     |   245    | DEV_ATL0_ATL_IO_PORT_BWS_3                                                        | CLK_STATE_READY     | 0               |
    |     2     |   246    | DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_MCASP_MAIN_0_MCASP_AFSR_POUT                    | CLK_STATE_READY     | 0               |
    |     2     |   247    | DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_MCASP_MAIN_1_MCASP_AFSR_POUT                    | CLK_STATE_READY     | 0               |
    |     2     |   248    | DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_MCASP_MAIN_2_MCASP_AFSR_POUT                    | CLK_STATE_READY     | 0               |
    |     2     |   249    | DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_MCASP_MAIN_3_MCASP_AFSR_POUT                    | CLK_STATE_READY     | 0               |
    |     2     |   250    | DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_MCASP_MAIN_4_MCASP_AFSR_POUT                    | CLK_STATE_READY     | 0               |
    |     2     |   258    | DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT                    | CLK_STATE_READY     | 0               |
    |     2     |   259    | DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT                    | CLK_STATE_READY     | 0               |
    |     2     |   260    | DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT                    | CLK_STATE_READY     | 0               |
    |     2     |   261    | DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT                    | CLK_STATE_READY     | 0               |
    |     2     |   262    | DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT                    | CLK_STATE_READY     | 0               |
    |     2     |   270    | DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT                   | CLK_STATE_READY     | 0               |
    |     2     |   271    | DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT                   | CLK_STATE_READY     | 0               |
    |   157     |     1    | DEV_BOARD0_DSI0_TXCLKN_IN                                                         | CLK_STATE_READY     | 0               |
    |   157     |     2    | DEV_BOARD0_I2C4_SCL_OUT                                                           | CLK_STATE_READY     | 0               |
    |   157     |     4    | DEV_BOARD0_CSI0_TXCLKN_IN                                                         | CLK_STATE_READY     | 0               |
    |   157     |     5    | DEV_BOARD0_CSI0_RXCLKP_OUT                                                        | CLK_STATE_READY     | 0               |
    |   157     |     6    | DEV_BOARD0_HYP0_TXPMCLK_IN                                                        | CLK_STATE_NOT_READY | 0               |
    |   157     |     7    | DEV_BOARD0_MCAN1_RX_OUT                                                           | CLK_STATE_READY     | 0               |
    |   157     |     8    | DEV_BOARD0_MCAN17_RX_OUT                                                          | CLK_STATE_READY     | 0               |
    |   157     |     9    | DEV_BOARD0_MMC1_CLK_IN                                                            | CLK_STATE_READY     | 0               |
    |   157     |    10    | DEV_BOARD0_MCU_OBSCLK0_IN                                                         | CLK_STATE_READY     | 1000000000      |
    |   157     |    11    | DEV_BOARD0_MCU_OBSCLK0_IN_PARENT_MCU_OBSCLK_DIV_OUT0                              | CLK_STATE_READY     | 1000000000      |
    |   157     |    12    | DEV_BOARD0_MCU_OBSCLK0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT                          | CLK_STATE_READY     | 19200000        |
    |   157     |    43    | DEV_BOARD0_I2C0_SCL_IN                                                            | CLK_STATE_NOT_READY | 0               |
    |   157     |    44    | DEV_BOARD0_SPI7_CLK_OUT                                                           | CLK_STATE_READY     | 0               |
    |   157     |    45    | DEV_BOARD0_MCU_CPTS0_RFT_CLK_OUT                                                  | CLK_STATE_READY     | 0               |
    |   157     |    46    | DEV_BOARD0_MCASP3_ACLKR_IN                                                        | CLK_STATE_READY     | 0               |
    |   157     |    47    | DEV_BOARD0_AUDIO_EXT_REFCLK1_OUT                                                  | CLK_STATE_READY     | 0               |
    |   157     |    48    | DEV_BOARD0_MCU_OSPI0_DQS_OUT                                                      | CLK_STATE_READY     | 0               |
    |   157     |    49    | DEV_BOARD0_HYP0_TXFLCLK_OUT                                                       | CLK_STATE_READY     | 0               |
    |   157     |    50    | DEV_BOARD0_MCU_OSPI0_LBCLKO_OUT                                                   | CLK_STATE_READY     | 0               |
    |   157     |    51    | DEV_BOARD0_MCASP3_ACLKX_IN                                                        | CLK_STATE_READY     | 0               |
    |   157     |    52    | DEV_BOARD0_HYP0_RXPMCLK_OUT                                                       | CLK_STATE_READY     | 0               |
    |   157     |    54    | DEV_BOARD0_MCASP1_ACLKX_IN                                                        | CLK_STATE_READY     | 0               |
    |   157     |    55    | DEV_BOARD0_MCU_SPI1_CLK_IN                                                        | CLK_STATE_READY     | 0               |
    |   157     |    56    | DEV_BOARD0_MCAN9_RX_OUT                                                           | CLK_STATE_READY     | 0               |
    |   157     |    57    | DEV_BOARD0_I2C6_SCL_OUT                                                           | CLK_STATE_READY     | 0               |
    |   157     |    58    | DEV_BOARD0_MCU_SPI0_CLK_OUT                                                       | CLK_STATE_READY     | 0               |
    |   157     |    59    | DEV_BOARD0_OBSCLK1_IN                                                             | CLK_STATE_READY     | 500000000       |
    |   157     |    60    | DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK                    | CLK_STATE_READY     | 500000000       |
    |   157     |    61    | DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT0_CLK                    | CLK_STATE_READY     | 192000000       |
    |   157     |    62    | DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK                    | CLK_STATE_READY     | 600000000       |
    |   157     |    63    | DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT0_CLK                    | CLK_STATE_READY     | 250000000       |
    |   157     |    64    | DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT0_CLK                    | CLK_STATE_READY     | 196608000       |
    |   157     |    65    | DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV1_16FFT_MAIN_5_HSDIVOUT0_CLK                    | CLK_STATE_READY     | 400000000       |
    |   157     |    66    | DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV0_16FFT_MAIN_6_HSDIVOUT0_CLK                    | CLK_STATE_READY     | 800000000       |
    |   157     |    67    | DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV0_16FFT_MAIN_26_HSDIVOUT0_CLK                   | CLK_STATE_READY     | 1066500000      |
    |   157     |    72    | DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV0_16FFT_MAIN_12_HSDIVOUT0_CLK                   | CLK_STATE_READY     | 1066500000      |
    |   157     |    73    | DEV_BOARD0_OBSCLK1_IN_PARENT_OBSCLK1_MUX_OUT0                                     | CLK_STATE_NOT_READY | 0               |
    |   157     |    74    | DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV2_16FFT_MAIN_14_HSDIVOUT0_CLK                   | CLK_STATE_READY     | 1000000000      |
    |   157     |    76    | DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK                   | CLK_STATE_READY     | 594000000       |
    |   157     |    77    | DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT0_CLK                   | CLK_STATE_READY     | 51200000        |
    |   157     |    79    | DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV1_16FFT_MAIN_19_HSDIVOUT0_CLK                   | CLK_STATE_READY     | 600000000       |
    |   157     |    85    | DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV1_16FFT_MAIN_25_HSDIVOUT0_CLK                   | CLK_STATE_READY     | 480000000       |
    |   157     |    86    | DEV_BOARD0_OBSCLK1_IN_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF3                      | CLK_STATE_READY     | 0               |
    |   157     |    87    | DEV_BOARD0_OBSCLK1_IN_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK         | CLK_STATE_READY     | 12500000        |
    |   157     |    88    | DEV_BOARD0_OBSCLK1_IN_PARENT_GLUELOGIC_LPXOSC_CLKOUT                              | CLK_STATE_READY     | 32768           |
    |   157     |    89    | DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK_DUP0               | CLK_STATE_READY     | 500000000       |
    |   157     |    90    | DEV_BOARD0_OBSCLK1_IN_PARENT_BOARD_0_HFOSC1_CLK_OUT                               | CLK_STATE_READY     | 0               |
    |   157     |    91    | DEV_BOARD0_OBSCLK1_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT                              | CLK_STATE_READY     | 19200000        |
    |   157     |    92    | DEV_BOARD0_MCU_OSPI1_LBCLKO_OUT                                                   | CLK_STATE_READY     | 0               |
    |   157     |    93    | DEV_BOARD0_MCASP3_ACLKX_OUT                                                       | CLK_STATE_READY     | 0               |
    |   157     |    95    | DEV_BOARD0_MCASP2_AFSR_OUT                                                        | CLK_STATE_READY     | 0               |
    |   157     |    96    | DEV_BOARD0_TRC_CLK_IN                                                             | CLK_STATE_READY     | 0               |
    |   157     |   100    | DEV_BOARD0_CSI1_RXCLKN_OUT                                                        | CLK_STATE_READY     | 0               |
    |   157     |   102    | DEV_BOARD0_MCASP0_ACLKX_OUT                                                       | CLK_STATE_READY     | 0               |
    |   157     |   103    | DEV_BOARD0_MCU_OSPI0_CLK_IN                                                       | CLK_STATE_READY     | 0               |
    |   157     |   105    | DEV_BOARD0_GPMC0_FCLK_MUX_IN                                                      | CLK_STATE_READY     | 133333333       |
    |   157     |   106    | DEV_BOARD0_MCU_SPI0_CLK_IN                                                        | CLK_STATE_READY     | 0               |
    |   157     |   108    | DEV_BOARD0_MCU_RGMII1_RXC_OUT                                                     | CLK_STATE_READY     | 0               |
    |   157     |   109    | DEV_BOARD0_MCASP0_AFSR_OUT                                                        | CLK_STATE_READY     | 0               |
    |   157     |   110    | DEV_BOARD0_CSI1_RXCLKP_OUT                                                        | CLK_STATE_READY     | 0               |
    |   157     |   111    | DEV_BOARD0_MCU_SYSCLKOUT0_IN                                                      | CLK_STATE_READY     | 250000000       |
    |   157     |   112    | DEV_BOARD0_SPI5_CLK_OUT                                                           | CLK_STATE_READY     | 0               |
    |   157     |   113    | DEV_BOARD0_MCU_RMII1_REF_CLK_OUT                                                  | CLK_STATE_READY     | 0               |
    |   157     |   114    | DEV_BOARD0_SPI0_CLK_OUT                                                           | CLK_STATE_READY     | 0               |
    |   157     |   116    | DEV_BOARD0_SPI6_CLK_OUT                                                           | CLK_STATE_READY     | 0               |
    |   157     |   117    | DEV_BOARD0_I2C1_SCL_IN                                                            | CLK_STATE_NOT_READY | 0               |
    |   157     |   118    | DEV_BOARD0_DSI1_TXCLKP_IN                                                         | CLK_STATE_NOT_READY | 0               |
    |   157     |   119    | DEV_BOARD0_MCAN0_RX_OUT                                                           | CLK_STATE_READY     | 0               |
    |   157     |   120    | DEV_BOARD0_MCASP0_ACLKR_OUT                                                       | CLK_STATE_READY     | 0               |
    |   157     |   121    | DEV_BOARD0_RMII_REF_CLK_OUT                                                       | CLK_STATE_READY     | 0               |
    |   157     |   123    | DEV_BOARD0_MCAN14_RX_OUT                                                          | CLK_STATE_READY     | 0               |
    |   157     |   125    | DEV_BOARD0_MCU_I2C0_SCL_OUT                                                       | CLK_STATE_READY     | 0               |
    |   157     |   126    | DEV_BOARD0_SPI6_CLK_IN                                                            | CLK_STATE_NOT_READY | 0               |
    |   157     |   128    | DEV_BOARD0_MCASP3_AFSX_OUT                                                        | CLK_STATE_READY     | 0               |
    |   157     |   129    | DEV_BOARD0_MCU_SPI1_CLK_OUT                                                       | CLK_STATE_READY     | 0               |
    |   157     |   130    | DEV_BOARD0_SERDES0_REFCLK_P_IN                                                    | CLK_STATE_READY     | 0               |
    |   157     |   131    | DEV_BOARD0_SERDES0_REFCLK_P_OUT                                                   | CLK_STATE_READY     | 0               |
    |   157     |   132    | DEV_BOARD0_MCASP1_ACLKR_IN                                                        | CLK_STATE_READY     | 0               |
    |   157     |   134    | DEV_BOARD0_MCASP1_AFSX_OUT                                                        | CLK_STATE_READY     | 0               |
    |   157     |   135    | DEV_BOARD0_SPI1_CLK_OUT                                                           | CLK_STATE_READY     | 0               |
    |   157     |   136    | DEV_BOARD0_I2C3_SCL_IN                                                            | CLK_STATE_NOT_READY | 0               |
    |   157     |   137    | DEV_BOARD0_MCU_I2C0_SCL_IN                                                        | CLK_STATE_READY     | 0               |
    |   157     |   138    | DEV_BOARD0_HYP1_TXPMCLK_IN                                                        | CLK_STATE_NOT_READY | 0               |
    |   157     |   139    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN                                                   | CLK_STATE_NOT_READY | 0               |
    |   157     |   140    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT             | CLK_STATE_READY     | 0               |
    |   157     |   141    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT             | CLK_STATE_READY     | 0               |
    |   157     |   142    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT             | CLK_STATE_READY     | 0               |
    |   157     |   143    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKR_POUT             | CLK_STATE_READY     | 0               |
    |   157     |   144    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKR_POUT             | CLK_STATE_READY     | 0               |
    |   157     |   152    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT             | CLK_STATE_READY     | 0               |
    |   157     |   153    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT             | CLK_STATE_READY     | 0               |
    |   157     |   154    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT             | CLK_STATE_READY     | 0               |
    |   157     |   155    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKX_POUT             | CLK_STATE_READY     | 0               |
    |   157     |   156    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKX_POUT             | CLK_STATE_READY     | 0               |
    |   157     |   164    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT           | CLK_STATE_NOT_READY | 0               |
    |   157     |   165    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1         | CLK_STATE_NOT_READY | 0               |
    |   157     |   166    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2         | CLK_STATE_NOT_READY | 0               |
    |   157     |   167    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3         | CLK_STATE_NOT_READY | 0               |
    |   157     |   168    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK          | CLK_STATE_READY     | 196608000       |
    |   157     |   173    | DEV_BOARD0_MCASP2_ACLKX_OUT                                                       | CLK_STATE_READY     | 0               |
    |   157     |   175    | DEV_BOARD0_MMC1_CLKLB_OUT                                                         | CLK_STATE_READY     | 0               |
    |   157     |   176    | DEV_BOARD0_WKUP_I2C0_SCL_OUT                                                      | CLK_STATE_READY     | 0               |
    |   157     |   177    | DEV_BOARD0_SYSCLKOUT0_IN                                                          | CLK_STATE_READY     | 125000000       |
    |   157     |   178    | DEV_BOARD0_I2C1_SCL_OUT                                                           | CLK_STATE_READY     | 0               |
    |   157     |   179    | DEV_BOARD0_MCU_OSPI0_LBCLKO_IN                                                    | CLK_STATE_READY     | 0               |
    |   157     |   180    | DEV_BOARD0_SPI3_CLK_IN                                                            | CLK_STATE_NOT_READY | 0               |
    |   157     |   181    | DEV_BOARD0_MCAN13_RX_OUT                                                          | CLK_STATE_READY     | 0               |
    |   157     |   182    | DEV_BOARD0_WKUP_I2C0_SCL_IN                                                       | CLK_STATE_READY     | 0               |
    |   157     |   183    | DEV_BOARD0_DSI1_TXCLKN_IN                                                         | CLK_STATE_NOT_READY | 0               |
    |   157     |   184    | DEV_BOARD0_CPTS0_RFT_CLK_OUT                                                      | CLK_STATE_READY     | 0               |
    |   157     |   185    | DEV_BOARD0_MCU_I2C1_SCL_OUT                                                       | CLK_STATE_READY     | 0               |
    |   157     |   186    | DEV_BOARD0_MCASP0_ACLKR_IN                                                        | CLK_STATE_READY     | 0               |
    |   157     |   187    | DEV_BOARD0_MCU_OSPI1_LBCLKO_IN                                                    | CLK_STATE_READY     | 0               |
    |   157     |   188    | DEV_BOARD0_MCASP0_AFSX_OUT                                                        | CLK_STATE_READY     | 0               |
    |   157     |   190    | DEV_BOARD0_MCU_I3C0_SDA_OUT                                                       | CLK_STATE_READY     | 0               |
    |   157     |   191    | DEV_BOARD0_MCASP0_ACLKX_IN                                                        | CLK_STATE_READY     | 0               |
    |   157     |   192    | DEV_BOARD0_AUDIO_EXT_REFCLK0_OUT                                                  | CLK_STATE_READY     | 0               |
    |   157     |   193    | DEV_BOARD0_MCAN3_RX_OUT                                                           | CLK_STATE_READY     | 0               |
    |   157     |   194    | DEV_BOARD0_MMC1_CLKLB_IN                                                          | CLK_STATE_READY     | 0               |
    |   157     |   195    | DEV_BOARD0_MCASP2_ACLKR_OUT                                                       | CLK_STATE_READY     | 0               |
    |   157     |   198    | DEV_BOARD0_HFOSC1_CLK_OUT                                                         | CLK_STATE_READY     | 0               |
    |   157     |   199    | DEV_BOARD0_MCASP1_ACLKR_OUT                                                       | CLK_STATE_READY     | 0               |
    |   157     |   200    | DEV_BOARD0_MCAN4_RX_OUT                                                           | CLK_STATE_READY     | 0               |
    |   157     |   201    | DEV_BOARD0_MCASP4_ACLKX_OUT                                                       | CLK_STATE_READY     | 0               |
    |   157     |   202    | DEV_BOARD0_CSI1_TXCLKP_IN                                                         | CLK_STATE_NOT_READY | 0               |
    |   157     |   203    | DEV_BOARD0_MCASP3_AFSR_OUT                                                        | CLK_STATE_READY     | 0               |
    |   157     |   204    | DEV_BOARD0_LED_CLK_OUT                                                            | CLK_STATE_READY     | 0               |
    |   157     |   206    | DEV_BOARD0_MCAN7_RX_OUT                                                           | CLK_STATE_READY     | 0               |
    |   157     |   207    | DEV_BOARD0_MCU_MDIO0_MDC_IN                                                       | CLK_STATE_READY     | 0               |
    |   157     |   209    | DEV_BOARD0_MCASP4_ACLKR_IN                                                        | CLK_STATE_READY     | 0               |
    |   157     |   210    | DEV_BOARD0_I2C2_SCL_IN                                                            | CLK_STATE_NOT_READY | 0               |
    |   157     |   212    | DEV_BOARD0_SPI1_CLK_IN                                                            | CLK_STATE_NOT_READY | 0               |
    |   157     |   213    | DEV_BOARD0_HYP1_RXPMCLK_OUT                                                       | CLK_STATE_READY     | 0               |
    |   157     |   214    | DEV_BOARD0_MCU_HYPERBUS0_CK_IN                                                    | CLK_STATE_READY     | 0               |
    |   157     |   215    | DEV_BOARD0_MCASP2_AFSX_OUT                                                        | CLK_STATE_READY     | 0               |
    |   157     |   216    | DEV_BOARD0_MCASP3_ACLKR_OUT                                                       | CLK_STATE_READY     | 0               |
    |   157     |   217    | DEV_BOARD0_MCAN15_RX_OUT                                                          | CLK_STATE_READY     | 0               |
    |   157     |   218    | DEV_BOARD0_SPI0_CLK_IN                                                            | CLK_STATE_NOT_READY | 0               |
    |   157     |   219    | DEV_BOARD0_MCAN12_RX_OUT                                                          | CLK_STATE_READY     | 0               |
    |   157     |   220    | DEV_BOARD0_MCASP2_ACLKR_IN                                                        | CLK_STATE_READY     | 0               |
    |   157     |   221    | DEV_BOARD0_MCU_CLKOUT0_IN                                                         | CLK_STATE_READY     | 50000000        |
    |   157     |   222    | DEV_BOARD0_MCU_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT0_CLK5                | CLK_STATE_READY     | 50000000        |
    |   157     |   223    | DEV_BOARD0_MCU_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT0_CLK10               | CLK_STATE_READY     | 25000000        |
    |   157     |   224    | DEV_BOARD0_MCU_OSPI1_DQS_OUT                                                      | CLK_STATE_READY     | 0               |
    |   157     |   226    | DEV_BOARD0_CSI0_RXCLKN_OUT                                                        | CLK_STATE_READY     | 0               |
    |   157     |   227    | DEV_BOARD0_TCK_OUT                                                                | CLK_STATE_READY     | 0               |
    |   157     |   228    | DEV_BOARD0_CSI1_TXCLKN_IN                                                         | CLK_STATE_NOT_READY | 0               |
    |   157     |   229    | DEV_BOARD0_MCU_MCAN0_RX_OUT                                                       | CLK_STATE_READY     | 0               |
    |   157     |   230    | DEV_BOARD0_MCASP4_AFSR_OUT                                                        | CLK_STATE_READY     | 0               |
    |   157     |   231    | DEV_BOARD0_MCU_HYPERBUS0_CKN_IN                                                   | CLK_STATE_READY     | 0               |
    |   157     |   232    | DEV_BOARD0_MCASP4_ACLKR_OUT                                                       | CLK_STATE_READY     | 0               |
    |   157     |   233    | DEV_BOARD0_MCAN11_RX_OUT                                                          | CLK_STATE_READY     | 0               |
    |   157     |   234    | DEV_BOARD0_I2C5_SCL_IN                                                            | CLK_STATE_NOT_READY | 0               |
    |   157     |   235    | DEV_BOARD0_MCU_I2C1_SCL_IN                                                        | CLK_STATE_READY     | 0               |
    |   157     |   236    | DEV_BOARD0_I2C0_SCL_OUT                                                           | CLK_STATE_READY     | 0               |
    |   157     |   237    | DEV_BOARD0_MCAN6_RX_OUT                                                           | CLK_STATE_READY     | 0               |
    |   157     |   238    | DEV_BOARD0_MCU_I3C0_SCL_IN                                                        | CLK_STATE_NOT_READY | 0               |
    |   157     |   239    | DEV_BOARD0_MMC1_CLK_OUT                                                           | CLK_STATE_READY     | 0               |
    |   157     |   240    | DEV_BOARD0_VOUT0_EXTPCLKIN_OUT                                                    | CLK_STATE_READY     | 0               |
    |   157     |   241    | DEV_BOARD0_EXT_REFCLK1_OUT                                                        | CLK_STATE_READY     | 0               |
    |   157     |   242    | DEV_BOARD0_I2C5_SCL_OUT                                                           | CLK_STATE_READY     | 0               |
    |   157     |   243    | DEV_BOARD0_MCAN16_RX_OUT                                                          | CLK_STATE_READY     | 0               |
    |   157     |   244    | DEV_BOARD0_MCU_RGMII1_TXC_IN                                                      | CLK_STATE_READY     | 0               |
    |   157     |   245    | DEV_BOARD0_MCASP4_ACLKX_IN                                                        | CLK_STATE_READY     | 0               |
    |   157     |   246    | DEV_BOARD0_GPMC0_CLKOUT_IN                                                        | CLK_STATE_NOT_READY | 0               |
    |   157     |   247    | DEV_BOARD0_GPMC0_CLK_OUT                                                          | CLK_STATE_READY     | 0               |
    |   157     |   248    | DEV_BOARD0_I2C6_SCL_IN                                                            | CLK_STATE_NOT_READY | 0               |
    |   157     |   249    | DEV_BOARD0_I2C4_SCL_IN                                                            | CLK_STATE_NOT_READY | 0               |
    |   157     |   250    | DEV_BOARD0_SERDES0_REFCLK_N_IN                                                    | CLK_STATE_READY     | 0               |
    |   157     |   251    | DEV_BOARD0_OBSCLK0_IN                                                             | CLK_STATE_READY     | 500000000       |
    |   157     |   252    | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK                    | CLK_STATE_READY     | 500000000       |
    |   157     |   253    | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT0_CLK                    | CLK_STATE_READY     | 192000000       |
    |   157     |   254    | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK                    | CLK_STATE_READY     | 600000000       |
    |   157     |   255    | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT0_CLK                    | CLK_STATE_READY     | 250000000       |
    |   157     |   256    | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT0_CLK                    | CLK_STATE_READY     | 196608000       |
    |   157     |   257    | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_5_HSDIVOUT0_CLK                    | CLK_STATE_READY     | 400000000       |
    |   157     |   258    | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MAIN_6_HSDIVOUT0_CLK                    | CLK_STATE_READY     | 800000000       |
    |   157     |   259    | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MAIN_26_HSDIVOUT0_CLK                   | CLK_STATE_READY     | 1066500000      |
    |   157     |   264    | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MAIN_12_HSDIVOUT0_CLK                   | CLK_STATE_READY     | 1066500000      |
    |   157     |   265    | DEV_BOARD0_OBSCLK0_IN_PARENT_OBSCLK1_MUX_OUT0                                     | CLK_STATE_NOT_READY | 0               |
    |   157     |   266    | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV2_16FFT_MAIN_14_HSDIVOUT0_CLK                   | CLK_STATE_READY     | 1000000000      |
    |   157     |   268    | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK                   | CLK_STATE_READY     | 594000000       |
    |   157     |   269    | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT0_CLK                   | CLK_STATE_READY     | 51200000        |
    |   157     |   271    | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_19_HSDIVOUT0_CLK                   | CLK_STATE_READY     | 600000000       |
    |   157     |   277    | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_25_HSDIVOUT0_CLK                   | CLK_STATE_READY     | 480000000       |
    |   157     |   278    | DEV_BOARD0_OBSCLK0_IN_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF3                      | CLK_STATE_READY     | 0               |
    |   157     |   279    | DEV_BOARD0_OBSCLK0_IN_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK         | CLK_STATE_READY     | 12500000        |
    |   157     |   280    | DEV_BOARD0_OBSCLK0_IN_PARENT_GLUELOGIC_LPXOSC_CLKOUT                              | CLK_STATE_READY     | 32768           |
    |   157     |   281    | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK_DUP0               | CLK_STATE_READY     | 500000000       |
    |   157     |   282    | DEV_BOARD0_OBSCLK0_IN_PARENT_BOARD_0_HFOSC1_CLK_OUT                               | CLK_STATE_READY     | 0               |
    |   157     |   283    | DEV_BOARD0_OBSCLK0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT                              | CLK_STATE_READY     | 19200000        |
    |   157     |   284    | DEV_BOARD0_MCAN2_RX_OUT                                                           | CLK_STATE_READY     | 0               |
    |   157     |   285    | DEV_BOARD0_MCASP2_ACLKX_IN                                                        | CLK_STATE_READY     | 0               |
    |   157     |   287    | DEV_BOARD0_MCU_EXT_REFCLK0_OUT                                                    | CLK_STATE_READY     | 0               |
    |   157     |   288    | DEV_BOARD0_MCASP1_ACLKX_OUT                                                       | CLK_STATE_READY     | 0               |
    |   157     |   289    | DEV_BOARD0_SPI2_CLK_OUT                                                           | CLK_STATE_READY     | 0               |
    |   157     |   290    | DEV_BOARD0_HYP0_RXFLCLK_IN                                                        | CLK_STATE_NOT_READY | 0               |
    |   157     |   291    | DEV_BOARD0_SPI3_CLK_OUT                                                           | CLK_STATE_READY     | 0               |
    |   157     |   292    | DEV_BOARD0_MCASP1_AFSR_OUT                                                        | CLK_STATE_READY     | 0               |
    |   157     |   293    | DEV_BOARD0_I2C2_SCL_OUT                                                           | CLK_STATE_READY     | 0               |
    |   157     |   294    | DEV_BOARD0_MCAN10_RX_OUT                                                          | CLK_STATE_READY     | 0               |
    |   157     |   295    | DEV_BOARD0_MCAN5_RX_OUT                                                           | CLK_STATE_READY     | 0               |
    |   157     |   296    | DEV_BOARD0_MCU_I3C0_SCL_OUT                                                       | CLK_STATE_READY     | 0               |
    |   157     |   297    | DEV_BOARD0_MCU_MCAN1_RX_OUT                                                       | CLK_STATE_READY     | 0               |
    |   157     |   299    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN                                                   | CLK_STATE_NOT_READY | 0               |
    |   157     |   300    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT             | CLK_STATE_READY     | 0               |
    |   157     |   301    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT             | CLK_STATE_READY     | 0               |
    |   157     |   302    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT             | CLK_STATE_READY     | 0               |
    |   157     |   303    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKR_POUT             | CLK_STATE_READY     | 0               |
    |   157     |   304    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKR_POUT             | CLK_STATE_READY     | 0               |
    |   157     |   312    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT             | CLK_STATE_READY     | 0               |
    |   157     |   313    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT             | CLK_STATE_READY     | 0               |
    |   157     |   314    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT             | CLK_STATE_READY     | 0               |
    |   157     |   315    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKX_POUT             | CLK_STATE_READY     | 0               |
    |   157     |   316    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKX_POUT             | CLK_STATE_READY     | 0               |
    |   157     |   324    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT           | CLK_STATE_NOT_READY | 0               |
    |   157     |   325    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1         | CLK_STATE_NOT_READY | 0               |
    |   157     |   326    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2         | CLK_STATE_NOT_READY | 0               |
    |   157     |   327    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3         | CLK_STATE_NOT_READY | 0               |
    |   157     |   328    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK          | CLK_STATE_READY     | 196608000       |
    |   157     |   333    | DEV_BOARD0_HYP1_TXFLCLK_OUT                                                       | CLK_STATE_READY     | 0               |
    |   157     |   334    | DEV_BOARD0_SPI5_CLK_IN                                                            | CLK_STATE_NOT_READY | 0               |
    |   157     |   335    | DEV_BOARD0_I2C3_SCL_OUT                                                           | CLK_STATE_READY     | 0               |
    |   157     |   336    | DEV_BOARD0_MCAN8_RX_OUT                                                           | CLK_STATE_READY     | 0               |
    |   157     |   338    | DEV_BOARD0_RGMII1_RXC_OUT                                                         | CLK_STATE_READY     | 0               |
    |   157     |   339    | DEV_BOARD0_SERDES0_REFCLK_N_OUT                                                   | CLK_STATE_READY     | 0               |
    |   157     |   340    | DEV_BOARD0_CSI0_TXCLKP_IN                                                         | CLK_STATE_READY     | 0               |
    |   157     |   341    | DEV_BOARD0_SPI7_CLK_IN                                                            | CLK_STATE_NOT_READY | 0               |
    |   157     |   342    | DEV_BOARD0_RGMII1_TXC_IN                                                          | CLK_STATE_NOT_READY | 0               |
    |   157     |   343    | DEV_BOARD0_HYP1_RXFLCLK_IN                                                        | CLK_STATE_NOT_READY | 0               |
    |   157     |   344    | DEV_BOARD0_MDIO1_MDC_IN                                                           | CLK_STATE_NOT_READY | 0               |
    |   157     |   345    | DEV_BOARD0_SPI2_CLK_IN                                                            | CLK_STATE_NOT_READY | 0               |
    |   157     |   346    | DEV_BOARD0_DSI0_TXCLKP_IN                                                         | CLK_STATE_READY     | 0               |
    |   157     |   347    | DEV_BOARD0_MCASP4_AFSX_OUT                                                        | CLK_STATE_READY     | 0               |
    |   157     |   352    | DEV_BOARD0_VOUT0_PCLK_IN                                                          | CLK_STATE_READY     | 600000000       |
    |   150     |     0    | DEV_CMPEVENT_INTRTR0_INTR_CLK                                                     | CLK_STATE_READY     | 125000000       |
    |   179     |     0    | DEV_CODEC0_VPU_PCLK_CLK                                                           | CLK_STATE_READY     | 600000000       |
    |   179     |     1    | DEV_CODEC0_VPU_BCLK_CLK                                                           | CLK_STATE_READY     | 400000000       |
    |   179     |     2    | DEV_CODEC0_VPU_CCLK_CLK                                                           | CLK_STATE_READY     | 600000000       |
    |   179     |     3    | DEV_CODEC0_VPU_ACLK_CLK                                                           | CLK_STATE_READY     | 600000000       |
    |     8     |     0    | DEV_COMPUTE_CLUSTER0_C71SS0_0_C7X_CLK                                             | CLK_STATE_READY     | 1000000000      |
    |     8     |     1    | DEV_COMPUTE_CLUSTER0_C71SS0_0_PLL_CTRL_CLK                                        | CLK_STATE_READY     | 500000000       |
    |     8     |     3    | DEV_COMPUTE_CLUSTER0_C71SS0_0_C7X_DIVH_CLK4_OBSCLK_OUT_CLK                        | CLK_STATE_READY     | 0               |
    |    11     |     0    | DEV_COMPUTE_CLUSTER0_C71SS1_0_C7X_CLK                                             | CLK_STATE_READY     | 1000000000      |
    |    11     |     1    | DEV_COMPUTE_CLUSTER0_C71SS1_0_PLL_CTRL_CLK                                        | CLK_STATE_READY     | 500000000       |
    |    14     |     1    | DEV_COMPUTE_CLUSTER0_CLEC_CLK1_CLK                                                | CLK_STATE_READY     | 500000000       |
    |    15     |     1    | DEV_COMPUTE_CLUSTER0_CORE_CORE_CLK1_CLK                                           | CLK_STATE_READY     | 500000000       |
    |    15     |     2    | DEV_COMPUTE_CLUSTER0_CORE_CORE_PSIL_LEAF_CLK                                      | CLK_STATE_READY     | 500000000       |
    |    18     |     0    | DEV_COMPUTE_CLUSTER0_DEBUG_WRAP_0_CLK1_CLK_CLK                                    | CLK_STATE_READY     | 1000000000      |
    |    18     |     1    | DEV_COMPUTE_CLUSTER0_DEBUG_WRAP_0_CLK2_CLK_CLK                                    | CLK_STATE_READY     | 500000000       |
    |    25     |     0    | DEV_COMPUTE_CLUSTER0_EN_MSMC_DOMAIN_0_MSMC_CLK1_CLK                               | CLK_STATE_READY     | 500000000       |
    |    26     |     0    | DEV_COMPUTE_CLUSTER0_GIC500SS_VCLK_CLK                                            | CLK_STATE_READY     | 500000000       |
    |    27     |     3    | DEV_COMPUTE_CLUSTER0_PBIST_WRAP_0_DIVP_CLK1_CLK_CLK                               | CLK_STATE_READY     | 1000000000      |
    |    27     |     4    | DEV_COMPUTE_CLUSTER0_PBIST_WRAP_0_DIVH_CLK2_CLK_CLK                               | CLK_STATE_READY     | 500000000       |
    |    28     |     0    | DEV_CPSW1_MDIO_MDCLK_O                                                            | CLK_STATE_READY     | 0               |
    |    28     |     1    | DEV_CPSW1_CPTS_GENF0                                                              | CLK_STATE_READY     | 0               |
    |    28     |     3    | DEV_CPSW1_CPTS_RFT_CLK                                                            | CLK_STATE_READY     | 250000000       |
    |    28     |     4    | DEV_CPSW1_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK                   | CLK_STATE_READY     | 250000000       |
    |    28     |     5    | DEV_CPSW1_CPTS_RFT_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK                 | CLK_STATE_READY     | 200000000       |
    |    28     |     6    | DEV_CPSW1_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT                       | CLK_STATE_READY     | 0               |
    |    28     |     7    | DEV_CPSW1_CPTS_RFT_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT                           | CLK_STATE_READY     | 0               |
    |    28     |     8    | DEV_CPSW1_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                         | CLK_STATE_READY     | 0               |
    |    28     |     9    | DEV_CPSW1_CPTS_RFT_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT                             | CLK_STATE_READY     | 0               |
    |    28     |    10    | DEV_CPSW1_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN0_TXMCLK                  | CLK_STATE_READY     | 0               |
    |    28     |    11    | DEV_CPSW1_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN1_TXMCLK                  | CLK_STATE_READY     | 0               |
    |    28     |    12    | DEV_CPSW1_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN2_TXMCLK                  | CLK_STATE_READY     | 0               |
    |    28     |    13    | DEV_CPSW1_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN3_TXMCLK                  | CLK_STATE_READY     | 0               |
    |    28     |    18    | DEV_CPSW1_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK                    | CLK_STATE_READY     | 500000000       |
    |    28     |    19    | DEV_CPSW1_CPTS_RFT_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK           | CLK_STATE_READY     | 500000000       |
    |    28     |    20    | DEV_CPSW1_GMII1_MR_CLK                                                            | CLK_STATE_READY     | 25000000        |
    |    28     |    21    | DEV_CPSW1_GMII_RFT_CLK                                                            | CLK_STATE_READY     | 125000000       |
    |    28     |    22    | DEV_CPSW1_RGMII1_RXC_I                                                            | CLK_STATE_READY     | 0               |
    |    28     |    26    | DEV_CPSW1_RMII_MHZ_50_CLK                                                         | CLK_STATE_READY     | 0               |
    |    28     |    27    | DEV_CPSW1_RGMII1_TXC_O                                                            | CLK_STATE_READY     | 0               |
    |    28     |    28    | DEV_CPSW1_CPPI_CLK_CLK                                                            | CLK_STATE_READY     | 320000000       |
    |    28     |    29    | DEV_CPSW1_RGMII_MHZ_5_CLK                                                         | CLK_STATE_READY     | 5000000         |
    |    28     |    30    | DEV_CPSW1_GMII1_MT_CLK                                                            | CLK_STATE_READY     | 25000000        |
    |    28     |    32    | DEV_CPSW1_RGMII_MHZ_50_CLK                                                        | CLK_STATE_READY     | 50000000        |
    |    28     |    33    | DEV_CPSW1_RGMII_MHZ_250_CLK                                                       | CLK_STATE_READY     | 250000000       |
    |    36     |     0    | DEV_CPT2_AGGR0_VCLK_CLK                                                           | CLK_STATE_READY     | 250000000       |
    |    30     |     0    | DEV_CPT2_AGGR1_VCLK_CLK                                                           | CLK_STATE_READY     | 250000000       |
    |    32     |     0    | DEV_CPT2_AGGR2_VCLK_CLK                                                           | CLK_STATE_READY     | 250000000       |
    |    34     |     0    | DEV_CPT2_AGGR3_VCLK_CLK                                                           | CLK_STATE_READY     | 250000000       |
    |    33     |     0    | DEV_CPT2_AGGR4_VCLK_CLK                                                           | CLK_STATE_READY     | 250000000       |
    |    31     |     0    | DEV_CPT2_AGGR5_VCLK_CLK                                                           | CLK_STATE_READY     | 250000000       |
    |   136     |     0    | DEV_CSI_PSILSS0_MAIN_CLK                                                          | CLK_STATE_READY     | 125000000       |
    |    38     |     0    | DEV_CSI_RX_IF0_PPI_D_RX_ULPS_ESC                                                  | CLK_STATE_NOT_READY | 0               |
    |    38     |     1    | DEV_CSI_RX_IF0_VBUS_CLK_CLK                                                       | CLK_STATE_READY     | 250000000       |
    |    38     |     2    | DEV_CSI_RX_IF0_PPI_RX_BYTE_CLK                                                    | CLK_STATE_NOT_READY | 0               |
    |    38     |     3    | DEV_CSI_RX_IF0_MAIN_CLK_CLK                                                       | CLK_STATE_READY     | 500000000       |
    |    38     |     4    | DEV_CSI_RX_IF0_VP_CLK_CLK                                                         | CLK_STATE_READY     | 720000000       |
    |    39     |     0    | DEV_CSI_RX_IF1_PPI_D_RX_ULPS_ESC                                                  | CLK_STATE_NOT_READY | 0               |
    |    39     |     1    | DEV_CSI_RX_IF1_VBUS_CLK_CLK                                                       | CLK_STATE_READY     | 250000000       |
    |    39     |     2    | DEV_CSI_RX_IF1_PPI_RX_BYTE_CLK                                                    | CLK_STATE_NOT_READY | 0               |
    |    39     |     3    | DEV_CSI_RX_IF1_MAIN_CLK_CLK                                                       | CLK_STATE_READY     | 500000000       |
    |    39     |     4    | DEV_CSI_RX_IF1_VP_CLK_CLK                                                         | CLK_STATE_READY     | 720000000       |
    |    40     |     1    | DEV_CSI_TX_IF_V2_0_VBUS_CLK_CLK                                                   | CLK_STATE_READY     | 250000000       |
    |    40     |     2    | DEV_CSI_TX_IF_V2_0_MAIN_CLK_CLK                                                   | CLK_STATE_READY     | 500000000       |
    |    40     |     3    | DEV_CSI_TX_IF_V2_0_DPHY_TXBYTECLKHS_CL_CLK                                        | CLK_STATE_READY     | 0               |
    |    40     |     5    | DEV_CSI_TX_IF_V2_0_ESC_CLK_CLK                                                    | CLK_STATE_READY     | 20000000        |
    |    41     |     1    | DEV_CSI_TX_IF_V2_1_VBUS_CLK_CLK                                                   | CLK_STATE_READY     | 250000000       |
    |    41     |     2    | DEV_CSI_TX_IF_V2_1_MAIN_CLK_CLK                                                   | CLK_STATE_READY     | 500000000       |
    |    41     |     3    | DEV_CSI_TX_IF_V2_1_DPHY_TXBYTECLKHS_CL_CLK                                        | CLK_STATE_NOT_READY | 0               |
    |    41     |     5    | DEV_CSI_TX_IF_V2_1_ESC_CLK_CLK                                                    | CLK_STATE_READY     | 20000000        |
    |    43     |     0    | DEV_DCC0_DCC_CLKSRC0_CLK                                                          | CLK_STATE_READY     | 250000000       |
    |    43     |     1    | DEV_DCC0_DCC_CLKSRC1_CLK                                                          | CLK_STATE_READY     | 200000000       |
    |    43     |     2    | DEV_DCC0_DCC_CLKSRC2_CLK                                                          | CLK_STATE_READY     | 133333333       |
    |    43     |     3    | DEV_DCC0_DCC_CLKSRC3_CLK                                                          | CLK_STATE_READY     | 80000000        |
    |    43     |     4    | DEV_DCC0_DCC_CLKSRC4_CLK                                                          | CLK_STATE_READY     | 19200000        |
    |    43     |     5    | DEV_DCC0_DCC_CLKSRC5_CLK                                                          | CLK_STATE_READY     | 0               |
    |    43     |     6    | DEV_DCC0_DCC_CLKSRC6_CLK                                                          | CLK_STATE_READY     | 500000000       |
    |    43     |     7    | DEV_DCC0_DCC_CLKSRC7_CLK                                                          | CLK_STATE_NOT_READY | 0               |
    |    43     |     8    | DEV_DCC0_DCC_INPUT00_CLK                                                          | CLK_STATE_READY     | 19200000        |
    |    43     |     9    | DEV_DCC0_DCC_INPUT01_CLK                                                          | CLK_STATE_READY     | 0               |
    |    43     |    10    | DEV_DCC0_DCC_INPUT02_CLK                                                          | CLK_STATE_READY     | 12500000        |
    |    43     |    11    | DEV_DCC0_DCC_INPUT10_CLK                                                          | CLK_STATE_READY     | 250000000       |
    |    43     |    12    | DEV_DCC0_VBUS_CLK                                                                 | CLK_STATE_READY     | 125000000       |
    |    44     |     0    | DEV_DCC1_DCC_CLKSRC0_CLK                                                          | CLK_STATE_READY     | 50000000        |
    |    44     |     1    | DEV_DCC1_DCC_CLKSRC1_CLK                                                          | CLK_STATE_READY     | 200000000       |
    |    44     |     2    | DEV_DCC1_DCC_CLKSRC2_CLK                                                          | CLK_STATE_READY     | 200000000       |
    |    44     |     3    | DEV_DCC1_DCC_CLKSRC3_CLK                                                          | CLK_STATE_READY     | 192000000       |
    |    44     |     4    | DEV_DCC1_DCC_CLKSRC4_CLK                                                          | CLK_STATE_READY     | 320000000       |
    |    44     |     5    | DEV_DCC1_DCC_CLKSRC5_CLK                                                          | CLK_STATE_READY     | 192000000       |
    |    44     |     6    | DEV_DCC1_DCC_CLKSRC6_CLK                                                          | CLK_STATE_READY     | 192000000       |
    |    44     |     7    | DEV_DCC1_DCC_CLKSRC7_CLK                                                          | CLK_STATE_READY     | 19200000        |
    |    44     |     8    | DEV_DCC1_DCC_INPUT00_CLK                                                          | CLK_STATE_READY     | 19200000        |
    |    44     |     9    | DEV_DCC1_DCC_INPUT01_CLK                                                          | CLK_STATE_READY     | 0               |
    |    44     |    10    | DEV_DCC1_DCC_INPUT02_CLK                                                          | CLK_STATE_READY     | 12500000        |
    |    44     |    11    | DEV_DCC1_DCC_INPUT10_CLK                                                          | CLK_STATE_READY     | 125000000       |
    |    44     |    12    | DEV_DCC1_VBUS_CLK                                                                 | CLK_STATE_READY     | 125000000       |
    |    45     |     0    | DEV_DCC2_DCC_CLKSRC0_CLK                                                          | CLK_STATE_READY     | 24000000        |
    |    45     |     1    | DEV_DCC2_DCC_CLKSRC1_CLK                                                          | CLK_STATE_READY     | 20000000        |
    |    45     |     3    | DEV_DCC2_DCC_CLKSRC3_CLK                                                          | CLK_STATE_READY     | 100000000       |
    |    45     |     4    | DEV_DCC2_DCC_CLKSRC4_CLK                                                          | CLK_STATE_READY     | 225000000       |
    |    45     |     5    | DEV_DCC2_DCC_CLKSRC5_CLK                                                          | CLK_STATE_READY     | 300000000       |
    |    45     |     6    | DEV_DCC2_DCC_CLKSRC6_CLK                                                          | CLK_STATE_READY     | 200000000       |
    |    45     |     7    | DEV_DCC2_DCC_CLKSRC7_CLK                                                          | CLK_STATE_READY     | 250000000       |
    |    45     |     8    | DEV_DCC2_DCC_INPUT00_CLK                                                          | CLK_STATE_READY     | 19200000        |
    |    45     |     9    | DEV_DCC2_DCC_INPUT01_CLK                                                          | CLK_STATE_READY     | 0               |
    |    45     |    10    | DEV_DCC2_DCC_INPUT02_CLK                                                          | CLK_STATE_READY     | 12500000        |
    |    45     |    11    | DEV_DCC2_DCC_INPUT10_CLK                                                          | CLK_STATE_READY     | 125000000       |
    |    45     |    12    | DEV_DCC2_VBUS_CLK                                                                 | CLK_STATE_READY     | 125000000       |
    |    46     |     0    | DEV_DCC3_DCC_CLKSRC0_CLK                                                          | CLK_STATE_READY     | 196608000       |
    |    46     |     1    | DEV_DCC3_DCC_CLKSRC1_CLK                                                          | CLK_STATE_READY     | 200000000       |
    |    46     |     2    | DEV_DCC3_DCC_CLKSRC2_CLK                                                          | CLK_STATE_READY     | 300000000       |
    |    46     |     5    | DEV_DCC3_DCC_CLKSRC5_CLK                                                          | CLK_STATE_READY     | 200000000       |
    |    46     |     6    | DEV_DCC3_DCC_CLKSRC6_CLK                                                          | CLK_STATE_READY     | 250000000       |
    |    46     |     7    | DEV_DCC3_DCC_CLKSRC7_CLK                                                          | CLK_STATE_READY     | 500000000       |
    |    46     |     8    | DEV_DCC3_DCC_INPUT00_CLK                                                          | CLK_STATE_READY     | 19200000        |
    |    46     |     9    | DEV_DCC3_DCC_INPUT01_CLK                                                          | CLK_STATE_READY     | 0               |
    |    46     |    10    | DEV_DCC3_DCC_INPUT02_CLK                                                          | CLK_STATE_READY     | 12500000        |
    |    46     |    11    | DEV_DCC3_DCC_INPUT10_CLK                                                          | CLK_STATE_READY     | 125000000       |
    |    46     |    12    | DEV_DCC3_VBUS_CLK                                                                 | CLK_STATE_READY     | 125000000       |
    |    47     |     0    | DEV_DCC4_DCC_CLKSRC0_CLK                                                          | CLK_STATE_READY     | 200000000       |
    |    47     |     2    | DEV_DCC4_DCC_CLKSRC2_CLK                                                          | CLK_STATE_READY     | 266625000       |
    |    47     |     3    | DEV_DCC4_DCC_CLKSRC3_CLK                                                          | CLK_STATE_READY     | 266625000       |
    |    47     |     4    | DEV_DCC4_DCC_CLKSRC4_CLK                                                          | CLK_STATE_READY     | 250000000       |
    |    47     |     5    | DEV_DCC4_DCC_CLKSRC5_CLK                                                          | CLK_STATE_READY     | 250000000       |
    |    47     |     7    | DEV_DCC4_DCC_CLKSRC7_CLK                                                          | CLK_STATE_READY     | 297000000       |
    |    47     |     8    | DEV_DCC4_DCC_INPUT00_CLK                                                          | CLK_STATE_READY     | 19200000        |
    |    47     |     9    | DEV_DCC4_DCC_INPUT01_CLK                                                          | CLK_STATE_READY     | 0               |
    |    47     |    10    | DEV_DCC4_DCC_INPUT02_CLK                                                          | CLK_STATE_READY     | 12500000        |
    |    47     |    11    | DEV_DCC4_DCC_INPUT10_CLK                                                          | CLK_STATE_READY     | 250000000       |
    |    47     |    12    | DEV_DCC4_VBUS_CLK                                                                 | CLK_STATE_READY     | 125000000       |
    |    48     |     1    | DEV_DCC5_DCC_CLKSRC1_CLK                                                          | CLK_STATE_READY     | 300000000       |
    |    48     |     2    | DEV_DCC5_DCC_CLKSRC2_CLK                                                          | CLK_STATE_READY     | 25600000        |
    |    48     |     3    | DEV_DCC5_DCC_CLKSRC3_CLK                                                          | CLK_STATE_READY     | 240000000       |
    |    48     |     4    | DEV_DCC5_DCC_CLKSRC4_CLK                                                          | CLK_STATE_READY     | 360000000       |
    |    48     |     6    | DEV_DCC5_DCC_CLKSRC6_CLK                                                          | CLK_STATE_READY     | 0               |
    |    48     |     7    | DEV_DCC5_DCC_CLKSRC7_CLK                                                          | CLK_STATE_READY     | 0               |
    |    48     |     8    | DEV_DCC5_DCC_INPUT00_CLK                                                          | CLK_STATE_READY     | 19200000        |
    |    48     |     9    | DEV_DCC5_DCC_INPUT01_CLK                                                          | CLK_STATE_READY     | 0               |
    |    48     |    10    | DEV_DCC5_DCC_INPUT02_CLK                                                          | CLK_STATE_READY     | 12500000        |
    |    48     |    11    | DEV_DCC5_DCC_INPUT10_CLK                                                          | CLK_STATE_READY     | 500000000       |
    |    48     |    12    | DEV_DCC5_VBUS_CLK                                                                 | CLK_STATE_READY     | 125000000       |
    |    49     |     0    | DEV_DCC6_DCC_CLKSRC0_CLK                                                          | CLK_STATE_READY     | 0               |
    |    49     |     1    | DEV_DCC6_DCC_CLKSRC1_CLK                                                          | CLK_STATE_READY     | 0               |
    |    49     |     2    | DEV_DCC6_DCC_CLKSRC2_CLK                                                          | CLK_STATE_READY     | 0               |
    |    49     |     3    | DEV_DCC6_DCC_CLKSRC3_CLK                                                          | CLK_STATE_READY     | 0               |
    |    49     |     4    | DEV_DCC6_DCC_CLKSRC4_CLK                                                          | CLK_STATE_READY     | 0               |
    |    49     |     5    | DEV_DCC6_DCC_CLKSRC5_CLK                                                          | CLK_STATE_READY     | 0               |
    |    49     |     6    | DEV_DCC6_DCC_CLKSRC6_CLK                                                          | CLK_STATE_READY     | 0               |
    |    49     |     7    | DEV_DCC6_DCC_CLKSRC7_CLK                                                          | CLK_STATE_READY     | 0               |
    |    49     |     8    | DEV_DCC6_DCC_INPUT00_CLK                                                          | CLK_STATE_READY     | 19200000        |
    |    49     |     9    | DEV_DCC6_DCC_INPUT01_CLK                                                          | CLK_STATE_READY     | 0               |
    |    49     |    10    | DEV_DCC6_DCC_INPUT02_CLK                                                          | CLK_STATE_READY     | 12500000        |
    |    49     |    11    | DEV_DCC6_DCC_INPUT10_CLK                                                          | CLK_STATE_READY     | 125000000       |
    |    49     |    12    | DEV_DCC6_VBUS_CLK                                                                 | CLK_STATE_READY     | 125000000       |
    |    50     |     0    | DEV_DCC7_DCC_CLKSRC0_CLK                                                          | CLK_STATE_READY     | 0               |
    |    50     |     1    | DEV_DCC7_DCC_CLKSRC1_CLK                                                          | CLK_STATE_READY     | 0               |
    |    50     |     2    | DEV_DCC7_DCC_CLKSRC2_CLK                                                          | CLK_STATE_READY     | 500000000       |
    |    50     |     5    | DEV_DCC7_DCC_CLKSRC5_CLK                                                          | CLK_STATE_READY     | 0               |
    |    50     |     6    | DEV_DCC7_DCC_CLKSRC6_CLK                                                          | CLK_STATE_READY     | 120000000       |
    |    50     |     7    | DEV_DCC7_DCC_CLKSRC7_CLK                                                          | CLK_STATE_READY     | 0               |
    |    50     |     8    | DEV_DCC7_DCC_INPUT00_CLK                                                          | CLK_STATE_READY     | 19200000        |
    |    50     |     9    | DEV_DCC7_DCC_INPUT01_CLK                                                          | CLK_STATE_READY     | 0               |
    |    50     |    10    | DEV_DCC7_DCC_INPUT02_CLK                                                          | CLK_STATE_READY     | 12500000        |
    |    50     |    11    | DEV_DCC7_DCC_INPUT10_CLK                                                          | CLK_STATE_READY     | 250000000       |
    |    50     |    12    | DEV_DCC7_VBUS_CLK                                                                 | CLK_STATE_READY     | 125000000       |
    |    51     |     0    | DEV_DCC8_DCC_CLKSRC0_CLK                                                          | CLK_STATE_READY     | 32000           |
    |    51     |     1    | DEV_DCC8_DCC_CLKSRC1_CLK                                                          | CLK_STATE_READY     | 32768           |
    |    51     |     2    | DEV_DCC8_DCC_CLKSRC2_CLK                                                          | CLK_STATE_READY     | 0               |
    |    51     |     3    | DEV_DCC8_DCC_CLKSRC3_CLK                                                          | CLK_STATE_NOT_READY | 0               |
    |    51     |     4    | DEV_DCC8_DCC_CLKSRC4_CLK                                                          | CLK_STATE_NOT_READY | 0               |
    |    51     |     6    | DEV_DCC8_DCC_CLKSRC6_CLK                                                          | CLK_STATE_READY     | 250000000       |
    |    51     |     7    | DEV_DCC8_DCC_CLKSRC7_CLK                                                          | CLK_STATE_READY     | 200000000       |
    |    51     |     8    | DEV_DCC8_DCC_INPUT00_CLK                                                          | CLK_STATE_READY     | 19200000        |
    |    51     |     9    | DEV_DCC8_DCC_INPUT01_CLK                                                          | CLK_STATE_READY     | 0               |
    |    51     |    10    | DEV_DCC8_DCC_INPUT02_CLK                                                          | CLK_STATE_READY     | 12500000        |
    |    51     |    11    | DEV_DCC8_DCC_INPUT10_CLK                                                          | CLK_STATE_READY     | 250000000       |
    |    51     |    12    | DEV_DCC8_VBUS_CLK                                                                 | CLK_STATE_READY     | 125000000       |
    |    52     |     0    | DEV_DCC9_DCC_CLKSRC0_CLK                                                          | CLK_STATE_READY     | 250000000       |
    |    52     |     1    | DEV_DCC9_DCC_CLKSRC1_CLK                                                          | CLK_STATE_READY     | 125000000       |
    |    52     |     2    | DEV_DCC9_DCC_CLKSRC2_CLK                                                          | CLK_STATE_READY     | 0               |
    |    52     |     3    | DEV_DCC9_DCC_CLKSRC3_CLK                                                          | CLK_STATE_READY     | 0               |
    |    52     |     4    | DEV_DCC9_DCC_CLKSRC4_CLK                                                          | CLK_STATE_READY     | 0               |
    |    52     |     5    | DEV_DCC9_DCC_CLKSRC5_CLK                                                          | CLK_STATE_READY     | 294912000       |
    |    52     |     6    | DEV_DCC9_DCC_CLKSRC6_CLK                                                          | CLK_STATE_READY     | 196608000       |
    |    52     |     8    | DEV_DCC9_DCC_INPUT00_CLK                                                          | CLK_STATE_READY     | 19200000        |
    |    52     |     9    | DEV_DCC9_DCC_INPUT01_CLK                                                          | CLK_STATE_READY     | 0               |
    |    52     |    10    | DEV_DCC9_DCC_INPUT02_CLK                                                          | CLK_STATE_READY     | 12500000        |
    |    52     |    11    | DEV_DCC9_DCC_INPUT10_CLK                                                          | CLK_STATE_READY     | 250000000       |
    |    52     |    12    | DEV_DCC9_VBUS_CLK                                                                 | CLK_STATE_READY     | 125000000       |
    |   138     |     0    | DEV_DDR0_DDRSS_DDR_PLL_CLK                                                        | CLK_STATE_READY     | 1066500000      |
    |   138     |     1    | DEV_DDR0_DDRSS_VBUS_CLK                                                           | CLK_STATE_READY     | 250000000       |
    |   138     |     2    | DEV_DDR0_PLL_CTRL_CLK                                                             | CLK_STATE_READY     | 500000000       |
    |   138     |     7    | DEV_DDR0_DDRSS_CFG_CLK                                                            | CLK_STATE_READY     | 125000000       |
    |   139     |     0    | DEV_DDR1_DDRSS_DDR_PLL_CLK                                                        | CLK_STATE_READY     | 1066500000      |
    |   139     |     1    | DEV_DDR1_DDRSS_VBUS_CLK                                                           | CLK_STATE_READY     | 250000000       |
    |   139     |     2    | DEV_DDR1_PLL_CTRL_CLK                                                             | CLK_STATE_READY     | 500000000       |
    |   139     |     7    | DEV_DDR1_DDRSS_CFG_CLK                                                            | CLK_STATE_READY     | 125000000       |
    |    57     |     1    | DEV_DEBUGSS_WRAP0_ATB_CLK                                                         | CLK_STATE_READY     | 250000000       |
    |    57     |    16    | DEV_DEBUGSS_WRAP0_CSTPIU_TRACECLK                                                 | CLK_STATE_READY     | 0               |
    |    57     |    17    | DEV_DEBUGSS_WRAP0_CORE_CLK                                                        | CLK_STATE_READY     | 125000000       |
    |    57     |    28    | DEV_DEBUGSS_WRAP0_TREXPT_CLK                                                      | CLK_STATE_READY     | 300000000       |
    |    57     |    41    | DEV_DEBUGSS_WRAP0_JTAG_TCK                                                        | CLK_STATE_READY     | 0               |
    |   137     |     0    | DEV_DEBUGSUSPENDRTR0_INTR_CLK                                                     | CLK_STATE_READY     | 125000000       |
    |    58     |     0    | DEV_DMPAC0_CLK                                                                    | CLK_STATE_READY     | 480000000       |
    |    62     |     0    | DEV_DMPAC0_SDE_0_CLK                                                              | CLK_STATE_READY     | 480000000       |
    |   374     |     0    | DEV_DMPAC0_UTC_0_PSIL_LEAF_CLK                                                    | CLK_STATE_READY     | 480000000       |
    |   140     |     0    | DEV_DMPAC_VPAC_PSILSS0_MAIN_CLK                                                   | CLK_STATE_READY     | 250000000       |
    |   152     |     0    | DEV_DPHY_RX0_IO_RX_CL_L_M                                                         | CLK_STATE_READY     | 0               |
    |   152     |     1    | DEV_DPHY_RX0_PPI_RX_BYTE_CLK                                                      | CLK_STATE_READY     | 0               |
    |   152     |     2    | DEV_DPHY_RX0_MAIN_CLK_CLK                                                         | CLK_STATE_READY     | 125000000       |
    |   152     |     3    | DEV_DPHY_RX0_IO_RX_CL_L_P                                                         | CLK_STATE_READY     | 0               |
    |   152     |     4    | DEV_DPHY_RX0_JTAG_TCK                                                             | CLK_STATE_READY     | 0               |
    |   152     |     8    | DEV_DPHY_RX0_PPI_D_RX_ULPS_ESC                                                    | CLK_STATE_READY     | 0               |
    |   153     |     0    | DEV_DPHY_RX1_IO_RX_CL_L_M                                                         | CLK_STATE_READY     | 0               |
    |   153     |     1    | DEV_DPHY_RX1_PPI_RX_BYTE_CLK                                                      | CLK_STATE_READY     | 0               |
    |   153     |     2    | DEV_DPHY_RX1_MAIN_CLK_CLK                                                         | CLK_STATE_READY     | 125000000       |
    |   153     |     3    | DEV_DPHY_RX1_IO_RX_CL_L_P                                                         | CLK_STATE_READY     | 0               |
    |   153     |     4    | DEV_DPHY_RX1_JTAG_TCK                                                             | CLK_STATE_READY     | 0               |
    |   153     |     8    | DEV_DPHY_RX1_PPI_D_RX_ULPS_ESC                                                    | CLK_STATE_READY     | 0               |
    |   363     |     1    | DEV_DPHY_TX0_IP2_PPI_TXBYTECLKHS_CL_CLK                                           | CLK_STATE_READY     | 0               |
    |   363     |     2    | DEV_DPHY_TX0_IP1_PPI_TXBYTECLKHS_CL_CLK                                           | CLK_STATE_READY     | 0               |
    |   363     |     5    | DEV_DPHY_TX0_CLK                                                                  | CLK_STATE_READY     | 125000000       |
    |   363     |     8    | DEV_DPHY_TX0_PSM_CLK                                                              | CLK_STATE_READY     | 20000000        |
    |   363     |    12    | DEV_DPHY_TX0_CK_M                                                                 | CLK_STATE_READY     | 0               |
    |   363     |    14    | DEV_DPHY_TX0_DPHY_REF_CLK                                                         | CLK_STATE_READY     | 19200000        |
    |   363     |    15    | DEV_DPHY_TX0_DPHY_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                          | CLK_STATE_READY     | 19200000        |
    |   363     |    16    | DEV_DPHY_TX0_DPHY_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                           | CLK_STATE_READY     | 0               |
    |   363     |    17    | DEV_DPHY_TX0_DPHY_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK                | CLK_STATE_READY     | 125000000       |
    |   363     |    18    | DEV_DPHY_TX0_DPHY_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK                | CLK_STATE_READY     | 100000000       |
    |   363     |    19    | DEV_DPHY_TX0_TAP_TCK                                                              | CLK_STATE_READY     | 0               |
    |   363     |    20    | DEV_DPHY_TX0_CK_P                                                                 | CLK_STATE_READY     | 0               |
    |   363     |    22    | DEV_DPHY_TX0_IP1_PPI_M_TXCLKESC_CLK                                               | CLK_STATE_READY     | 20000000        |
    |   363     |    23    | DEV_DPHY_TX0_IP1_PPI_M_RXCLKESC_CLK                                               | CLK_STATE_READY     | 0               |
    |   363     |    24    | DEV_DPHY_TX0_IP2_PPI_M_TXCLKESC_CLK                                               | CLK_STATE_READY     | 20000000        |
    |   364     |     1    | DEV_DPHY_TX1_IP2_PPI_TXBYTECLKHS_CL_CLK                                           | CLK_STATE_READY     | 0               |
    |   364     |     2    | DEV_DPHY_TX1_IP1_PPI_TXBYTECLKHS_CL_CLK                                           | CLK_STATE_READY     | 0               |
    |   364     |     5    | DEV_DPHY_TX1_CLK                                                                  | CLK_STATE_READY     | 125000000       |
    |   364     |     8    | DEV_DPHY_TX1_PSM_CLK                                                              | CLK_STATE_READY     | 20000000        |
    |   364     |    12    | DEV_DPHY_TX1_CK_M                                                                 | CLK_STATE_READY     | 0               |
    |   364     |    14    | DEV_DPHY_TX1_DPHY_REF_CLK                                                         | CLK_STATE_READY     | 19200000        |
    |   364     |    15    | DEV_DPHY_TX1_DPHY_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                          | CLK_STATE_READY     | 19200000        |
    |   364     |    16    | DEV_DPHY_TX1_DPHY_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                           | CLK_STATE_READY     | 0               |
    |   364     |    17    | DEV_DPHY_TX1_DPHY_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK                | CLK_STATE_READY     | 125000000       |
    |   364     |    18    | DEV_DPHY_TX1_DPHY_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK                | CLK_STATE_READY     | 100000000       |
    |   364     |    19    | DEV_DPHY_TX1_TAP_TCK                                                              | CLK_STATE_READY     | 0               |
    |   364     |    20    | DEV_DPHY_TX1_CK_P                                                                 | CLK_STATE_READY     | 0               |
    |   364     |    22    | DEV_DPHY_TX1_IP1_PPI_M_TXCLKESC_CLK                                               | CLK_STATE_READY     | 20000000        |
    |   364     |    23    | DEV_DPHY_TX1_IP1_PPI_M_RXCLKESC_CLK                                               | CLK_STATE_READY     | 0               |
    |   158     |     0    | DEV_DSS0_DSS_FUNC_CLK                                                             | CLK_STATE_READY     | 600000000       |
    |   158     |     1    | DEV_DSS0_DSS_INST0_DPI_0_IN_CLK                                                   | CLK_STATE_READY     | 297000000       |
    |   158     |     2    | DEV_DSS0_DSS_INST0_DPI_0_IN_2X_CLK                                                | CLK_STATE_READY     | 594000000       |
    |   158     |     3    | DEV_DSS0_DSS_INST0_DPI_0_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK      | CLK_STATE_READY     | 594000000       |
    |   158     |     4    | DEV_DSS0_DSS_INST0_DPI_0_IN_2X_CLK_PARENT_DPI_1_PCLK_SEL_OUT0                     | CLK_STATE_READY     | 600000000       |
    |   158     |     5    | DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK                                                | CLK_STATE_READY     | 600000000       |
    |   158     |     6    | DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT0_CLK      | CLK_STATE_READY     | 51200000        |
    |   158     |     7    | DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK_PARENT_DPI0_EXT_CLKSEL_OUT0                    | CLK_STATE_READY     | 600000000       |
    |   158     |     8    | DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK_PARENT_DPI0_EXT_CLKSEL_OUT0_DUP0               | CLK_STATE_READY     | 600000000       |
    |   158     |     9    | DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK      | CLK_STATE_READY     | 594000000       |
    |   158     |    10    | DEV_DSS0_DSS_INST0_DPI_2_IN_CLK                                                   | CLK_STATE_READY     | 25600000        |
    |   158     |    11    | DEV_DSS0_DSS_INST0_DPI_2_IN_CLK_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK         | CLK_STATE_READY     | 297000000       |
    |   158     |    12    | DEV_DSS0_DSS_INST0_DPI_2_IN_CLK_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT0_CLK         | CLK_STATE_READY     | 25600000        |
    |   158     |    13    | DEV_DSS0_DSS_INST0_DPI_2_IN_CLK_PARENT_DPI0_EXT_CLKSEL_OUT0                       | CLK_STATE_READY     | 300000000       |
    |   158     |    14    | DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK                                                | CLK_STATE_READY     | 51200000        |
    |   158     |    15    | DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK      | CLK_STATE_READY     | 594000000       |
    |   158     |    16    | DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT0_CLK      | CLK_STATE_READY     | 51200000        |
    |   158     |    17    | DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK_PARENT_DPI0_EXT_CLKSEL_OUT0                    | CLK_STATE_READY     | 600000000       |
    |   158     |    18    | DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK                                                | CLK_STATE_READY     | 600000000       |
    |   158     |    19    | DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT1_CLK      | CLK_STATE_READY     | 594000000       |
    |   158     |    20    | DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT1_CLK      | CLK_STATE_READY     | 276480000       |
    |   158     |    21    | DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT1_CLK_DUP0 | CLK_STATE_READY     | 276480000       |
    |   158     |    22    | DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_DPI0_EXT_CLKSEL_OUT0                    | CLK_STATE_READY     | 600000000       |
    |   158     |    23    | DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_DPI0_EXT_CLKSEL_OUT0_DUP0               | CLK_STATE_READY     | 600000000       |
    |   158     |    24    | DEV_DSS0_DSS_INST0_PARA_1_OUT_CLK                                                 | CLK_STATE_READY     | 0               |
    |   158     |    25    | DEV_DSS0_DSS_INST0_PARA_3_OUT_CLK                                                 | CLK_STATE_READY     | 0               |
    |   158     |    26    | DEV_DSS0_DSS_INST0_DPI_0_OUT_CLK                                                  | CLK_STATE_READY     | 0               |
    |   158     |    27    | DEV_DSS0_DSS_INST0_DPI_1_OUT_CLK                                                  | CLK_STATE_READY     | 0               |
    |   158     |    28    | DEV_DSS0_DSS_INST0_DPI_2_OUT_CLK                                                  | CLK_STATE_READY     | 0               |
    |   158     |    29    | DEV_DSS0_DSS_INST0_DPI_3_OUT_CLK                                                  | CLK_STATE_READY     | 0               |
    |   158     |    30    | DEV_DSS0_DSS_INST0_DPI_0_OUT_2X_CLK                                               | CLK_STATE_READY     | 0               |
    |   154     |     0    | DEV_DSS_DSI0_PLL_CTRL_CLK                                                         | CLK_STATE_READY     | 500000000       |
    |   154     |     1    | DEV_DSS_DSI0_SYS_CLK                                                              | CLK_STATE_READY     | 250000000       |
    |   154     |     2    | DEV_DSS_DSI0_DPHY_0_RX_ESC_CLK                                                    | CLK_STATE_READY     | 0               |
    |   154     |     3    | DEV_DSS_DSI0_DPHY_0_TX_ESC_CLK                                                    | CLK_STATE_READY     | 20000000        |
    |   154     |     4    | DEV_DSS_DSI0_DPI_0_CLK                                                            | CLK_STATE_READY     | 0               |
    |   154     |     5    | DEV_DSS_DSI0_PPI_0_TXBYTECLKHS_CL_CLK                                             | CLK_STATE_READY     | 0               |
    |   155     |     0    | DEV_DSS_DSI1_PLL_CTRL_CLK                                                         | CLK_STATE_READY     | 500000000       |
    |   155     |     1    | DEV_DSS_DSI1_SYS_CLK                                                              | CLK_STATE_READY     | 250000000       |
    |   155     |     2    | DEV_DSS_DSI1_DPHY_0_RX_ESC_CLK                                                    | CLK_STATE_NOT_READY | 0               |
    |   155     |     3    | DEV_DSS_DSI1_DPHY_0_TX_ESC_CLK                                                    | CLK_STATE_READY     | 20000000        |
    |   155     |     4    | DEV_DSS_DSI1_DPI_0_CLK                                                            | CLK_STATE_NOT_READY | 0               |
    |   155     |     5    | DEV_DSS_DSI1_PPI_0_TXBYTECLKHS_CL_CLK                                             | CLK_STATE_NOT_READY | 0               |
    |   156     |     0    | DEV_DSS_EDP0_PHY_LN0_RXCLK                                                        | CLK_STATE_READY     | 0               |
    |   156     |     1    | DEV_DSS_EDP0_PHY_LN2_TXCLK                                                        | CLK_STATE_READY     | 0               |
    |   156     |     2    | DEV_DSS_EDP0_PHY_LN3_RXFCLK                                                       | CLK_STATE_READY     | 0               |
    |   156     |     3    | DEV_DSS_EDP0_PHY_LN2_TXMCLK                                                       | CLK_STATE_READY     | 0               |
    |   156     |     4    | DEV_DSS_EDP0_PHY_LN3_REFCLK                                                       | CLK_STATE_READY     | 0               |
    |   156     |     6    | DEV_DSS_EDP0_DPI_2_2X_CLK                                                         | CLK_STATE_READY     | 0               |
    |   156     |     7    | DEV_DSS_EDP0_PHY_LN0_TXCLK                                                        | CLK_STATE_READY     | 0               |
    |   156     |     8    | DEV_DSS_EDP0_PHY_LN2_TXFCLK                                                       | CLK_STATE_READY     | 0               |
    |   156     |     9    | DEV_DSS_EDP0_DPI_3_CLK                                                            | CLK_STATE_READY     | 0               |
    |   156     |    10    | DEV_DSS_EDP0_PHY_LN1_RXCLK                                                        | CLK_STATE_READY     | 0               |
    |   156     |    11    | DEV_DSS_EDP0_PHY_LN1_TXCLK                                                        | CLK_STATE_READY     | 0               |
    |   156     |    12    | DEV_DSS_EDP0_PHY_LN1_RXFCLK                                                       | CLK_STATE_READY     | 0               |
    |   156     |    13    | DEV_DSS_EDP0_DPI_5_CLK                                                            | CLK_STATE_READY     | 0               |
    |   156     |    14    | DEV_DSS_EDP0_PHY_LN2_RXCLK                                                        | CLK_STATE_READY     | 0               |
    |   156     |    16    | DEV_DSS_EDP0_PHY_LN1_TXMCLK                                                       | CLK_STATE_READY     | 0               |
    |   156     |    18    | DEV_DSS_EDP0_DPI_2_CLK                                                            | CLK_STATE_READY     | 0               |
    |   156     |    19    | DEV_DSS_EDP0_DPTX_MOD_CLK                                                         | CLK_STATE_READY     | 125000000       |
    |   156     |    20    | DEV_DSS_EDP0_PHY_LN1_REFCLK                                                       | CLK_STATE_READY     | 0               |
    |   156     |    21    | DEV_DSS_EDP0_PHY_LN1_TXFCLK                                                       | CLK_STATE_READY     | 0               |
    |   156     |    22    | DEV_DSS_EDP0_PHY_LN0_RXFCLK                                                       | CLK_STATE_READY     | 0               |
    |   156     |    24    | DEV_DSS_EDP0_PHY_LN3_TXMCLK                                                       | CLK_STATE_READY     | 0               |
    |   156     |    25    | DEV_DSS_EDP0_PLL_CTRL_CLK                                                         | CLK_STATE_READY     | 500000000       |
    |   156     |    26    | DEV_DSS_EDP0_PHY_LN0_TXFCLK                                                       | CLK_STATE_READY     | 0               |
    |   156     |    27    | DEV_DSS_EDP0_PHY_LN3_TXFCLK                                                       | CLK_STATE_READY     | 0               |
    |   156     |    28    | DEV_DSS_EDP0_PHY_LN3_TXCLK                                                        | CLK_STATE_READY     | 0               |
    |   156     |    29    | DEV_DSS_EDP0_PHY_LN2_REFCLK                                                       | CLK_STATE_READY     | 0               |
    |   156     |    30    | DEV_DSS_EDP0_DPI_4_CLK                                                            | CLK_STATE_READY     | 0               |
    |   156     |    31    | DEV_DSS_EDP0_PHY_LN0_TXMCLK                                                       | CLK_STATE_READY     | 0               |
    |   156     |    33    | DEV_DSS_EDP0_PHY_LN0_REFCLK                                                       | CLK_STATE_READY     | 0               |
    |   156     |    34    | DEV_DSS_EDP0_PHY_LN3_RXCLK                                                        | CLK_STATE_READY     | 0               |
    |   156     |    35    | DEV_DSS_EDP0_AIF_I2S_CLK                                                          | CLK_STATE_READY     | 0               |
    |   156     |    36    | DEV_DSS_EDP0_PHY_LN2_RXFCLK                                                       | CLK_STATE_READY     | 0               |
    |    92     |     0    | DEV_ECAP0_VBUS_CLK                                                                | CLK_STATE_READY     | 125000000       |
    |    93     |     0    | DEV_ECAP1_VBUS_CLK                                                                | CLK_STATE_READY     | 125000000       |
    |    94     |     0    | DEV_ECAP2_VBUS_CLK                                                                | CLK_STATE_READY     | 125000000       |
    |    95     |     0    | DEV_ELM0_VBUSP_CLK                                                                | CLK_STATE_READY     | 125000000       |
    |   160     |     0    | DEV_EPWM0_VBUSP_CLK                                                               | CLK_STATE_READY     | 125000000       |
    |   161     |     0    | DEV_EPWM1_VBUSP_CLK                                                               | CLK_STATE_READY     | 125000000       |
    |   162     |     0    | DEV_EPWM2_VBUSP_CLK                                                               | CLK_STATE_READY     | 125000000       |
    |   163     |     0    | DEV_EPWM3_VBUSP_CLK                                                               | CLK_STATE_READY     | 125000000       |
    |   164     |     0    | DEV_EPWM4_VBUSP_CLK                                                               | CLK_STATE_READY     | 125000000       |
    |   165     |     0    | DEV_EPWM5_VBUSP_CLK                                                               | CLK_STATE_READY     | 125000000       |
    |   100     |     0    | DEV_EQEP0_VBUS_CLK                                                                | CLK_STATE_READY     | 125000000       |
    |   101     |     0    | DEV_EQEP1_VBUS_CLK                                                                | CLK_STATE_READY     | 125000000       |
    |   102     |     0    | DEV_EQEP2_VBUS_CLK                                                                | CLK_STATE_READY     | 125000000       |
    |   103     |     0    | DEV_ESM0_CLK                                                                      | CLK_STATE_READY     | 125000000       |
    |   111     |     0    | DEV_GPIO0_MMR_CLK                                                                 | CLK_STATE_READY     | 125000000       |
    |   112     |     0    | DEV_GPIO2_MMR_CLK                                                                 | CLK_STATE_READY     | 125000000       |
    |   113     |     0    | DEV_GPIO4_MMR_CLK                                                                 | CLK_STATE_READY     | 125000000       |
    |   114     |     0    | DEV_GPIO6_MMR_CLK                                                                 | CLK_STATE_READY     | 125000000       |
    |   148     |     0    | DEV_GPIOMUX_INTRTR0_INTR_CLK                                                      | CLK_STATE_READY     | 125000000       |
    |   117     |     0    | DEV_GPMC0_VBUSM_CLK                                                               | CLK_STATE_READY     | 250000000       |
    |   117     |     1    | DEV_GPMC0_PO_GPMC_DEV_CLK                                                         | CLK_STATE_READY     | 0               |
    |   117     |     2    | DEV_GPMC0_FUNC_CLK                                                                | CLK_STATE_READY     | 133333333       |
    |   117     |     3    | DEV_GPMC0_FUNC_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT3_CLK                       | CLK_STATE_READY     | 133333333       |
    |   117     |     4    | DEV_GPMC0_FUNC_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK6                      | CLK_STATE_READY     | 100000000       |
    |   117     |     5    | DEV_GPMC0_FUNC_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK4                      | CLK_STATE_READY     | 150000000       |
    |   117     |     6    | DEV_GPMC0_FUNC_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK4              | CLK_STATE_READY     | 125000000       |
    |   117     |     7    | DEV_GPMC0_PI_GPMC_RET_CLK                                                         | CLK_STATE_READY     | 0               |
    |    61     |     0    | DEV_GTC0_VBUSP_CLK                                                                | CLK_STATE_READY     | 125000000       |
    |    61     |     1    | DEV_GTC0_GTC_CLK                                                                  | CLK_STATE_READY     | 200000000       |
    |    61     |     2    | DEV_GTC0_GTC_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK                         | CLK_STATE_READY     | 250000000       |
    |    61     |     3    | DEV_GTC0_GTC_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK                       | CLK_STATE_READY     | 200000000       |
    |    61     |     4    | DEV_GTC0_GTC_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT                             | CLK_STATE_READY     | 0               |
    |    61     |     5    | DEV_GTC0_GTC_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT                                 | CLK_STATE_READY     | 0               |
    |    61     |     6    | DEV_GTC0_GTC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                               | CLK_STATE_READY     | 0               |
    |    61     |     7    | DEV_GTC0_GTC_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT                                   | CLK_STATE_READY     | 0               |
    |    61     |     8    | DEV_GTC0_GTC_CLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN0_TXMCLK                        | CLK_STATE_READY     | 0               |
    |    61     |     9    | DEV_GTC0_GTC_CLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN1_TXMCLK                        | CLK_STATE_READY     | 0               |
    |    61     |    10    | DEV_GTC0_GTC_CLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN2_TXMCLK                        | CLK_STATE_READY     | 0               |
    |    61     |    11    | DEV_GTC0_GTC_CLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN3_TXMCLK                        | CLK_STATE_READY     | 0               |
    |    61     |    16    | DEV_GTC0_GTC_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK                          | CLK_STATE_READY     | 500000000       |
    |    61     |    17    | DEV_GTC0_GTC_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK                 | CLK_STATE_READY     | 500000000       |
    |   214     |     0    | DEV_I2C0_PORSCL                                                                   | CLK_STATE_READY     | 0               |
    |   214     |     1    | DEV_I2C0_PISYS_CLK                                                                | CLK_STATE_READY     | 96000000        |
    |   214     |     2    | DEV_I2C0_CLK                                                                      | CLK_STATE_READY     | 125000000       |
    |   214     |     3    | DEV_I2C0_PISCL                                                                    | CLK_STATE_READY     | 0               |
    |   215     |     0    | DEV_I2C1_PORSCL                                                                   | CLK_STATE_READY     | 0               |
    |   215     |     1    | DEV_I2C1_PISYS_CLK                                                                | CLK_STATE_READY     | 96000000        |
    |   215     |     2    | DEV_I2C1_CLK                                                                      | CLK_STATE_READY     | 125000000       |
    |   215     |     3    | DEV_I2C1_PISCL                                                                    | CLK_STATE_READY     | 0               |
    |   216     |     0    | DEV_I2C2_PORSCL                                                                   | CLK_STATE_READY     | 0               |
    |   216     |     1    | DEV_I2C2_PISYS_CLK                                                                | CLK_STATE_READY     | 96000000        |
    |   216     |     2    | DEV_I2C2_CLK                                                                      | CLK_STATE_READY     | 125000000       |
    |   216     |     3    | DEV_I2C2_PISCL                                                                    | CLK_STATE_READY     | 0               |
    |   217     |     0    | DEV_I2C3_PORSCL                                                                   | CLK_STATE_READY     | 0               |
    |   217     |     1    | DEV_I2C3_PISYS_CLK                                                                | CLK_STATE_READY     | 96000000        |
    |   217     |     2    | DEV_I2C3_CLK                                                                      | CLK_STATE_READY     | 125000000       |
    |   217     |     3    | DEV_I2C3_PISCL                                                                    | CLK_STATE_READY     | 0               |
    |   218     |     0    | DEV_I2C4_PORSCL                                                                   | CLK_STATE_READY     | 0               |
    |   218     |     1    | DEV_I2C4_PISYS_CLK                                                                | CLK_STATE_READY     | 96000000        |
    |   218     |     2    | DEV_I2C4_CLK                                                                      | CLK_STATE_READY     | 125000000       |
    |   218     |     3    | DEV_I2C4_PISCL                                                                    | CLK_STATE_READY     | 0               |
    |   219     |     0    | DEV_I2C5_PORSCL                                                                   | CLK_STATE_READY     | 0               |
    |   219     |     1    | DEV_I2C5_PISYS_CLK                                                                | CLK_STATE_READY     | 96000000        |
    |   219     |     2    | DEV_I2C5_CLK                                                                      | CLK_STATE_READY     | 125000000       |
    |   219     |     3    | DEV_I2C5_PISCL                                                                    | CLK_STATE_READY     | 0               |
    |   220     |     0    | DEV_I2C6_PORSCL                                                                   | CLK_STATE_READY     | 0               |
    |   220     |     1    | DEV_I2C6_PISYS_CLK                                                                | CLK_STATE_READY     | 96000000        |
    |   220     |     2    | DEV_I2C6_CLK                                                                      | CLK_STATE_READY     | 125000000       |
    |   220     |     3    | DEV_I2C6_PISCL                                                                    | CLK_STATE_READY     | 0               |
    |   130     |     0    | DEV_J7AEP_GPU_BXS464_WRAP0_GPU_SS_0_PLL_CTRL_CLK                                  | CLK_STATE_READY     | 500000000       |
    |   130     |     1    | DEV_J7AEP_GPU_BXS464_WRAP0_GPU_SS_0_GPU_PLL_CLK                                   | CLK_STATE_READY     | 800000000       |
    |   131     |     0    | DEV_J7AM_32_64_ATB_FUNNEL0_DBG_CLK                                                | CLK_STATE_READY     | 250000000       |
    |   132     |     0    | DEV_J7AM_32_64_ATB_FUNNEL1_DBG_CLK                                                | CLK_STATE_READY     | 250000000       |
    |   133     |     0    | DEV_J7AM_32_64_ATB_FUNNEL2_DBG_CLK                                                | CLK_STATE_READY     | 250000000       |
    |   135     |     0    | DEV_J7AM_BOLT_PGD0_WKUP_OSC0_CLK                                                  | CLK_STATE_READY     | 19200000        |
    |   141     |     0    | DEV_J7AM_HWA_ATB_FUNNEL0_DBG_CLK                                                  | CLK_STATE_READY     | 250000000       |
    |   142     |     0    | DEV_J7AM_MAIN_16FF0_WKUP_OSC0_CLK                                                 | CLK_STATE_READY     | 19200000        |
    |   144     |     0    | DEV_J7AM_PULSAR_ATB_FUNNEL0_DBG_CLK                                               | CLK_STATE_READY     | 250000000       |
    |   120     |     0    | DEV_LED0_VBUS_CLK                                                                 | CLK_STATE_READY     | 250000000       |
    |   120     |     1    | DEV_LED0_LED_CLK                                                                  | CLK_STATE_READY     | 0               |
    |   121     |     0    | DEV_MAIN2MCU_LVL_INTRTR0_INTR_CLK                                                 | CLK_STATE_READY     | 125000000       |
    |   122     |     0    | DEV_MAIN2MCU_PLS_INTRTR0_INTR_CLK                                                 | CLK_STATE_READY     | 125000000       |
    |   182     |     0    | DEV_MCAN0_MCANSS_HCLK_CLK                                                         | CLK_STATE_READY     | 125000000       |
    |   182     |     1    | DEV_MCAN0_MCANSS_CCLK_CLK                                                         | CLK_STATE_READY     | 80000000        |
    |   182     |     2    | DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK                | CLK_STATE_READY     | 80000000        |
    |   182     |     3    | DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                      | CLK_STATE_READY     | 0               |
    |   182     |     4    | DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                           | CLK_STATE_READY     | 0               |
    |   182     |     5    | DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                          | CLK_STATE_READY     | 19200000        |
    |   182     |     6    | DEV_MCAN0_MCANSS_CAN_RXD                                                          | CLK_STATE_READY     | 0               |
    |   183     |     0    | DEV_MCAN1_MCANSS_HCLK_CLK                                                         | CLK_STATE_READY     | 125000000       |
    |   183     |     1    | DEV_MCAN1_MCANSS_CCLK_CLK                                                         | CLK_STATE_READY     | 80000000        |
    |   183     |     2    | DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK                | CLK_STATE_READY     | 80000000        |
    |   183     |     3    | DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                      | CLK_STATE_READY     | 0               |
    |   183     |     4    | DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                           | CLK_STATE_READY     | 0               |
    |   183     |     5    | DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                          | CLK_STATE_READY     | 19200000        |
    |   183     |     6    | DEV_MCAN1_MCANSS_CAN_RXD                                                          | CLK_STATE_READY     | 0               |
    |   192     |     0    | DEV_MCAN10_MCANSS_HCLK_CLK                                                        | CLK_STATE_READY     | 125000000       |
    |   192     |     1    | DEV_MCAN10_MCANSS_CCLK_CLK                                                        | CLK_STATE_READY     | 80000000        |
    |   192     |     2    | DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK               | CLK_STATE_READY     | 80000000        |
    |   192     |     3    | DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                     | CLK_STATE_READY     | 0               |
    |   192     |     4    | DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                          | CLK_STATE_READY     | 0               |
    |   192     |     5    | DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                         | CLK_STATE_READY     | 19200000        |
    |   192     |     6    | DEV_MCAN10_MCANSS_CAN_RXD                                                         | CLK_STATE_READY     | 0               |
    |   193     |     0    | DEV_MCAN11_MCANSS_HCLK_CLK                                                        | CLK_STATE_READY     | 125000000       |
    |   193     |     1    | DEV_MCAN11_MCANSS_CCLK_CLK                                                        | CLK_STATE_READY     | 80000000        |
    |   193     |     2    | DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK               | CLK_STATE_READY     | 80000000        |
    |   193     |     3    | DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                     | CLK_STATE_READY     | 0               |
    |   193     |     4    | DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                          | CLK_STATE_READY     | 0               |
    |   193     |     5    | DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                         | CLK_STATE_READY     | 19200000        |
    |   193     |     6    | DEV_MCAN11_MCANSS_CAN_RXD                                                         | CLK_STATE_READY     | 0               |
    |   194     |     0    | DEV_MCAN12_MCANSS_HCLK_CLK                                                        | CLK_STATE_READY     | 125000000       |
    |   194     |     1    | DEV_MCAN12_MCANSS_CCLK_CLK                                                        | CLK_STATE_READY     | 80000000        |
    |   194     |     2    | DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK               | CLK_STATE_READY     | 80000000        |
    |   194     |     3    | DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                     | CLK_STATE_READY     | 0               |
    |   194     |     4    | DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                          | CLK_STATE_READY     | 0               |
    |   194     |     5    | DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                         | CLK_STATE_READY     | 19200000        |
    |   194     |     6    | DEV_MCAN12_MCANSS_CAN_RXD                                                         | CLK_STATE_READY     | 0               |
    |   195     |     0    | DEV_MCAN13_MCANSS_HCLK_CLK                                                        | CLK_STATE_READY     | 125000000       |
    |   195     |     1    | DEV_MCAN13_MCANSS_CCLK_CLK                                                        | CLK_STATE_READY     | 80000000        |
    |   195     |     2    | DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK               | CLK_STATE_READY     | 80000000        |
    |   195     |     3    | DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                     | CLK_STATE_READY     | 0               |
    |   195     |     4    | DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                          | CLK_STATE_READY     | 0               |
    |   195     |     5    | DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                         | CLK_STATE_READY     | 19200000        |
    |   195     |     6    | DEV_MCAN13_MCANSS_CAN_RXD                                                         | CLK_STATE_READY     | 0               |
    |   197     |     0    | DEV_MCAN14_MCANSS_HCLK_CLK                                                        | CLK_STATE_READY     | 125000000       |
    |   197     |     1    | DEV_MCAN14_MCANSS_CCLK_CLK                                                        | CLK_STATE_READY     | 80000000        |
    |   197     |     2    | DEV_MCAN14_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK               | CLK_STATE_READY     | 80000000        |
    |   197     |     3    | DEV_MCAN14_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                     | CLK_STATE_READY     | 0               |
    |   197     |     4    | DEV_MCAN14_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                          | CLK_STATE_READY     | 0               |
    |   197     |     5    | DEV_MCAN14_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                         | CLK_STATE_READY     | 19200000        |
    |   197     |     6    | DEV_MCAN14_MCANSS_CAN_RXD                                                         | CLK_STATE_READY     | 0               |
    |   199     |     0    | DEV_MCAN15_MCANSS_HCLK_CLK                                                        | CLK_STATE_READY     | 125000000       |
    |   199     |     1    | DEV_MCAN15_MCANSS_CCLK_CLK                                                        | CLK_STATE_READY     | 80000000        |
    |   199     |     2    | DEV_MCAN15_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK               | CLK_STATE_READY     | 80000000        |
    |   199     |     3    | DEV_MCAN15_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                     | CLK_STATE_READY     | 0               |
    |   199     |     4    | DEV_MCAN15_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                          | CLK_STATE_READY     | 0               |
    |   199     |     5    | DEV_MCAN15_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                         | CLK_STATE_READY     | 19200000        |
    |   199     |     6    | DEV_MCAN15_MCANSS_CAN_RXD                                                         | CLK_STATE_READY     | 0               |
    |   201     |     0    | DEV_MCAN16_MCANSS_HCLK_CLK                                                        | CLK_STATE_READY     | 125000000       |
    |   201     |     1    | DEV_MCAN16_MCANSS_CCLK_CLK                                                        | CLK_STATE_READY     | 80000000        |
    |   201     |     2    | DEV_MCAN16_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK               | CLK_STATE_READY     | 80000000        |
    |   201     |     3    | DEV_MCAN16_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                     | CLK_STATE_READY     | 0               |
    |   201     |     4    | DEV_MCAN16_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                          | CLK_STATE_READY     | 0               |
    |   201     |     5    | DEV_MCAN16_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                         | CLK_STATE_READY     | 19200000        |
    |   201     |     6    | DEV_MCAN16_MCANSS_CAN_RXD                                                         | CLK_STATE_READY     | 0               |
    |   206     |     0    | DEV_MCAN17_MCANSS_HCLK_CLK                                                        | CLK_STATE_READY     | 125000000       |
    |   206     |     1    | DEV_MCAN17_MCANSS_CCLK_CLK                                                        | CLK_STATE_READY     | 80000000        |
    |   206     |     2    | DEV_MCAN17_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK               | CLK_STATE_READY     | 80000000        |
    |   206     |     3    | DEV_MCAN17_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                     | CLK_STATE_READY     | 0               |
    |   206     |     4    | DEV_MCAN17_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                          | CLK_STATE_READY     | 0               |
    |   206     |     5    | DEV_MCAN17_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                         | CLK_STATE_READY     | 19200000        |
    |   206     |     6    | DEV_MCAN17_MCANSS_CAN_RXD                                                         | CLK_STATE_READY     | 0               |
    |   184     |     0    | DEV_MCAN2_MCANSS_HCLK_CLK                                                         | CLK_STATE_READY     | 125000000       |
    |   184     |     1    | DEV_MCAN2_MCANSS_CCLK_CLK                                                         | CLK_STATE_READY     | 80000000        |
    |   184     |     2    | DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK                | CLK_STATE_READY     | 80000000        |
    |   184     |     3    | DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                      | CLK_STATE_READY     | 0               |
    |   184     |     4    | DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                           | CLK_STATE_READY     | 0               |
    |   184     |     5    | DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                          | CLK_STATE_READY     | 19200000        |
    |   184     |     6    | DEV_MCAN2_MCANSS_CAN_RXD                                                          | CLK_STATE_READY     | 0               |
    |   185     |     0    | DEV_MCAN3_MCANSS_HCLK_CLK                                                         | CLK_STATE_READY     | 125000000       |
    |   185     |     1    | DEV_MCAN3_MCANSS_CCLK_CLK                                                         | CLK_STATE_READY     | 80000000        |
    |   185     |     2    | DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK                | CLK_STATE_READY     | 80000000        |
    |   185     |     3    | DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                      | CLK_STATE_READY     | 0               |
    |   185     |     4    | DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                           | CLK_STATE_READY     | 0               |
    |   185     |     5    | DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                          | CLK_STATE_READY     | 19200000        |
    |   185     |     6    | DEV_MCAN3_MCANSS_CAN_RXD                                                          | CLK_STATE_READY     | 0               |
    |   186     |     0    | DEV_MCAN4_MCANSS_HCLK_CLK                                                         | CLK_STATE_READY     | 125000000       |
    |   186     |     1    | DEV_MCAN4_MCANSS_CCLK_CLK                                                         | CLK_STATE_READY     | 80000000        |
    |   186     |     2    | DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK                | CLK_STATE_READY     | 80000000        |
    |   186     |     3    | DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                      | CLK_STATE_READY     | 0               |
    |   186     |     4    | DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                           | CLK_STATE_READY     | 0               |
    |   186     |     5    | DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                          | CLK_STATE_READY     | 19200000        |
    |   186     |     6    | DEV_MCAN4_MCANSS_CAN_RXD                                                          | CLK_STATE_READY     | 0               |
    |   187     |     0    | DEV_MCAN5_MCANSS_HCLK_CLK                                                         | CLK_STATE_READY     | 125000000       |
    |   187     |     1    | DEV_MCAN5_MCANSS_CCLK_CLK                                                         | CLK_STATE_READY     | 80000000        |
    |   187     |     2    | DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK                | CLK_STATE_READY     | 80000000        |
    |   187     |     3    | DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                      | CLK_STATE_READY     | 0               |
    |   187     |     4    | DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                           | CLK_STATE_READY     | 0               |
    |   187     |     5    | DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                          | CLK_STATE_READY     | 19200000        |
    |   187     |     6    | DEV_MCAN5_MCANSS_CAN_RXD                                                          | CLK_STATE_READY     | 0               |
    |   188     |     0    | DEV_MCAN6_MCANSS_HCLK_CLK                                                         | CLK_STATE_READY     | 125000000       |
    |   188     |     1    | DEV_MCAN6_MCANSS_CCLK_CLK                                                         | CLK_STATE_READY     | 80000000        |
    |   188     |     2    | DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK                | CLK_STATE_READY     | 80000000        |
    |   188     |     3    | DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                      | CLK_STATE_READY     | 0               |
    |   188     |     4    | DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                           | CLK_STATE_READY     | 0               |
    |   188     |     5    | DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                          | CLK_STATE_READY     | 19200000        |
    |   188     |     6    | DEV_MCAN6_MCANSS_CAN_RXD                                                          | CLK_STATE_READY     | 0               |
    |   189     |     0    | DEV_MCAN7_MCANSS_HCLK_CLK                                                         | CLK_STATE_READY     | 125000000       |
    |   189     |     1    | DEV_MCAN7_MCANSS_CCLK_CLK                                                         | CLK_STATE_READY     | 80000000        |
    |   189     |     2    | DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK                | CLK_STATE_READY     | 80000000        |
    |   189     |     3    | DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                      | CLK_STATE_READY     | 0               |
    |   189     |     4    | DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                           | CLK_STATE_READY     | 0               |
    |   189     |     5    | DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                          | CLK_STATE_READY     | 19200000        |
    |   189     |     6    | DEV_MCAN7_MCANSS_CAN_RXD                                                          | CLK_STATE_READY     | 0               |
    |   190     |     0    | DEV_MCAN8_MCANSS_HCLK_CLK                                                         | CLK_STATE_READY     | 125000000       |
    |   190     |     1    | DEV_MCAN8_MCANSS_CCLK_CLK                                                         | CLK_STATE_READY     | 80000000        |
    |   190     |     2    | DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK                | CLK_STATE_READY     | 80000000        |
    |   190     |     3    | DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                      | CLK_STATE_READY     | 0               |
    |   190     |     4    | DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                           | CLK_STATE_READY     | 0               |
    |   190     |     5    | DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                          | CLK_STATE_READY     | 19200000        |
    |   190     |     6    | DEV_MCAN8_MCANSS_CAN_RXD                                                          | CLK_STATE_READY     | 0               |
    |   191     |     0    | DEV_MCAN9_MCANSS_HCLK_CLK                                                         | CLK_STATE_READY     | 125000000       |
    |   191     |     1    | DEV_MCAN9_MCANSS_CCLK_CLK                                                         | CLK_STATE_READY     | 80000000        |
    |   191     |     2    | DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK                | CLK_STATE_READY     | 80000000        |
    |   191     |     3    | DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                      | CLK_STATE_READY     | 0               |
    |   191     |     4    | DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                           | CLK_STATE_READY     | 0               |
    |   191     |     5    | DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                          | CLK_STATE_READY     | 19200000        |
    |   191     |     6    | DEV_MCAN9_MCANSS_CAN_RXD                                                          | CLK_STATE_READY     | 0               |
    |   209     |     0    | DEV_MCASP0_AUX_CLK                                                                | CLK_STATE_READY     | 196608000       |
    |   209     |     1    | DEV_MCASP0_AUX_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT0_CLK                       | CLK_STATE_READY     | 196608000       |
    |   209     |     2    | DEV_MCASP0_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK                       | CLK_STATE_READY     | 200000000       |
    |   209     |     5    | DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT                        | CLK_STATE_NOT_READY | 0               |
    |   209     |     6    | DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1                      | CLK_STATE_NOT_READY | 0               |
    |   209     |     7    | DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2                      | CLK_STATE_NOT_READY | 0               |
    |   209     |     8    | DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3                      | CLK_STATE_NOT_READY | 0               |
    |   209     |     9    | DEV_MCASP0_MCASP_AFSX_POUT                                                        | CLK_STATE_READY     | 0               |
    |   209     |    10    | DEV_MCASP0_MCASP_AHCLKR_POUT                                                      | CLK_STATE_READY     | 0               |
    |   209     |    11    | DEV_MCASP0_MCASP_AHCLKR_PIN                                                       | CLK_STATE_READY     | 0               |
    |   209     |    12    | DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT                         | CLK_STATE_READY     | 0               |
    |   209     |    13    | DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT                        | CLK_STATE_READY     | 19200000        |
    |   209     |    14    | DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT                  | CLK_STATE_READY     | 0               |
    |   209     |    15    | DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT                  | CLK_STATE_READY     | 0               |
    |   209     |    20    | DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT               | CLK_STATE_NOT_READY | 0               |
    |   209     |    21    | DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1             | CLK_STATE_NOT_READY | 0               |
    |   209     |    22    | DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2             | CLK_STATE_NOT_READY | 0               |
    |   209     |    23    | DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3             | CLK_STATE_NOT_READY | 0               |
    |   209     |    28    | DEV_MCASP0_MCASP_ACLKX_POUT                                                       | CLK_STATE_READY     | 0               |
    |   209     |    29    | DEV_MCASP0_MCASP_AFSR_POUT                                                        | CLK_STATE_READY     | 0               |
    |   209     |    30    | DEV_MCASP0_VBUSP_CLK                                                              | CLK_STATE_READY     | 250000000       |
    |   209     |    31    | DEV_MCASP0_MCASP_ACLKR_POUT                                                       | CLK_STATE_READY     | 0               |
    |   209     |    32    | DEV_MCASP0_MCASP_AHCLKX_POUT                                                      | CLK_STATE_READY     | 0               |
    |   209     |    33    | DEV_MCASP0_MCASP_ACLKX_PIN                                                        | CLK_STATE_READY     | 0               |
    |   209     |    34    | DEV_MCASP0_MCASP_AHCLKX_PIN                                                       | CLK_STATE_READY     | 0               |
    |   209     |    35    | DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT                         | CLK_STATE_READY     | 0               |
    |   209     |    36    | DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT                        | CLK_STATE_READY     | 19200000        |
    |   209     |    37    | DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT                  | CLK_STATE_READY     | 0               |
    |   209     |    38    | DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT                  | CLK_STATE_READY     | 0               |
    |   209     |    43    | DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT               | CLK_STATE_NOT_READY | 0               |
    |   209     |    44    | DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1             | CLK_STATE_NOT_READY | 0               |
    |   209     |    45    | DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2             | CLK_STATE_NOT_READY | 0               |
    |   209     |    46    | DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3             | CLK_STATE_NOT_READY | 0               |
    |   209     |    51    | DEV_MCASP0_MCASP_ACLKR_PIN                                                        | CLK_STATE_READY     | 0               |
    |   210     |     0    | DEV_MCASP1_AUX_CLK                                                                | CLK_STATE_READY     | 196608000       |
    |   210     |     1    | DEV_MCASP1_AUX_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT0_CLK                       | CLK_STATE_READY     | 196608000       |
    |   210     |     2    | DEV_MCASP1_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK                       | CLK_STATE_READY     | 200000000       |
    |   210     |     5    | DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT                        | CLK_STATE_NOT_READY | 0               |
    |   210     |     6    | DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1                      | CLK_STATE_NOT_READY | 0               |
    |   210     |     7    | DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2                      | CLK_STATE_NOT_READY | 0               |
    |   210     |     8    | DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3                      | CLK_STATE_NOT_READY | 0               |
    |   210     |     9    | DEV_MCASP1_MCASP_AFSX_POUT                                                        | CLK_STATE_READY     | 0               |
    |   210     |    10    | DEV_MCASP1_MCASP_AHCLKR_POUT                                                      | CLK_STATE_READY     | 0               |
    |   210     |    11    | DEV_MCASP1_MCASP_AHCLKR_PIN                                                       | CLK_STATE_READY     | 0               |
    |   210     |    12    | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT                         | CLK_STATE_READY     | 0               |
    |   210     |    13    | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT                        | CLK_STATE_READY     | 19200000        |
    |   210     |    14    | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT                  | CLK_STATE_READY     | 0               |
    |   210     |    15    | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT                  | CLK_STATE_READY     | 0               |
    |   210     |    20    | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT               | CLK_STATE_NOT_READY | 0               |
    |   210     |    21    | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1             | CLK_STATE_NOT_READY | 0               |
    |   210     |    22    | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2             | CLK_STATE_NOT_READY | 0               |
    |   210     |    23    | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3             | CLK_STATE_NOT_READY | 0               |
    |   210     |    28    | DEV_MCASP1_MCASP_ACLKX_POUT                                                       | CLK_STATE_READY     | 0               |
    |   210     |    29    | DEV_MCASP1_MCASP_AFSR_POUT                                                        | CLK_STATE_READY     | 0               |
    |   210     |    30    | DEV_MCASP1_VBUSP_CLK                                                              | CLK_STATE_READY     | 250000000       |
    |   210     |    31    | DEV_MCASP1_MCASP_ACLKR_POUT                                                       | CLK_STATE_READY     | 0               |
    |   210     |    32    | DEV_MCASP1_MCASP_AHCLKX_POUT                                                      | CLK_STATE_READY     | 0               |
    |   210     |    33    | DEV_MCASP1_MCASP_ACLKX_PIN                                                        | CLK_STATE_READY     | 0               |
    |   210     |    34    | DEV_MCASP1_MCASP_AHCLKX_PIN                                                       | CLK_STATE_READY     | 0               |
    |   210     |    35    | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT                         | CLK_STATE_READY     | 0               |
    |   210     |    36    | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT                        | CLK_STATE_READY     | 19200000        |
    |   210     |    37    | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT                  | CLK_STATE_READY     | 0               |
    |   210     |    38    | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT                  | CLK_STATE_READY     | 0               |
    |   210     |    43    | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT               | CLK_STATE_NOT_READY | 0               |
    |   210     |    44    | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1             | CLK_STATE_NOT_READY | 0               |
    |   210     |    45    | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2             | CLK_STATE_NOT_READY | 0               |
    |   210     |    46    | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3             | CLK_STATE_NOT_READY | 0               |
    |   210     |    51    | DEV_MCASP1_MCASP_ACLKR_PIN                                                        | CLK_STATE_READY     | 0               |
    |   211     |     0    | DEV_MCASP2_AUX_CLK                                                                | CLK_STATE_READY     | 196608000       |
    |   211     |     1    | DEV_MCASP2_AUX_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT0_CLK                       | CLK_STATE_READY     | 196608000       |
    |   211     |     2    | DEV_MCASP2_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK                       | CLK_STATE_READY     | 200000000       |
    |   211     |     5    | DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT                        | CLK_STATE_NOT_READY | 0               |
    |   211     |     6    | DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1                      | CLK_STATE_NOT_READY | 0               |
    |   211     |     7    | DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2                      | CLK_STATE_NOT_READY | 0               |
    |   211     |     8    | DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3                      | CLK_STATE_NOT_READY | 0               |
    |   211     |     9    | DEV_MCASP2_MCASP_AFSX_POUT                                                        | CLK_STATE_READY     | 0               |
    |   211     |    10    | DEV_MCASP2_MCASP_AHCLKR_POUT                                                      | CLK_STATE_READY     | 0               |
    |   211     |    11    | DEV_MCASP2_MCASP_AHCLKR_PIN                                                       | CLK_STATE_READY     | 0               |
    |   211     |    12    | DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT                         | CLK_STATE_READY     | 0               |
    |   211     |    13    | DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT                        | CLK_STATE_READY     | 19200000        |
    |   211     |    14    | DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT                  | CLK_STATE_READY     | 0               |
    |   211     |    15    | DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT                  | CLK_STATE_READY     | 0               |
    |   211     |    20    | DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT               | CLK_STATE_NOT_READY | 0               |
    |   211     |    21    | DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1             | CLK_STATE_NOT_READY | 0               |
    |   211     |    22    | DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2             | CLK_STATE_NOT_READY | 0               |
    |   211     |    23    | DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3             | CLK_STATE_NOT_READY | 0               |
    |   211     |    28    | DEV_MCASP2_MCASP_ACLKX_POUT                                                       | CLK_STATE_READY     | 0               |
    |   211     |    29    | DEV_MCASP2_MCASP_AFSR_POUT                                                        | CLK_STATE_READY     | 0               |
    |   211     |    30    | DEV_MCASP2_VBUSP_CLK                                                              | CLK_STATE_READY     | 250000000       |
    |   211     |    31    | DEV_MCASP2_MCASP_ACLKR_POUT                                                       | CLK_STATE_READY     | 0               |
    |   211     |    32    | DEV_MCASP2_MCASP_AHCLKX_POUT                                                      | CLK_STATE_READY     | 0               |
    |   211     |    33    | DEV_MCASP2_MCASP_ACLKX_PIN                                                        | CLK_STATE_READY     | 0               |
    |   211     |    34    | DEV_MCASP2_MCASP_AHCLKX_PIN                                                       | CLK_STATE_READY     | 0               |
    |   211     |    35    | DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT                         | CLK_STATE_READY     | 0               |
    |   211     |    36    | DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT                        | CLK_STATE_READY     | 19200000        |
    |   211     |    37    | DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT                  | CLK_STATE_READY     | 0               |
    |   211     |    38    | DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT                  | CLK_STATE_READY     | 0               |
    |   211     |    43    | DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT               | CLK_STATE_NOT_READY | 0               |
    |   211     |    44    | DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1             | CLK_STATE_NOT_READY | 0               |
    |   211     |    45    | DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2             | CLK_STATE_NOT_READY | 0               |
    |   211     |    46    | DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3             | CLK_STATE_NOT_READY | 0               |
    |   211     |    51    | DEV_MCASP2_MCASP_ACLKR_PIN                                                        | CLK_STATE_READY     | 0               |
    |   212     |     0    | DEV_MCASP3_AUX_CLK                                                                | CLK_STATE_READY     | 196608000       |
    |   212     |     1    | DEV_MCASP3_AUX_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT0_CLK                       | CLK_STATE_READY     | 196608000       |
    |   212     |     2    | DEV_MCASP3_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK                       | CLK_STATE_READY     | 200000000       |
    |   212     |     5    | DEV_MCASP3_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT                        | CLK_STATE_NOT_READY | 0               |
    |   212     |     6    | DEV_MCASP3_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1                      | CLK_STATE_NOT_READY | 0               |
    |   212     |     7    | DEV_MCASP3_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2                      | CLK_STATE_NOT_READY | 0               |
    |   212     |     8    | DEV_MCASP3_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3                      | CLK_STATE_NOT_READY | 0               |
    |   212     |     9    | DEV_MCASP3_MCASP_AFSX_POUT                                                        | CLK_STATE_READY     | 0               |
    |   212     |    10    | DEV_MCASP3_MCASP_AHCLKR_POUT                                                      | CLK_STATE_READY     | 0               |
    |   212     |    11    | DEV_MCASP3_MCASP_AHCLKR_PIN                                                       | CLK_STATE_READY     | 0               |
    |   212     |    12    | DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT                         | CLK_STATE_READY     | 0               |
    |   212     |    13    | DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT                        | CLK_STATE_READY     | 19200000        |
    |   212     |    14    | DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT                  | CLK_STATE_READY     | 0               |
    |   212     |    15    | DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT                  | CLK_STATE_READY     | 0               |
    |   212     |    20    | DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT               | CLK_STATE_NOT_READY | 0               |
    |   212     |    21    | DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1             | CLK_STATE_NOT_READY | 0               |
    |   212     |    22    | DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2             | CLK_STATE_NOT_READY | 0               |
    |   212     |    23    | DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3             | CLK_STATE_NOT_READY | 0               |
    |   212     |    28    | DEV_MCASP3_MCASP_ACLKX_POUT                                                       | CLK_STATE_READY     | 0               |
    |   212     |    29    | DEV_MCASP3_MCASP_AFSR_POUT                                                        | CLK_STATE_READY     | 0               |
    |   212     |    30    | DEV_MCASP3_VBUSP_CLK                                                              | CLK_STATE_READY     | 250000000       |
    |   212     |    31    | DEV_MCASP3_MCASP_ACLKR_POUT                                                       | CLK_STATE_READY     | 0               |
    |   212     |    32    | DEV_MCASP3_MCASP_AHCLKX_POUT                                                      | CLK_STATE_READY     | 0               |
    |   212     |    33    | DEV_MCASP3_MCASP_ACLKX_PIN                                                        | CLK_STATE_READY     | 0               |
    |   212     |    34    | DEV_MCASP3_MCASP_AHCLKX_PIN                                                       | CLK_STATE_READY     | 0               |
    |   212     |    35    | DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT                         | CLK_STATE_READY     | 0               |
    |   212     |    36    | DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT                        | CLK_STATE_READY     | 19200000        |
    |   212     |    37    | DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT                  | CLK_STATE_READY     | 0               |
    |   212     |    38    | DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT                  | CLK_STATE_READY     | 0               |
    |   212     |    43    | DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT               | CLK_STATE_NOT_READY | 0               |
    |   212     |    44    | DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1             | CLK_STATE_NOT_READY | 0               |
    |   212     |    45    | DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2             | CLK_STATE_NOT_READY | 0               |
    |   212     |    46    | DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3             | CLK_STATE_NOT_READY | 0               |
    |   212     |    51    | DEV_MCASP3_MCASP_ACLKR_PIN                                                        | CLK_STATE_READY     | 0               |
    |   213     |     0    | DEV_MCASP4_AUX_CLK                                                                | CLK_STATE_READY     | 196608000       |
    |   213     |     1    | DEV_MCASP4_AUX_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT0_CLK                       | CLK_STATE_READY     | 196608000       |
    |   213     |     2    | DEV_MCASP4_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK                       | CLK_STATE_READY     | 200000000       |
    |   213     |     5    | DEV_MCASP4_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT                        | CLK_STATE_NOT_READY | 0               |
    |   213     |     6    | DEV_MCASP4_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1                      | CLK_STATE_NOT_READY | 0               |
    |   213     |     7    | DEV_MCASP4_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2                      | CLK_STATE_NOT_READY | 0               |
    |   213     |     8    | DEV_MCASP4_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3                      | CLK_STATE_NOT_READY | 0               |
    |   213     |     9    | DEV_MCASP4_MCASP_AFSX_POUT                                                        | CLK_STATE_READY     | 0               |
    |   213     |    10    | DEV_MCASP4_MCASP_AHCLKR_POUT                                                      | CLK_STATE_READY     | 0               |
    |   213     |    11    | DEV_MCASP4_MCASP_AHCLKR_PIN                                                       | CLK_STATE_READY     | 0               |
    |   213     |    12    | DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT                         | CLK_STATE_READY     | 0               |
    |   213     |    13    | DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT                        | CLK_STATE_READY     | 19200000        |
    |   213     |    14    | DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT                  | CLK_STATE_READY     | 0               |
    |   213     |    15    | DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT                  | CLK_STATE_READY     | 0               |
    |   213     |    20    | DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT               | CLK_STATE_NOT_READY | 0               |
    |   213     |    21    | DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1             | CLK_STATE_NOT_READY | 0               |
    |   213     |    22    | DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2             | CLK_STATE_NOT_READY | 0               |
    |   213     |    23    | DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3             | CLK_STATE_NOT_READY | 0               |
    |   213     |    28    | DEV_MCASP4_MCASP_ACLKX_POUT                                                       | CLK_STATE_READY     | 0               |
    |   213     |    29    | DEV_MCASP4_MCASP_AFSR_POUT                                                        | CLK_STATE_READY     | 0               |
    |   213     |    30    | DEV_MCASP4_VBUSP_CLK                                                              | CLK_STATE_READY     | 250000000       |
    |   213     |    31    | DEV_MCASP4_MCASP_ACLKR_POUT                                                       | CLK_STATE_READY     | 0               |
    |   213     |    32    | DEV_MCASP4_MCASP_AHCLKX_POUT                                                      | CLK_STATE_READY     | 0               |
    |   213     |    33    | DEV_MCASP4_MCASP_ACLKX_PIN                                                        | CLK_STATE_READY     | 0               |
    |   213     |    34    | DEV_MCASP4_MCASP_AHCLKX_PIN                                                       | CLK_STATE_READY     | 0               |
    |   213     |    35    | DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT                         | CLK_STATE_READY     | 0               |
    |   213     |    36    | DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT                        | CLK_STATE_READY     | 19200000        |
    |   213     |    37    | DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT                  | CLK_STATE_READY     | 0               |
    |   213     |    38    | DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT                  | CLK_STATE_READY     | 0               |
    |   213     |    43    | DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT               | CLK_STATE_NOT_READY | 0               |
    |   213     |    44    | DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1             | CLK_STATE_NOT_READY | 0               |
    |   213     |    45    | DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2             | CLK_STATE_NOT_READY | 0               |
    |   213     |    46    | DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3             | CLK_STATE_NOT_READY | 0               |
    |   213     |    51    | DEV_MCASP4_MCASP_ACLKR_PIN                                                        | CLK_STATE_READY     | 0               |
    |   339     |     0    | DEV_MCSPI0_IO_CLKSPIO_CLK                                                         | CLK_STATE_READY     | 0               |
    |   339     |     1    | DEV_MCSPI0_VBUSP_CLK                                                              | CLK_STATE_READY     | 125000000       |
    |   339     |     2    | DEV_MCSPI0_CLKSPIREF_CLK                                                          | CLK_STATE_READY     | 50000000        |
    |   339     |     3    | DEV_MCSPI0_IO_CLKSPII_CLK                                                         | CLK_STATE_READY     | 0               |
    |   339     |     4    | DEV_MCSPI0_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI0_CLK_OUT                             | CLK_STATE_READY     | 0               |
    |   339     |     5    | DEV_MCSPI0_IO_CLKSPII_CLK_PARENT_SPI_MAIN_0_IO_CLKSPIO_CLK                        | CLK_STATE_NOT_READY | 0               |
    |   340     |     0    | DEV_MCSPI1_IO_CLKSPIO_CLK                                                         | CLK_STATE_READY     | 0               |
    |   340     |     1    | DEV_MCSPI1_VBUSP_CLK                                                              | CLK_STATE_READY     | 125000000       |
    |   340     |     2    | DEV_MCSPI1_CLKSPIREF_CLK                                                          | CLK_STATE_READY     | 50000000        |
    |   340     |     3    | DEV_MCSPI1_IO_CLKSPII_CLK                                                         | CLK_STATE_READY     | 0               |
    |   340     |     4    | DEV_MCSPI1_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI1_CLK_OUT                             | CLK_STATE_READY     | 0               |
    |   340     |     5    | DEV_MCSPI1_IO_CLKSPII_CLK_PARENT_SPI_MAIN_1_IO_CLKSPIO_CLK                        | CLK_STATE_NOT_READY | 0               |
    |   341     |     0    | DEV_MCSPI2_IO_CLKSPIO_CLK                                                         | CLK_STATE_READY     | 0               |
    |   341     |     1    | DEV_MCSPI2_VBUSP_CLK                                                              | CLK_STATE_READY     | 125000000       |
    |   341     |     2    | DEV_MCSPI2_CLKSPIREF_CLK                                                          | CLK_STATE_READY     | 50000000        |
    |   341     |     3    | DEV_MCSPI2_IO_CLKSPII_CLK                                                         | CLK_STATE_READY     | 0               |
    |   341     |     4    | DEV_MCSPI2_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI2_CLK_OUT                             | CLK_STATE_READY     | 0               |
    |   341     |     5    | DEV_MCSPI2_IO_CLKSPII_CLK_PARENT_SPI_MAIN_2_IO_CLKSPIO_CLK                        | CLK_STATE_NOT_READY | 0               |
    |   342     |     0    | DEV_MCSPI3_IO_CLKSPIO_CLK                                                         | CLK_STATE_READY     | 0               |
    |   342     |     1    | DEV_MCSPI3_VBUSP_CLK                                                              | CLK_STATE_READY     | 125000000       |
    |   342     |     2    | DEV_MCSPI3_CLKSPIREF_CLK                                                          | CLK_STATE_READY     | 50000000        |
    |   342     |     3    | DEV_MCSPI3_IO_CLKSPII_CLK                                                         | CLK_STATE_NOT_READY | 0               |
    |   342     |     4    | DEV_MCSPI3_IO_CLKSPII_CLK_PARENT_SPI_MAIN_3_IO_CLKSPIO_CLK                        | CLK_STATE_NOT_READY | 0               |
    |   342     |     5    | DEV_MCSPI3_IO_CLKSPII_CLK_PARENT_SPI3_CLK_LPBK_MUX_OUT0                           | CLK_STATE_READY     | 0               |
    |   343     |     0    | DEV_MCSPI4_IO_CLKSPIO_CLK                                                         | CLK_STATE_READY     | 0               |
    |   343     |     1    | DEV_MCSPI4_VBUSP_CLK                                                              | CLK_STATE_READY     | 125000000       |
    |   343     |     2    | DEV_MCSPI4_CLKSPIREF_CLK                                                          | CLK_STATE_READY     | 50000000        |
    |   343     |     3    | DEV_MCSPI4_IO_CLKSPII_CLK                                                         | CLK_STATE_NOT_READY | 0               |
    |   344     |     0    | DEV_MCSPI5_IO_CLKSPIO_CLK                                                         | CLK_STATE_READY     | 0               |
    |   344     |     1    | DEV_MCSPI5_VBUSP_CLK                                                              | CLK_STATE_READY     | 125000000       |
    |   344     |     2    | DEV_MCSPI5_CLKSPIREF_CLK                                                          | CLK_STATE_READY     | 50000000        |
    |   344     |     3    | DEV_MCSPI5_IO_CLKSPII_CLK                                                         | CLK_STATE_READY     | 0               |
    |   344     |     4    | DEV_MCSPI5_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI5_CLK_OUT                             | CLK_STATE_READY     | 0               |
    |   344     |     5    | DEV_MCSPI5_IO_CLKSPII_CLK_PARENT_SPI_MAIN_5_IO_CLKSPIO_CLK                        | CLK_STATE_NOT_READY | 0               |
    |   345     |     0    | DEV_MCSPI6_IO_CLKSPIO_CLK                                                         | CLK_STATE_READY     | 0               |
    |   345     |     1    | DEV_MCSPI6_VBUSP_CLK                                                              | CLK_STATE_READY     | 125000000       |
    |   345     |     2    | DEV_MCSPI6_CLKSPIREF_CLK                                                          | CLK_STATE_READY     | 50000000        |
    |   345     |     3    | DEV_MCSPI6_IO_CLKSPII_CLK                                                         | CLK_STATE_READY     | 0               |
    |   345     |     4    | DEV_MCSPI6_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI6_CLK_OUT                             | CLK_STATE_READY     | 0               |
    |   345     |     5    | DEV_MCSPI6_IO_CLKSPII_CLK_PARENT_SPI_MAIN_6_IO_CLKSPIO_CLK                        | CLK_STATE_NOT_READY | 0               |
    |   346     |     0    | DEV_MCSPI7_IO_CLKSPIO_CLK                                                         | CLK_STATE_READY     | 0               |
    |   346     |     1    | DEV_MCSPI7_VBUSP_CLK                                                              | CLK_STATE_READY     | 125000000       |
    |   346     |     2    | DEV_MCSPI7_CLKSPIREF_CLK                                                          | CLK_STATE_READY     | 50000000        |
    |   346     |     3    | DEV_MCSPI7_IO_CLKSPII_CLK                                                         | CLK_STATE_READY     | 0               |
    |   346     |     4    | DEV_MCSPI7_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI7_CLK_OUT                             | CLK_STATE_READY     | 0               |
    |   346     |     5    | DEV_MCSPI7_IO_CLKSPII_CLK_PARENT_SPI_MAIN_7_IO_CLKSPIO_CLK                        | CLK_STATE_NOT_READY | 0               |
    |     0     |     0    | DEV_MCU_ADC12FC_16FFC0_ADC_CLK                                                    | CLK_STATE_READY     | 19200000        |
    |     0     |     1    | DEV_MCU_ADC12FC_16FFC0_ADC_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                     | CLK_STATE_READY     | 19200000        |
    |     0     |     2    | DEV_MCU_ADC12FC_16FFC0_ADC_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT1_CLK            | CLK_STATE_READY     | 60000000        |
    |     0     |     3    | DEV_MCU_ADC12FC_16FFC0_ADC_CLK_PARENT_HSDIV1_16FFT_MCU_0_HSDIVOUT1_CLK            | CLK_STATE_READY     | 58823529        |
    |     0     |     4    | DEV_MCU_ADC12FC_16FFC0_ADC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                 | CLK_STATE_READY     | 0               |
    |     0     |     5    | DEV_MCU_ADC12FC_16FFC0_VBUS_CLK                                                   | CLK_STATE_READY     | 333333333       |
    |     0     |     6    | DEV_MCU_ADC12FC_16FFC0_SYS_CLK                                                    | CLK_STATE_READY     | 500000000       |
    |     1     |     0    | DEV_MCU_ADC12FC_16FFC1_ADC_CLK                                                    | CLK_STATE_READY     | 19200000        |
    |     1     |     1    | DEV_MCU_ADC12FC_16FFC1_ADC_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                     | CLK_STATE_READY     | 19200000        |
    |     1     |     2    | DEV_MCU_ADC12FC_16FFC1_ADC_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT1_CLK            | CLK_STATE_READY     | 60000000        |
    |     1     |     3    | DEV_MCU_ADC12FC_16FFC1_ADC_CLK_PARENT_HSDIV1_16FFT_MCU_0_HSDIVOUT1_CLK            | CLK_STATE_READY     | 58823529        |
    |     1     |     4    | DEV_MCU_ADC12FC_16FFC1_ADC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                 | CLK_STATE_READY     | 0               |
    |     1     |     5    | DEV_MCU_ADC12FC_16FFC1_VBUS_CLK                                                   | CLK_STATE_READY     | 333333333       |
    |     1     |     6    | DEV_MCU_ADC12FC_16FFC1_SYS_CLK                                                    | CLK_STATE_READY     | 500000000       |
    |    29     |     0    | DEV_MCU_CPSW0_MDIO_MDCLK_O                                                        | CLK_STATE_READY     | 0               |
    |    29     |     1    | DEV_MCU_CPSW0_CPTS_GENF0                                                          | CLK_STATE_READY     | 0               |
    |    29     |     3    | DEV_MCU_CPSW0_CPTS_RFT_CLK                                                        | CLK_STATE_READY     | 500000000       |
    |    29     |     4    | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK               | CLK_STATE_READY     | 250000000       |
    |    29     |     5    | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK             | CLK_STATE_READY     | 200000000       |
    |    29     |     6    | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT                   | CLK_STATE_READY     | 0               |
    |    29     |     7    | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT                       | CLK_STATE_READY     | 0               |
    |    29     |     8    | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                     | CLK_STATE_READY     | 0               |
    |    29     |     9    | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT                         | CLK_STATE_READY     | 0               |
    |    29     |    10    | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN0_TXMCLK              | CLK_STATE_READY     | 0               |
    |    29     |    11    | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN1_TXMCLK              | CLK_STATE_READY     | 0               |
    |    29     |    12    | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN2_TXMCLK              | CLK_STATE_READY     | 0               |
    |    29     |    13    | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN3_TXMCLK              | CLK_STATE_READY     | 0               |
    |    29     |    18    | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK                | CLK_STATE_READY     | 500000000       |
    |    29     |    19    | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK2      | CLK_STATE_READY     | 500000000       |
    |    29     |    20    | DEV_MCU_CPSW0_GMII1_MR_CLK                                                        | CLK_STATE_READY     | 25000000        |
    |    29     |    21    | DEV_MCU_CPSW0_GMII_RFT_CLK                                                        | CLK_STATE_READY     | 125000000       |
    |    29     |    22    | DEV_MCU_CPSW0_RGMII1_RXC_I                                                        | CLK_STATE_READY     | 0               |
    |    29     |    26    | DEV_MCU_CPSW0_RMII_MHZ_50_CLK                                                     | CLK_STATE_READY     | 0               |
    |    29     |    27    | DEV_MCU_CPSW0_RGMII1_TXC_O                                                        | CLK_STATE_READY     | 0               |
    |    29     |    28    | DEV_MCU_CPSW0_CPPI_CLK_CLK                                                        | CLK_STATE_READY     | 333333333       |
    |    29     |    29    | DEV_MCU_CPSW0_RGMII_MHZ_5_CLK                                                     | CLK_STATE_READY     | 5000000         |
    |    29     |    30    | DEV_MCU_CPSW0_GMII1_MT_CLK                                                        | CLK_STATE_READY     | 25000000        |
    |    29     |    32    | DEV_MCU_CPSW0_RGMII_MHZ_50_CLK                                                    | CLK_STATE_READY     | 50000000        |
    |    29     |    33    | DEV_MCU_CPSW0_RGMII_MHZ_250_CLK                                                   | CLK_STATE_READY     | 250000000       |
    |    37     |     0    | DEV_MCU_CPT2_AGGR0_VCLK_CLK                                                       | CLK_STATE_READY     | 333333333       |
    |    53     |     0    | DEV_MCU_DCC0_DCC_CLKSRC0_CLK                                                      | CLK_STATE_READY     | 200000000       |
    |    53     |     1    | DEV_MCU_DCC0_DCC_CLKSRC1_CLK                                                      | CLK_STATE_READY     | 60000000        |
    |    53     |     2    | DEV_MCU_DCC0_DCC_CLKSRC2_CLK                                                      | CLK_STATE_READY     | 80000000        |
    |    53     |     3    | DEV_MCU_DCC0_DCC_CLKSRC3_CLK                                                      | CLK_STATE_READY     | 96000000        |
    |    53     |     4    | DEV_MCU_DCC0_DCC_CLKSRC4_CLK                                                      | CLK_STATE_READY     | 133333333       |
    |    53     |     5    | DEV_MCU_DCC0_DCC_CLKSRC5_CLK                                                      | CLK_STATE_READY     | 32000           |
    |    53     |     6    | DEV_MCU_DCC0_DCC_CLKSRC6_CLK                                                      | CLK_STATE_READY     | 32768           |
    |    53     |     7    | DEV_MCU_DCC0_DCC_CLKSRC7_CLK                                                      | CLK_STATE_READY     | 0               |
    |    53     |     8    | DEV_MCU_DCC0_DCC_INPUT00_CLK                                                      | CLK_STATE_READY     | 19200000        |
    |    53     |     9    | DEV_MCU_DCC0_DCC_INPUT01_CLK                                                      | CLK_STATE_READY     | 32000           |
    |    53     |    10    | DEV_MCU_DCC0_DCC_INPUT02_CLK                                                      | CLK_STATE_READY     | 12500000        |
    |    53     |    11    | DEV_MCU_DCC0_DCC_INPUT10_CLK                                                      | CLK_STATE_READY     | 333333333       |
    |    53     |    12    | DEV_MCU_DCC0_VBUS_CLK                                                             | CLK_STATE_READY     | 166666666       |
    |    54     |     0    | DEV_MCU_DCC1_DCC_CLKSRC0_CLK                                                      | CLK_STATE_READY     | 250000000       |
    |    54     |     1    | DEV_MCU_DCC1_DCC_CLKSRC1_CLK                                                      | CLK_STATE_READY     | 200000000       |
    |    54     |     2    | DEV_MCU_DCC1_DCC_CLKSRC2_CLK                                                      | CLK_STATE_READY     | 80000000        |
    |    54     |     3    | DEV_MCU_DCC1_DCC_CLKSRC3_CLK                                                      | CLK_STATE_READY     | 166666666       |
    |    54     |     4    | DEV_MCU_DCC1_DCC_CLKSRC4_CLK                                                      | CLK_STATE_READY     | 250000000       |
    |    54     |     5    | DEV_MCU_DCC1_DCC_CLKSRC5_CLK                                                      | CLK_STATE_READY     | 58823529        |
    |    54     |     6    | DEV_MCU_DCC1_DCC_CLKSRC6_CLK                                                      | CLK_STATE_READY     | 0               |
    |    54     |     7    | DEV_MCU_DCC1_DCC_CLKSRC7_CLK                                                      | CLK_STATE_READY     | 500000000       |
    |    54     |     8    | DEV_MCU_DCC1_DCC_INPUT00_CLK                                                      | CLK_STATE_READY     | 19200000        |
    |    54     |     9    | DEV_MCU_DCC1_DCC_INPUT01_CLK                                                      | CLK_STATE_READY     | 32768           |
    |    54     |    10    | DEV_MCU_DCC1_DCC_INPUT02_CLK                                                      | CLK_STATE_READY     | 12500000        |
    |    54     |    11    | DEV_MCU_DCC1_DCC_INPUT10_CLK                                                      | CLK_STATE_READY     | 250000000       |
    |    54     |    12    | DEV_MCU_DCC1_VBUS_CLK                                                             | CLK_STATE_READY     | 166666666       |
    |    55     |     0    | DEV_MCU_DCC2_DCC_CLKSRC0_CLK                                                      | CLK_STATE_READY     | 0               |
    |    55     |     1    | DEV_MCU_DCC2_DCC_CLKSRC1_CLK                                                      | CLK_STATE_READY     | 0               |
    |    55     |     2    | DEV_MCU_DCC2_DCC_CLKSRC2_CLK                                                      | CLK_STATE_READY     | 0               |
    |    55     |     3    | DEV_MCU_DCC2_DCC_CLKSRC3_CLK                                                      | CLK_STATE_READY     | 192000000       |
    |    55     |     4    | DEV_MCU_DCC2_DCC_CLKSRC4_CLK                                                      | CLK_STATE_READY     | 0               |
    |    55     |     6    | DEV_MCU_DCC2_DCC_CLKSRC6_CLK                                                      | CLK_STATE_READY     | 12500000        |
    |    55     |     7    | DEV_MCU_DCC2_DCC_CLKSRC7_CLK                                                      | CLK_STATE_READY     | 19200000        |
    |    55     |     8    | DEV_MCU_DCC2_DCC_INPUT00_CLK                                                      | CLK_STATE_READY     | 19200000        |
    |    55     |     9    | DEV_MCU_DCC2_DCC_INPUT01_CLK                                                      | CLK_STATE_READY     | 0               |
    |    55     |    10    | DEV_MCU_DCC2_DCC_INPUT02_CLK                                                      | CLK_STATE_READY     | 12500000        |
    |    55     |    11    | DEV_MCU_DCC2_DCC_INPUT10_CLK                                                      | CLK_STATE_READY     | 333333333       |
    |    55     |    12    | DEV_MCU_DCC2_VBUS_CLK                                                             | CLK_STATE_READY     | 166666666       |
    |   105     |     0    | DEV_MCU_ESM0_CLK                                                                  | CLK_STATE_READY     | 166666666       |
    |   107     |     0    | DEV_MCU_FSS0_FSAS_0_GCLK                                                          | CLK_STATE_READY     | 1000000000      |
    |   108     |     1    | DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_CLKX2_INV_CLK                                      | CLK_STATE_READY     | 166666666       |
    |   108     |     2    | DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_CLKX1_INV_CLK                                      | CLK_STATE_READY     | 83333333        |
    |   108     |     3    | DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_CLKX1_CLK                                          | CLK_STATE_READY     | 83333333        |
    |   108     |     6    | DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_CLKX2_CLK                                          | CLK_STATE_READY     | 166666666       |
    |   108     |     7    | DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_OUT_CLK_N                                          | CLK_STATE_READY     | 0               |
    |   108     |     8    | DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_OUT_CLK_P                                          | CLK_STATE_READY     | 0               |
    |   108     |    11    | DEV_MCU_FSS0_HYPERBUS1P0_0_CBA_CLK                                                | CLK_STATE_READY     | 1000000000      |
    |   109     |     0    | DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK                                                 | CLK_STATE_READY     | 0               |
    |   109     |     1    | DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK_PARENT_BOARD_0_MCU_OSPI0_DQS_OUT                | CLK_STATE_READY     | 0               |
    |   109     |     2    | DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK_PARENT_FSS_MCU_0_OSPI_0_OSPI_OCLK_CLK           | CLK_STATE_READY     | 0               |
    |   109     |     3    | DEV_MCU_FSS0_OSPI_0_OSPI_HCLK_CLK                                                 | CLK_STATE_READY     | 1000000000      |
    |   109     |     4    | DEV_MCU_FSS0_OSPI_0_OSPI_OCLK_CLK                                                 | CLK_STATE_READY     | 0               |
    |   109     |     5    | DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK                                                 | CLK_STATE_READY     | 133333333       |
    |   109     |     6    | DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT4_CLK         | CLK_STATE_READY     | 133333333       |
    |   109     |     7    | DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT4_CLK         | CLK_STATE_READY     | 166666666       |
    |   109     |     8    | DEV_MCU_FSS0_OSPI_0_OSPI_DQS_CLK                                                  | CLK_STATE_READY     | 0               |
    |   109     |     9    | DEV_MCU_FSS0_OSPI_0_OSPI_PCLK_CLK                                                 | CLK_STATE_READY     | 1000000000      |
    |   110     |     0    | DEV_MCU_FSS0_OSPI_1_OSPI_ICLK_CLK                                                 | CLK_STATE_READY     | 0               |
    |   110     |     1    | DEV_MCU_FSS0_OSPI_1_OSPI_ICLK_CLK_PARENT_BOARD_0_MCU_OSPI1_DQS_OUT                | CLK_STATE_READY     | 0               |
    |   110     |     2    | DEV_MCU_FSS0_OSPI_1_OSPI_ICLK_CLK_PARENT_FSS_MCU_0_OSPI_1_OSPI_OCLK_CLK           | CLK_STATE_READY     | 0               |
    |   110     |     3    | DEV_MCU_FSS0_OSPI_1_OSPI_HCLK_CLK                                                 | CLK_STATE_READY     | 1000000000      |
    |   110     |     4    | DEV_MCU_FSS0_OSPI_1_OSPI_OCLK_CLK                                                 | CLK_STATE_READY     | 0               |
    |   110     |     5    | DEV_MCU_FSS0_OSPI_1_OSPI_RCLK_CLK                                                 | CLK_STATE_READY     | 133333333       |
    |   110     |     6    | DEV_MCU_FSS0_OSPI_1_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT4_CLK         | CLK_STATE_READY     | 133333333       |
    |   110     |     7    | DEV_MCU_FSS0_OSPI_1_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT4_CLK         | CLK_STATE_READY     | 166666666       |
    |   110     |     8    | DEV_MCU_FSS0_OSPI_1_OSPI_DQS_CLK                                                  | CLK_STATE_READY     | 0               |
    |   110     |     9    | DEV_MCU_FSS0_OSPI_1_OSPI_PCLK_CLK                                                 | CLK_STATE_READY     | 1000000000      |
    |   221     |     0    | DEV_MCU_I2C0_PORSCL                                                               | CLK_STATE_READY     | 0               |
    |   221     |     1    | DEV_MCU_I2C0_PISYS_CLK                                                            | CLK_STATE_READY     | 96000000        |
    |   221     |     2    | DEV_MCU_I2C0_CLK                                                                  | CLK_STATE_READY     | 166666666       |
    |   221     |     3    | DEV_MCU_I2C0_PISCL                                                                | CLK_STATE_READY     | 0               |
    |   222     |     0    | DEV_MCU_I2C1_PORSCL                                                               | CLK_STATE_READY     | 0               |
    |   222     |     1    | DEV_MCU_I2C1_PISYS_CLK                                                            | CLK_STATE_READY     | 96000000        |
    |   222     |     2    | DEV_MCU_I2C1_CLK                                                                  | CLK_STATE_READY     | 166666666       |
    |   222     |     3    | DEV_MCU_I2C1_PISCL                                                                | CLK_STATE_READY     | 0               |
    |   118     |     0    | DEV_MCU_I3C0_I3C_SCL_DI                                                           | CLK_STATE_READY     | 0               |
    |   118     |     1    | DEV_MCU_I3C0_I3C_SCL_DO                                                           | CLK_STATE_READY     | 0               |
    |   118     |     2    | DEV_MCU_I3C0_I3C_SCLK_CLK                                                         | CLK_STATE_READY     | 166666666       |
    |   118     |     3    | DEV_MCU_I3C0_I3C_PCLK_CLK                                                         | CLK_STATE_READY     | 166666666       |
    |   118     |     4    | DEV_MCU_I3C0_I3C_SDA_DI                                                           | CLK_STATE_READY     | 0               |
    |   119     |     2    | DEV_MCU_I3C1_I3C_SCLK_CLK                                                         | CLK_STATE_READY     | 166666666       |
    |   119     |     3    | DEV_MCU_I3C1_I3C_PCLK_CLK                                                         | CLK_STATE_READY     | 166666666       |
    |   207     |     0    | DEV_MCU_MCAN0_MCANSS_HCLK_CLK                                                     | CLK_STATE_READY     | 166666666       |
    |   207     |     1    | DEV_MCU_MCAN0_MCANSS_CCLK_CLK                                                     | CLK_STATE_READY     | 80000000        |
    |   207     |     2    | DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT3_CLK             | CLK_STATE_READY     | 80000000        |
    |   207     |     3    | DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                  | CLK_STATE_READY     | 0               |
    |   207     |     4    | DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT2_CLK             | CLK_STATE_READY     | 80000000        |
    |   207     |     5    | DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                      | CLK_STATE_READY     | 19200000        |
    |   207     |     6    | DEV_MCU_MCAN0_MCANSS_CAN_RXD                                                      | CLK_STATE_READY     | 0               |
    |   208     |     0    | DEV_MCU_MCAN1_MCANSS_HCLK_CLK                                                     | CLK_STATE_READY     | 166666666       |
    |   208     |     1    | DEV_MCU_MCAN1_MCANSS_CCLK_CLK                                                     | CLK_STATE_READY     | 80000000        |
    |   208     |     2    | DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT3_CLK             | CLK_STATE_READY     | 80000000        |
    |   208     |     3    | DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                  | CLK_STATE_READY     | 0               |
    |   208     |     4    | DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT2_CLK             | CLK_STATE_READY     | 80000000        |
    |   208     |     5    | DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                      | CLK_STATE_READY     | 19200000        |
    |   208     |     6    | DEV_MCU_MCAN1_MCANSS_CAN_RXD                                                      | CLK_STATE_READY     | 0               |
    |   347     |     0    | DEV_MCU_MCSPI0_IO_CLKSPIO_CLK                                                     | CLK_STATE_READY     | 0               |
    |   347     |     1    | DEV_MCU_MCSPI0_VBUSP_CLK                                                          | CLK_STATE_READY     | 166666666       |
    |   347     |     2    | DEV_MCU_MCSPI0_CLKSPIREF_CLK                                                      | CLK_STATE_READY     | 50000000        |
    |   347     |     3    | DEV_MCU_MCSPI0_IO_CLKSPII_CLK                                                     | CLK_STATE_READY     | 0               |
    |   347     |     4    | DEV_MCU_MCSPI0_IO_CLKSPII_CLK_PARENT_BOARD_0_MCU_SPI0_CLK_OUT                     | CLK_STATE_READY     | 0               |
    |   347     |     5    | DEV_MCU_MCSPI0_IO_CLKSPII_CLK_PARENT_SPI_MCU_0_IO_CLKSPIO_CLK                     | CLK_STATE_READY     | 0               |
    |   348     |     0    | DEV_MCU_MCSPI1_IO_CLKSPIO_CLK                                                     | CLK_STATE_READY     | 0               |
    |   348     |     1    | DEV_MCU_MCSPI1_VBUSP_CLK                                                          | CLK_STATE_READY     | 166666666       |
    |   348     |     2    | DEV_MCU_MCSPI1_CLKSPIREF_CLK                                                      | CLK_STATE_READY     | 50000000        |
    |   348     |     3    | DEV_MCU_MCSPI1_IO_CLKSPII_CLK                                                     | CLK_STATE_NOT_READY | 0               |
    |   348     |     4    | DEV_MCU_MCSPI1_IO_CLKSPII_CLK_PARENT_SPI_MAIN_3_IO_CLKSPIO_CLK                    | CLK_STATE_NOT_READY | 0               |
    |   348     |     5    | DEV_MCU_MCSPI1_IO_CLKSPII_CLK_PARENT_MCU_SPI1_CLK_LPBK_MUX_OUT0                   | CLK_STATE_READY     | 0               |
    |   349     |     0    | DEV_MCU_MCSPI2_IO_CLKSPIO_CLK                                                     | CLK_STATE_READY     | 0               |
    |   349     |     1    | DEV_MCU_MCSPI2_VBUSP_CLK                                                          | CLK_STATE_READY     | 166666666       |
    |   349     |     2    | DEV_MCU_MCSPI2_CLKSPIREF_CLK                                                      | CLK_STATE_READY     | 50000000        |
    |   349     |     3    | DEV_MCU_MCSPI2_IO_CLKSPII_CLK                                                     | CLK_STATE_READY     | 0               |
    |   268     |     0    | DEV_MCU_NAVSS0_INTR_ROUTER_0_INTR_CLK                                             | CLK_STATE_READY     | 1000000000      |
    |   269     |     0    | DEV_MCU_NAVSS0_MCRC_0_CLK                                                         | CLK_STATE_READY     | 1000000000      |
    |   270     |     0    | DEV_MCU_NAVSS0_MODSS_VD2CLK                                                       | CLK_STATE_READY     | 1000000000      |
    |   271     |     0    | DEV_MCU_NAVSS0_PROXY0_CLK_CLK                                                     | CLK_STATE_READY     | 1000000000      |
    |   272     |     0    | DEV_MCU_NAVSS0_RINGACC0_SYS_CLK                                                   | CLK_STATE_READY     | 1000000000      |
    |   273     |     0    | DEV_MCU_NAVSS0_UDMAP_0_SYS_CLK                                                    | CLK_STATE_READY     | 1000000000      |
    |   274     |     0    | DEV_MCU_NAVSS0_UDMASS_VD2CLK                                                      | CLK_STATE_READY     | 1000000000      |
    |   275     |     0    | DEV_MCU_NAVSS0_UDMASS_INTA_0_SYS_CLK                                              | CLK_STATE_READY     | 1000000000      |
    |   176     |     0    | DEV_MCU_PBIST0_CLK6_CLK                                                           | CLK_STATE_READY     | 83333333        |
    |   176     |     1    | DEV_MCU_PBIST0_CLK8_CLK                                                           | CLK_STATE_READY     | 83333333        |
    |   176     |     3    | DEV_MCU_PBIST0_CLK3_CLK                                                           | CLK_STATE_READY     | 166666666       |
    |   176     |     4    | DEV_MCU_PBIST0_CLK7_CLK                                                           | CLK_STATE_READY     | 83333333        |
    |   176     |     6    | DEV_MCU_PBIST0_CLK4_CLK                                                           | CLK_STATE_READY     | 83333333        |
    |   176     |     7    | DEV_MCU_PBIST0_CLK5_CLK                                                           | CLK_STATE_READY     | 83333333        |
    |   176     |     8    | DEV_MCU_PBIST0_CLK1_CLK                                                           | CLK_STATE_READY     | 500000000       |
    |   176     |     9    | DEV_MCU_PBIST0_CLK2_CLK                                                           | CLK_STATE_READY     | 333333333       |
    |   177     |     0    | DEV_MCU_PBIST1_CLK6_CLK                                                           | CLK_STATE_READY     | 83333333        |
    |   177     |     1    | DEV_MCU_PBIST1_CLK8_CLK                                                           | CLK_STATE_READY     | 83333333        |
    |   177     |     3    | DEV_MCU_PBIST1_CLK3_CLK                                                           | CLK_STATE_READY     | 333333333       |
    |   177     |     4    | DEV_MCU_PBIST1_CLK7_CLK                                                           | CLK_STATE_READY     | 83333333        |
    |   177     |     6    | DEV_MCU_PBIST1_CLK4_CLK                                                           | CLK_STATE_READY     | 83333333        |
    |   177     |     7    | DEV_MCU_PBIST1_CLK5_CLK                                                           | CLK_STATE_READY     | 166666666       |
    |   177     |     8    | DEV_MCU_PBIST1_CLK1_CLK                                                           | CLK_STATE_READY     | 500000000       |
    |   177     |     9    | DEV_MCU_PBIST1_CLK2_CLK                                                           | CLK_STATE_READY     | 400000000       |
    |   178     |     1    | DEV_MCU_PBIST2_CLK8_CLK                                                           | CLK_STATE_READY     | 83333333        |
    |   284     |     0    | DEV_MCU_R5FSS0_CORE0_CPU_CLK                                                      | CLK_STATE_READY     | 1000000000      |
    |   284     |     1    | DEV_MCU_R5FSS0_CORE0_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK     | CLK_STATE_READY     | 1000000000      |
    |   284     |     2    | DEV_MCU_R5FSS0_CORE0_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK3    | CLK_STATE_READY     | 333333333       |
    |   284     |     3    | DEV_MCU_R5FSS0_CORE0_INTERFACE_CLK                                                | CLK_STATE_READY     | 1000000000      |
    |   284     |     4    | DEV_MCU_R5FSS0_CORE0_INTERFACE_PHASE                                              | CLK_STATE_READY     | 333333333       |
    |   285     |     0    | DEV_MCU_R5FSS0_CORE1_CPU_CLK                                                      | CLK_STATE_READY     | 1000000000      |
    |   285     |     1    | DEV_MCU_R5FSS0_CORE1_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK     | CLK_STATE_READY     | 1000000000      |
    |   285     |     2    | DEV_MCU_R5FSS0_CORE1_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK3    | CLK_STATE_READY     | 333333333       |
    |   285     |     3    | DEV_MCU_R5FSS0_CORE1_INTERFACE_CLK                                                | CLK_STATE_READY     | 1000000000      |
    |   285     |     4    | DEV_MCU_R5FSS0_CORE1_INTERFACE_PHASE                                              | CLK_STATE_READY     | 333333333       |
    |   295     |     0    | DEV_MCU_RTI0_VBUSP_CLK                                                            | CLK_STATE_READY     | 166666666       |
    |   295     |     1    | DEV_MCU_RTI0_RTI_CLK                                                              | CLK_STATE_READY     | 19200000        |
    |   295     |     2    | DEV_MCU_RTI0_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                               | CLK_STATE_READY     | 19200000        |
    |   295     |     3    | DEV_MCU_RTI0_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                               | CLK_STATE_READY     | 32768           |
    |   295     |     4    | DEV_MCU_RTI0_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK          | CLK_STATE_READY     | 12500000        |
    |   295     |     5    | DEV_MCU_RTI0_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK            | CLK_STATE_READY     | 32000           |
    |   296     |     0    | DEV_MCU_RTI1_VBUSP_CLK                                                            | CLK_STATE_READY     | 166666666       |
    |   296     |     1    | DEV_MCU_RTI1_RTI_CLK                                                              | CLK_STATE_READY     | 19200000        |
    |   296     |     2    | DEV_MCU_RTI1_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                               | CLK_STATE_READY     | 19200000        |
    |   296     |     3    | DEV_MCU_RTI1_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                               | CLK_STATE_READY     | 32768           |
    |   296     |     4    | DEV_MCU_RTI1_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK          | CLK_STATE_READY     | 12500000        |
    |   296     |     5    | DEV_MCU_RTI1_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK            | CLK_STATE_READY     | 32000           |
    |    35     |     0    | DEV_MCU_TIMER0_TIMER_PWM                                                          | CLK_STATE_READY     | 0               |
    |    35     |     1    | DEV_MCU_TIMER0_TIMER_TCLK_CLK                                                     | CLK_STATE_READY     | 62500000        |
    |    35     |     2    | DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                      | CLK_STATE_READY     | 19200000        |
    |    35     |     3    | DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK16  | CLK_STATE_READY     | 62500000        |
    |    35     |     4    | DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY     | 12500000        |
    |    35     |     5    | DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK             | CLK_STATE_READY     | 200000000       |
    |    35     |     6    | DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                  | CLK_STATE_READY     | 0               |
    |    35     |     7    | DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                      | CLK_STATE_READY     | 32768           |
    |    35     |     8    | DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0                  | CLK_STATE_READY     | 0               |
    |    35     |     9    | DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK   | CLK_STATE_READY     | 32000           |
    |    35     |    10    | DEV_MCU_TIMER0_TIMER_HCLK_CLK                                                     | CLK_STATE_READY     | 166666666       |
    |    83     |     1    | DEV_MCU_TIMER1_TIMER_TCLK_CLK                                                     | CLK_STATE_READY     | 19200000        |
    |    83     |     2    | DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT1                        | CLK_STATE_READY     | 19200000        |
    |    83     |     3    | DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_0_TIMER_PWM               | CLK_STATE_READY     | 0               |
    |    83     |    10    | DEV_MCU_TIMER1_TIMER_HCLK_CLK                                                     | CLK_STATE_READY     | 166666666       |
    |    84     |     0    | DEV_MCU_TIMER2_TIMER_PWM                                                          | CLK_STATE_READY     | 0               |
    |    84     |     1    | DEV_MCU_TIMER2_TIMER_TCLK_CLK                                                     | CLK_STATE_READY     | 19200000        |
    |    84     |     2    | DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                      | CLK_STATE_READY     | 19200000        |
    |    84     |     3    | DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK16  | CLK_STATE_READY     | 62500000        |
    |    84     |     4    | DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY     | 12500000        |
    |    84     |     5    | DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK             | CLK_STATE_READY     | 200000000       |
    |    84     |     6    | DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                  | CLK_STATE_READY     | 0               |
    |    84     |     7    | DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                      | CLK_STATE_READY     | 32768           |
    |    84     |     8    | DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0                  | CLK_STATE_READY     | 0               |
    |    84     |     9    | DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK   | CLK_STATE_READY     | 32000           |
    |    84     |    10    | DEV_MCU_TIMER2_TIMER_HCLK_CLK                                                     | CLK_STATE_READY     | 166666666       |
    |    85     |     1    | DEV_MCU_TIMER3_TIMER_TCLK_CLK                                                     | CLK_STATE_READY     | 19200000        |
    |    85     |     2    | DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT3                        | CLK_STATE_READY     | 19200000        |
    |    85     |     3    | DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_2_TIMER_PWM               | CLK_STATE_READY     | 0               |
    |    85     |    10    | DEV_MCU_TIMER3_TIMER_HCLK_CLK                                                     | CLK_STATE_READY     | 166666666       |
    |    86     |     0    | DEV_MCU_TIMER4_TIMER_PWM                                                          | CLK_STATE_READY     | 0               |
    |    86     |     1    | DEV_MCU_TIMER4_TIMER_TCLK_CLK                                                     | CLK_STATE_READY     | 19200000        |
    |    86     |     2    | DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                      | CLK_STATE_READY     | 19200000        |
    |    86     |     3    | DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK16  | CLK_STATE_READY     | 62500000        |
    |    86     |     4    | DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY     | 12500000        |
    |    86     |     5    | DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK             | CLK_STATE_READY     | 200000000       |
    |    86     |     6    | DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                  | CLK_STATE_READY     | 0               |
    |    86     |     7    | DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                      | CLK_STATE_READY     | 32768           |
    |    86     |     8    | DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0                  | CLK_STATE_READY     | 0               |
    |    86     |     9    | DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK   | CLK_STATE_READY     | 32000           |
    |    86     |    10    | DEV_MCU_TIMER4_TIMER_HCLK_CLK                                                     | CLK_STATE_READY     | 166666666       |
    |    87     |     1    | DEV_MCU_TIMER5_TIMER_TCLK_CLK                                                     | CLK_STATE_READY     | 19200000        |
    |    87     |     2    | DEV_MCU_TIMER5_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT5                        | CLK_STATE_READY     | 19200000        |
    |    87     |     3    | DEV_MCU_TIMER5_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_4_TIMER_PWM               | CLK_STATE_READY     | 0               |
    |    87     |    10    | DEV_MCU_TIMER5_TIMER_HCLK_CLK                                                     | CLK_STATE_READY     | 166666666       |
    |    88     |     0    | DEV_MCU_TIMER6_TIMER_PWM                                                          | CLK_STATE_READY     | 0               |
    |    88     |     1    | DEV_MCU_TIMER6_TIMER_TCLK_CLK                                                     | CLK_STATE_READY     | 19200000        |
    |    88     |     2    | DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                      | CLK_STATE_READY     | 19200000        |
    |    88     |     3    | DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK16  | CLK_STATE_READY     | 62500000        |
    |    88     |     4    | DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY     | 12500000        |
    |    88     |     5    | DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK             | CLK_STATE_READY     | 200000000       |
    |    88     |     6    | DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                  | CLK_STATE_READY     | 0               |
    |    88     |     7    | DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                      | CLK_STATE_READY     | 32768           |
    |    88     |     8    | DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0                  | CLK_STATE_READY     | 0               |
    |    88     |     9    | DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK   | CLK_STATE_READY     | 32000           |
    |    88     |    10    | DEV_MCU_TIMER6_TIMER_HCLK_CLK                                                     | CLK_STATE_READY     | 166666666       |
    |    89     |     1    | DEV_MCU_TIMER7_TIMER_TCLK_CLK                                                     | CLK_STATE_READY     | 19200000        |
    |    89     |     2    | DEV_MCU_TIMER7_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT7                        | CLK_STATE_READY     | 19200000        |
    |    89     |     3    | DEV_MCU_TIMER7_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_6_TIMER_PWM               | CLK_STATE_READY     | 0               |
    |    89     |    10    | DEV_MCU_TIMER7_TIMER_HCLK_CLK                                                     | CLK_STATE_READY     | 166666666       |
    |    90     |     0    | DEV_MCU_TIMER8_TIMER_PWM                                                          | CLK_STATE_READY     | 0               |
    |    90     |     1    | DEV_MCU_TIMER8_TIMER_TCLK_CLK                                                     | CLK_STATE_READY     | 19200000        |
    |    90     |     2    | DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                      | CLK_STATE_READY     | 19200000        |
    |    90     |     3    | DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK16  | CLK_STATE_READY     | 62500000        |
    |    90     |     4    | DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY     | 12500000        |
    |    90     |     5    | DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK             | CLK_STATE_READY     | 200000000       |
    |    90     |     6    | DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                  | CLK_STATE_READY     | 0               |
    |    90     |     7    | DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                      | CLK_STATE_READY     | 32768           |
    |    90     |     8    | DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0                  | CLK_STATE_READY     | 0               |
    |    90     |     9    | DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK   | CLK_STATE_READY     | 32000           |
    |    90     |    10    | DEV_MCU_TIMER8_TIMER_HCLK_CLK                                                     | CLK_STATE_READY     | 166666666       |
    |    91     |     1    | DEV_MCU_TIMER9_TIMER_TCLK_CLK                                                     | CLK_STATE_READY     | 62500000        |
    |    91     |     2    | DEV_MCU_TIMER9_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT9                        | CLK_STATE_READY     | 62500000        |
    |    91     |     3    | DEV_MCU_TIMER9_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_8_TIMER_PWM               | CLK_STATE_READY     | 0               |
    |    91     |    10    | DEV_MCU_TIMER9_TIMER_HCLK_CLK                                                     | CLK_STATE_READY     | 166666666       |
    |   149     |     2    | DEV_MCU_UART0_VBUSP_CLK                                                           | CLK_STATE_READY     | 166666666       |
    |   149     |     3    | DEV_MCU_UART0_FCLK_CLK                                                            | CLK_STATE_READY     | 96000000        |
    |   149     |     4    | DEV_MCU_UART0_FCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT3_CLK                    | CLK_STATE_READY     | 96000000        |
    |   149     |     5    | DEV_MCU_UART0_FCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_1_HSDIVOUT5_CLK                 | CLK_STATE_READY     | 192000000       |
    |    98     |     1    | DEV_MMCSD0_EMMCSS_XIN_CLK                                                         | CLK_STATE_READY     | 200000000       |
    |    98     |     2    | DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT2_CLK                | CLK_STATE_READY     | 200000000       |
    |    98     |     3    | DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT2_CLK                | CLK_STATE_READY     | 192000000       |
    |    98     |     4    | DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK                | CLK_STATE_READY     | 200000000       |
    |    98     |     5    | DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT2_CLK                | CLK_STATE_READY     | 200000000       |
    |    98     |     7    | DEV_MMCSD0_EMMCSS_VBUS_CLK                                                        | CLK_STATE_READY     | 250000000       |
    |    99     |     1    | DEV_MMCSD1_EMMCSDSS_XIN_CLK                                                       | CLK_STATE_READY     | 200000000       |
    |    99     |     2    | DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT2_CLK              | CLK_STATE_READY     | 200000000       |
    |    99     |     3    | DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT2_CLK              | CLK_STATE_READY     | 192000000       |
    |    99     |     4    | DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK              | CLK_STATE_READY     | 200000000       |
    |    99     |     5    | DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT2_CLK              | CLK_STATE_READY     | 200000000       |
    |    99     |     6    | DEV_MMCSD1_EMMCSDSS_IO_CLK_O                                                      | CLK_STATE_READY     | 0               |
    |    99     |     7    | DEV_MMCSD1_EMMCSDSS_IO_CLK_I                                                      | CLK_STATE_READY     | 0               |
    |    99     |     8    | DEV_MMCSD1_EMMCSDSS_VBUS_CLK                                                      | CLK_STATE_READY     | 250000000       |
    |   224     |     0    | DEV_NAVSS0_CPTS0_GENF2                                                            | CLK_STATE_READY     | 0               |
    |   224     |     1    | DEV_NAVSS0_CPTS0_GENF3                                                            | CLK_STATE_READY     | 0               |
    |   225     |     0    | DEV_NAVSS0_BCDMA_0_CLK                                                            | CLK_STATE_READY     | 500000000       |
    |   226     |     0    | DEV_NAVSS0_CPTS_0_TS_GENF0                                                        | CLK_STATE_READY     | 0               |
    |   226     |     2    | DEV_NAVSS0_CPTS_0_TS_GENF1                                                        | CLK_STATE_READY     | 0               |
    |   226     |     4    | DEV_NAVSS0_CPTS_0_VBUSP_GCLK                                                      | CLK_STATE_READY     | 500000000       |
    |   226     |     5    | DEV_NAVSS0_CPTS_0_RCLK                                                            | CLK_STATE_READY     | 200000000       |
    |   226     |     6    | DEV_NAVSS0_CPTS_0_RCLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK                   | CLK_STATE_READY     | 250000000       |
    |   226     |     7    | DEV_NAVSS0_CPTS_0_RCLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK                 | CLK_STATE_READY     | 200000000       |
    |   226     |     8    | DEV_NAVSS0_CPTS_0_RCLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT                       | CLK_STATE_READY     | 0               |
    |   226     |     9    | DEV_NAVSS0_CPTS_0_RCLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT                           | CLK_STATE_READY     | 0               |
    |   226     |    10    | DEV_NAVSS0_CPTS_0_RCLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                         | CLK_STATE_READY     | 0               |
    |   226     |    11    | DEV_NAVSS0_CPTS_0_RCLK_PARENT_BOARD_0_EXT_REFCLK1_OUT                             | CLK_STATE_READY     | 0               |
    |   226     |    12    | DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN0_TXMCLK                  | CLK_STATE_READY     | 0               |
    |   226     |    13    | DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN1_TXMCLK                  | CLK_STATE_READY     | 0               |
    |   226     |    14    | DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN2_TXMCLK                  | CLK_STATE_READY     | 0               |
    |   226     |    15    | DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN3_TXMCLK                  | CLK_STATE_READY     | 0               |
    |   226     |    20    | DEV_NAVSS0_CPTS_0_RCLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK                    | CLK_STATE_READY     | 500000000       |
    |   226     |    21    | DEV_NAVSS0_CPTS_0_RCLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK           | CLK_STATE_READY     | 500000000       |
    |   227     |     0    | DEV_NAVSS0_INTR_0_INTR_CLK                                                        | CLK_STATE_READY     | 500000000       |
    |   228     |     0    | DEV_NAVSS0_MAILBOX1_0_VCLK_CLK                                                    | CLK_STATE_READY     | 500000000       |
    |   229     |     0    | DEV_NAVSS0_MAILBOX1_1_VCLK_CLK                                                    | CLK_STATE_READY     | 500000000       |
    |   238     |     0    | DEV_NAVSS0_MAILBOX1_10_VCLK_CLK                                                   | CLK_STATE_READY     | 500000000       |
    |   239     |     0    | DEV_NAVSS0_MAILBOX1_11_VCLK_CLK                                                   | CLK_STATE_READY     | 500000000       |
    |   230     |     0    | DEV_NAVSS0_MAILBOX1_2_VCLK_CLK                                                    | CLK_STATE_READY     | 500000000       |
    |   231     |     0    | DEV_NAVSS0_MAILBOX1_3_VCLK_CLK                                                    | CLK_STATE_READY     | 500000000       |
    |   232     |     0    | DEV_NAVSS0_MAILBOX1_4_VCLK_CLK                                                    | CLK_STATE_READY     | 500000000       |
    |   233     |     0    | DEV_NAVSS0_MAILBOX1_5_VCLK_CLK                                                    | CLK_STATE_READY     | 500000000       |
    |   234     |     0    | DEV_NAVSS0_MAILBOX1_6_VCLK_CLK                                                    | CLK_STATE_READY     | 500000000       |
    |   235     |     0    | DEV_NAVSS0_MAILBOX1_7_VCLK_CLK                                                    | CLK_STATE_READY     | 500000000       |
    |   236     |     0    | DEV_NAVSS0_MAILBOX1_8_VCLK_CLK                                                    | CLK_STATE_READY     | 500000000       |
    |   237     |     0    | DEV_NAVSS0_MAILBOX1_9_VCLK_CLK                                                    | CLK_STATE_READY     | 500000000       |
    |   240     |     0    | DEV_NAVSS0_MAILBOX_0_VCLK_CLK                                                     | CLK_STATE_READY     | 500000000       |
    |   241     |     0    | DEV_NAVSS0_MAILBOX_1_VCLK_CLK                                                     | CLK_STATE_READY     | 500000000       |
    |   250     |     0    | DEV_NAVSS0_MAILBOX_10_VCLK_CLK                                                    | CLK_STATE_READY     | 500000000       |
    |   251     |     0    | DEV_NAVSS0_MAILBOX_11_VCLK_CLK                                                    | CLK_STATE_READY     | 500000000       |
    |   242     |     0    | DEV_NAVSS0_MAILBOX_2_VCLK_CLK                                                     | CLK_STATE_READY     | 500000000       |
    |   243     |     0    | DEV_NAVSS0_MAILBOX_3_VCLK_CLK                                                     | CLK_STATE_READY     | 500000000       |
    |   244     |     0    | DEV_NAVSS0_MAILBOX_4_VCLK_CLK                                                     | CLK_STATE_READY     | 500000000       |
    |   245     |     0    | DEV_NAVSS0_MAILBOX_5_VCLK_CLK                                                     | CLK_STATE_READY     | 500000000       |
    |   246     |     0    | DEV_NAVSS0_MAILBOX_6_VCLK_CLK                                                     | CLK_STATE_READY     | 500000000       |
    |   247     |     0    | DEV_NAVSS0_MAILBOX_7_VCLK_CLK                                                     | CLK_STATE_READY     | 500000000       |
    |   248     |     0    | DEV_NAVSS0_MAILBOX_8_VCLK_CLK                                                     | CLK_STATE_READY     | 500000000       |
    |   249     |     0    | DEV_NAVSS0_MAILBOX_9_VCLK_CLK                                                     | CLK_STATE_READY     | 500000000       |
    |   252     |     0    | DEV_NAVSS0_MCRC_0_CLK                                                             | CLK_STATE_READY     | 500000000       |
    |   253     |     0    | DEV_NAVSS0_MODSS_VD2CLK                                                           | CLK_STATE_READY     | 500000000       |
    |   254     |     0    | DEV_NAVSS0_MODSS_INTA_0_SYS_CLK                                                   | CLK_STATE_READY     | 500000000       |
    |   255     |     0    | DEV_NAVSS0_MODSS_INTA_1_SYS_CLK                                                   | CLK_STATE_READY     | 500000000       |
    |   256     |     0    | DEV_NAVSS0_PROXY_0_CLK_CLK                                                        | CLK_STATE_READY     | 500000000       |
    |   257     |     0    | DEV_NAVSS0_PVU_0_CLK_CLK                                                          | CLK_STATE_READY     | 500000000       |
    |   258     |     0    | DEV_NAVSS0_PVU_1_CLK_CLK                                                          | CLK_STATE_READY     | 500000000       |
    |   259     |     0    | DEV_NAVSS0_RINGACC_0_SYS_CLK                                                      | CLK_STATE_READY     | 500000000       |
    |   260     |     0    | DEV_NAVSS0_SPINLOCK_0_CLK                                                         | CLK_STATE_READY     | 500000000       |
    |   261     |     0    | DEV_NAVSS0_TIMERMGR_0_EON_TICK_EVT                                                | CLK_STATE_READY     | 0               |
    |   261     |     1    | DEV_NAVSS0_TIMERMGR_0_VCLK_CLK                                                    | CLK_STATE_READY     | 500000000       |
    |   262     |     0    | DEV_NAVSS0_TIMERMGR_1_EON_TICK_EVT                                                | CLK_STATE_READY     | 0               |
    |   262     |     1    | DEV_NAVSS0_TIMERMGR_1_VCLK_CLK                                                    | CLK_STATE_READY     | 500000000       |
    |   263     |     0    | DEV_NAVSS0_UDMAP_0_SYS_CLK                                                        | CLK_STATE_READY     | 500000000       |
    |   264     |     0    | DEV_NAVSS0_UDMASS_VD2CLK                                                          | CLK_STATE_READY     | 500000000       |
    |   265     |     0    | DEV_NAVSS0_UDMASS_INTA_0_SYS_CLK                                                  | CLK_STATE_READY     | 500000000       |
    |   266     |     0    | DEV_NAVSS0_VIRTSS_VD2CLK                                                          | CLK_STATE_READY     | 500000000       |
    |   171     |     1    | DEV_PBIST0_CLK8_CLK                                                               | CLK_STATE_READY     | 125000000       |
    |   172     |     1    | DEV_PBIST1_CLK8_CLK                                                               | CLK_STATE_READY     | 125000000       |
    |   175     |     1    | DEV_PBIST10_CLK8_CLK                                                              | CLK_STATE_READY     | 125000000       |
    |   168     |     4    | DEV_PBIST11_CLK7_CLK                                                              | CLK_STATE_READY     | 125000000       |
    |   174     |     1    | DEV_PBIST2_CLK8_CLK                                                               | CLK_STATE_READY     | 125000000       |
    |   170     |     1    | DEV_PBIST3_CLK8_CLK                                                               | CLK_STATE_READY     | 125000000       |
    |   173     |     1    | DEV_PBIST4_CLK8_CLK                                                               | CLK_STATE_READY     | 125000000       |
    |   167     |     1    | DEV_PBIST5_CLK8_CLK                                                               | CLK_STATE_READY     | 125000000       |
    |   276     |     0    | DEV_PCIE1_PCIE_LANE0_TXMCLK                                                       | CLK_STATE_READY     | 0               |
    |   276     |     1    | DEV_PCIE1_PCIE_LANE0_TXFCLK                                                       | CLK_STATE_READY     | 0               |
    |   276     |     2    | DEV_PCIE1_PCIE_LANE0_RXFCLK                                                       | CLK_STATE_READY     | 0               |
    |   276     |     3    | DEV_PCIE1_PCIE_LANE0_TXCLK                                                        | CLK_STATE_READY     | 0               |
    |   276     |     4    | DEV_PCIE1_PCIE_LANE3_RXFCLK                                                       | CLK_STATE_READY     | 0               |
    |   276     |     5    | DEV_PCIE1_PCIE_LANE3_RXCLK                                                        | CLK_STATE_READY     | 0               |
    |   276     |     6    | DEV_PCIE1_PCIE_LANE2_RXFCLK                                                       | CLK_STATE_READY     | 0               |
    |   276     |     7    | DEV_PCIE1_PCIE_LANE1_TXCLK                                                        | CLK_STATE_READY     | 0               |
    |   276     |     8    | DEV_PCIE1_PCIE_CPTS_RCLK_CLK                                                      | CLK_STATE_READY     | 250000000       |
    |   276     |     9    | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK             | CLK_STATE_READY     | 250000000       |
    |   276     |    10    | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK           | CLK_STATE_READY     | 200000000       |
    |   276     |    11    | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT                 | CLK_STATE_READY     | 0               |
    |   276     |    12    | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT                     | CLK_STATE_READY     | 0               |
    |   276     |    13    | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                   | CLK_STATE_READY     | 0               |
    |   276     |    14    | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT                       | CLK_STATE_READY     | 0               |
    |   276     |    15    | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN0_TXMCLK            | CLK_STATE_READY     | 0               |
    |   276     |    16    | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN1_TXMCLK            | CLK_STATE_READY     | 0               |
    |   276     |    17    | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN2_TXMCLK            | CLK_STATE_READY     | 0               |
    |   276     |    18    | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN3_TXMCLK            | CLK_STATE_READY     | 0               |
    |   276     |    23    | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK              | CLK_STATE_READY     | 500000000       |
    |   276     |    24    | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK     | CLK_STATE_READY     | 500000000       |
    |   276     |    26    | DEV_PCIE1_PCIE_LANE3_TXMCLK                                                       | CLK_STATE_READY     | 0               |
    |   276     |    27    | DEV_PCIE1_PCIE_LANE2_RXCLK                                                        | CLK_STATE_READY     | 0               |
    |   276     |    28    | DEV_PCIE1_PCIE_LANE1_RXFCLK                                                       | CLK_STATE_READY     | 0               |
    |   276     |    29    | DEV_PCIE1_PCIE_LANE0_RXCLK                                                        | CLK_STATE_READY     | 0               |
    |   276     |    30    | DEV_PCIE1_PCIE_LANE2_REFCLK                                                       | CLK_STATE_READY     | 0               |
    |   276     |    31    | DEV_PCIE1_PCIE_LANE3_REFCLK                                                       | CLK_STATE_READY     | 0               |
    |   276     |    32    | DEV_PCIE1_PCIE_LANE2_TXMCLK                                                       | CLK_STATE_READY     | 0               |
    |   276     |    33    | DEV_PCIE1_PCIE_LANE1_REFCLK                                                       | CLK_STATE_READY     | 0               |
    |   276     |    34    | DEV_PCIE1_PCIE_LANE2_TXFCLK                                                       | CLK_STATE_READY     | 0               |
    |   276     |    35    | DEV_PCIE1_PCIE_PM_CLK                                                             | CLK_STATE_READY     | 12500000        |
    |   276     |    36    | DEV_PCIE1_PCIE_LANE1_TXFCLK                                                       | CLK_STATE_READY     | 0               |
    |   276     |    37    | DEV_PCIE1_PCIE_LANE1_TXMCLK                                                       | CLK_STATE_READY     | 0               |
    |   276     |    38    | DEV_PCIE1_PCIE_LANE0_REFCLK                                                       | CLK_STATE_READY     | 0               |
    |   276     |    39    | DEV_PCIE1_PCIE_LANE1_RXCLK                                                        | CLK_STATE_READY     | 0               |
    |   276     |    40    | DEV_PCIE1_PCIE_LANE3_TXFCLK                                                       | CLK_STATE_READY     | 0               |
    |   276     |    41    | DEV_PCIE1_PCIE_CBA_CLK                                                            | CLK_STATE_READY     | 250000000       |
    |   276     |    42    | DEV_PCIE1_PCIE_LANE2_TXCLK                                                        | CLK_STATE_READY     | 0               |
    |   276     |    43    | DEV_PCIE1_PCIE_LANE3_TXCLK                                                        | CLK_STATE_READY     | 0               |
    |   143     |     0    | DEV_PSC0_SLOW_CLK                                                                 | CLK_STATE_READY     | 20833333        |
    |   143     |     1    | DEV_PSC0_CLK                                                                      | CLK_STATE_READY     | 125000000       |
    |   279     |     0    | DEV_R5FSS0_CORE0_CPU_CLK                                                          | CLK_STATE_READY     | 1000000000      |
    |   279     |     1    | DEV_R5FSS0_CORE0_INTERFACE_CLK                                                    | CLK_STATE_READY     | 1000000000      |
    |   280     |     0    | DEV_R5FSS0_CORE1_CPU_CLK                                                          | CLK_STATE_READY     | 1000000000      |
    |   280     |     1    | DEV_R5FSS0_CORE1_INTERFACE_CLK                                                    | CLK_STATE_READY     | 1000000000      |
    |   281     |     0    | DEV_R5FSS1_CORE0_CPU_CLK                                                          | CLK_STATE_READY     | 1000000000      |
    |   281     |     1    | DEV_R5FSS1_CORE0_INTERFACE_CLK                                                    | CLK_STATE_READY     | 1000000000      |
    |   282     |     0    | DEV_R5FSS1_CORE1_CPU_CLK                                                          | CLK_STATE_READY     | 1000000000      |
    |   282     |     1    | DEV_R5FSS1_CORE1_INTERFACE_CLK                                                    | CLK_STATE_READY     | 1000000000      |
    |   286     |     0    | DEV_RTI0_VBUSP_CLK                                                                | CLK_STATE_READY     | 125000000       |
    |   286     |     1    | DEV_RTI0_RTI_CLK                                                                  | CLK_STATE_READY     | 32000           |
    |   286     |     2    | DEV_RTI0_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                                   | CLK_STATE_READY     | 19200000        |
    |   286     |     3    | DEV_RTI0_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                                   | CLK_STATE_READY     | 32768           |
    |   286     |     4    | DEV_RTI0_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK              | CLK_STATE_READY     | 12500000        |
    |   286     |     5    | DEV_RTI0_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK                | CLK_STATE_READY     | 32000           |
    |   286     |     6    | DEV_RTI0_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                                    | CLK_STATE_READY     | 0               |
    |   286     |     7    | DEV_RTI0_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0                               | CLK_STATE_READY     | 0               |
    |   286     |     8    | DEV_RTI0_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1                               | CLK_STATE_READY     | 0               |
    |   286     |     9    | DEV_RTI0_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2                               | CLK_STATE_READY     | 0               |
    |   287     |     0    | DEV_RTI1_VBUSP_CLK                                                                | CLK_STATE_READY     | 125000000       |
    |   287     |     1    | DEV_RTI1_RTI_CLK                                                                  | CLK_STATE_READY     | 32000           |
    |   287     |     2    | DEV_RTI1_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                                   | CLK_STATE_READY     | 19200000        |
    |   287     |     3    | DEV_RTI1_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                                   | CLK_STATE_READY     | 32768           |
    |   287     |     4    | DEV_RTI1_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK              | CLK_STATE_READY     | 12500000        |
    |   287     |     5    | DEV_RTI1_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK                | CLK_STATE_READY     | 32000           |
    |   287     |     6    | DEV_RTI1_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                                    | CLK_STATE_READY     | 0               |
    |   287     |     7    | DEV_RTI1_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0                               | CLK_STATE_READY     | 0               |
    |   287     |     8    | DEV_RTI1_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1                               | CLK_STATE_READY     | 0               |
    |   287     |     9    | DEV_RTI1_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2                               | CLK_STATE_READY     | 0               |
    |   290     |     0    | DEV_RTI15_VBUSP_CLK                                                               | CLK_STATE_READY     | 125000000       |
    |   290     |     1    | DEV_RTI15_RTI_CLK                                                                 | CLK_STATE_READY     | 19200000        |
    |   290     |     2    | DEV_RTI15_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                                  | CLK_STATE_READY     | 19200000        |
    |   290     |     3    | DEV_RTI15_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                                  | CLK_STATE_READY     | 32768           |
    |   290     |     4    | DEV_RTI15_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK             | CLK_STATE_READY     | 12500000        |
    |   290     |     5    | DEV_RTI15_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK               | CLK_STATE_READY     | 32000           |
    |   290     |     6    | DEV_RTI15_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                                   | CLK_STATE_READY     | 0               |
    |   290     |     7    | DEV_RTI15_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0                              | CLK_STATE_READY     | 0               |
    |   290     |     8    | DEV_RTI15_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1                              | CLK_STATE_READY     | 0               |
    |   290     |     9    | DEV_RTI15_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2                              | CLK_STATE_READY     | 0               |
    |   288     |     0    | DEV_RTI16_VBUSP_CLK                                                               | CLK_STATE_READY     | 125000000       |
    |   288     |     1    | DEV_RTI16_RTI_CLK                                                                 | CLK_STATE_READY     | 19200000        |
    |   288     |     2    | DEV_RTI16_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                                  | CLK_STATE_READY     | 19200000        |
    |   288     |     3    | DEV_RTI16_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                                  | CLK_STATE_READY     | 32768           |
    |   288     |     4    | DEV_RTI16_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK             | CLK_STATE_READY     | 12500000        |
    |   288     |     5    | DEV_RTI16_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK               | CLK_STATE_READY     | 32000           |
    |   288     |     6    | DEV_RTI16_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                                   | CLK_STATE_READY     | 0               |
    |   288     |     7    | DEV_RTI16_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0                              | CLK_STATE_READY     | 0               |
    |   288     |     8    | DEV_RTI16_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1                              | CLK_STATE_READY     | 0               |
    |   288     |     9    | DEV_RTI16_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2                              | CLK_STATE_READY     | 0               |
    |   289     |     0    | DEV_RTI17_VBUSP_CLK                                                               | CLK_STATE_READY     | 125000000       |
    |   289     |     1    | DEV_RTI17_RTI_CLK                                                                 | CLK_STATE_READY     | 19200000        |
    |   289     |     2    | DEV_RTI17_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                                  | CLK_STATE_READY     | 19200000        |
    |   289     |     3    | DEV_RTI17_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                                  | CLK_STATE_READY     | 32768           |
    |   289     |     4    | DEV_RTI17_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK             | CLK_STATE_READY     | 12500000        |
    |   289     |     5    | DEV_RTI17_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK               | CLK_STATE_READY     | 32000           |
    |   289     |     6    | DEV_RTI17_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                                   | CLK_STATE_READY     | 0               |
    |   289     |     7    | DEV_RTI17_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0                              | CLK_STATE_READY     | 0               |
    |   289     |     8    | DEV_RTI17_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1                              | CLK_STATE_READY     | 0               |
    |   289     |     9    | DEV_RTI17_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2                              | CLK_STATE_READY     | 0               |
    |   291     |     0    | DEV_RTI28_VBUSP_CLK                                                               | CLK_STATE_READY     | 125000000       |
    |   291     |     1    | DEV_RTI28_RTI_CLK                                                                 | CLK_STATE_READY     | 19200000        |
    |   291     |     2    | DEV_RTI28_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                                  | CLK_STATE_READY     | 19200000        |
    |   291     |     3    | DEV_RTI28_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                                  | CLK_STATE_READY     | 32768           |
    |   291     |     4    | DEV_RTI28_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK             | CLK_STATE_READY     | 12500000        |
    |   291     |     5    | DEV_RTI28_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK               | CLK_STATE_READY     | 32000           |
    |   291     |     6    | DEV_RTI28_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                                   | CLK_STATE_READY     | 0               |
    |   291     |     7    | DEV_RTI28_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0                              | CLK_STATE_READY     | 0               |
    |   291     |     8    | DEV_RTI28_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1                              | CLK_STATE_READY     | 0               |
    |   291     |     9    | DEV_RTI28_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2                              | CLK_STATE_READY     | 0               |
    |   292     |     0    | DEV_RTI29_VBUSP_CLK                                                               | CLK_STATE_READY     | 125000000       |
    |   292     |     1    | DEV_RTI29_RTI_CLK                                                                 | CLK_STATE_READY     | 19200000        |
    |   292     |     2    | DEV_RTI29_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                                  | CLK_STATE_READY     | 19200000        |
    |   292     |     3    | DEV_RTI29_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                                  | CLK_STATE_READY     | 32768           |
    |   292     |     4    | DEV_RTI29_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK             | CLK_STATE_READY     | 12500000        |
    |   292     |     5    | DEV_RTI29_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK               | CLK_STATE_READY     | 32000           |
    |   292     |     6    | DEV_RTI29_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                                   | CLK_STATE_READY     | 0               |
    |   292     |     7    | DEV_RTI29_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0                              | CLK_STATE_READY     | 0               |
    |   292     |     8    | DEV_RTI29_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1                              | CLK_STATE_READY     | 0               |
    |   292     |     9    | DEV_RTI29_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2                              | CLK_STATE_READY     | 0               |
    |   293     |     0    | DEV_RTI30_VBUSP_CLK                                                               | CLK_STATE_READY     | 125000000       |
    |   293     |     1    | DEV_RTI30_RTI_CLK                                                                 | CLK_STATE_READY     | 19200000        |
    |   293     |     2    | DEV_RTI30_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                                  | CLK_STATE_READY     | 19200000        |
    |   293     |     3    | DEV_RTI30_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                                  | CLK_STATE_READY     | 32768           |
    |   293     |     4    | DEV_RTI30_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK             | CLK_STATE_READY     | 12500000        |
    |   293     |     5    | DEV_RTI30_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK               | CLK_STATE_READY     | 32000           |
    |   293     |     6    | DEV_RTI30_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                                   | CLK_STATE_READY     | 0               |
    |   293     |     7    | DEV_RTI30_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0                              | CLK_STATE_READY     | 0               |
    |   293     |     8    | DEV_RTI30_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1                              | CLK_STATE_READY     | 0               |
    |   293     |     9    | DEV_RTI30_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2                              | CLK_STATE_READY     | 0               |
    |   294     |     0    | DEV_RTI31_VBUSP_CLK                                                               | CLK_STATE_READY     | 125000000       |
    |   294     |     1    | DEV_RTI31_RTI_CLK                                                                 | CLK_STATE_READY     | 19200000        |
    |   294     |     2    | DEV_RTI31_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                                  | CLK_STATE_READY     | 19200000        |
    |   294     |     3    | DEV_RTI31_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                                  | CLK_STATE_READY     | 32768           |
    |   294     |     4    | DEV_RTI31_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK             | CLK_STATE_READY     | 12500000        |
    |   294     |     5    | DEV_RTI31_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK               | CLK_STATE_READY     | 32000           |
    |   294     |     6    | DEV_RTI31_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                                   | CLK_STATE_READY     | 0               |
    |   294     |     7    | DEV_RTI31_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0                              | CLK_STATE_READY     | 0               |
    |   294     |     8    | DEV_RTI31_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1                              | CLK_STATE_READY     | 0               |
    |   294     |     9    | DEV_RTI31_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2                              | CLK_STATE_READY     | 0               |
    |   145     |     0    | DEV_SA2_CPSW_PSILSS0_MAIN_CLK                                                     | CLK_STATE_READY     | 500000000       |
    |   145     |     1    | DEV_SA2_CPSW_PSILSS0_MAIN_2_CLK                                                   | CLK_STATE_READY     | 250000000       |
    |   297     |     0    | DEV_SA2_UL0_PKA_IN_CLK                                                            | CLK_STATE_READY     | 400000000       |
    |   297     |     1    | DEV_SA2_UL0_X1_CLK                                                                | CLK_STATE_READY     | 125000000       |
    |   297     |     2    | DEV_SA2_UL0_X2_CLK                                                                | CLK_STATE_READY     | 250000000       |
    |   365     |     0    | DEV_SERDES_10G0_CLK                                                               | CLK_STATE_READY     | 125000000       |
    |   365     |     1    | DEV_SERDES_10G0_CMN_REFCLK_M                                                      | CLK_STATE_READY     | 0               |
    |   365     |     1    | DEV_SERDES_10G0_CMN_REFCLK_M                                                      | CLK_STATE_READY     | 0               |
    |   365     |     2    | DEV_SERDES_10G0_CMN_REFCLK_P                                                      | CLK_STATE_READY     | 0               |
    |   365     |     2    | DEV_SERDES_10G0_CMN_REFCLK_P                                                      | CLK_STATE_READY     | 0               |
    |   365     |     3    | DEV_SERDES_10G0_CORE_REF_CLK                                                      | CLK_STATE_READY     | 100000000       |
    |   365     |     4    | DEV_SERDES_10G0_CORE_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                       | CLK_STATE_READY     | 19200000        |
    |   365     |     5    | DEV_SERDES_10G0_CORE_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                        | CLK_STATE_READY     | 0               |
    |   365     |     6    | DEV_SERDES_10G0_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK             | CLK_STATE_READY     | 125000000       |
    |   365     |     7    | DEV_SERDES_10G0_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK             | CLK_STATE_READY     | 100000000       |
    |   365     |     9    | DEV_SERDES_10G0_IP1_LN0_REFCLK                                                    | CLK_STATE_READY     | 0               |
    |   365     |    10    | DEV_SERDES_10G0_IP1_LN0_RXCLK                                                     | CLK_STATE_READY     | 0               |
    |   365     |    11    | DEV_SERDES_10G0_IP1_LN0_RXFCLK                                                    | CLK_STATE_READY     | 0               |
    |   365     |    12    | DEV_SERDES_10G0_IP1_LN0_TXCLK                                                     | CLK_STATE_NOT_READY | 0               |
    |   365     |    13    | DEV_SERDES_10G0_IP1_LN0_TXFCLK                                                    | CLK_STATE_READY     | 0               |
    |   365     |    14    | DEV_SERDES_10G0_IP1_LN0_TXMCLK                                                    | CLK_STATE_READY     | 0               |
    |   365     |    15    | DEV_SERDES_10G0_IP1_LN1_REFCLK                                                    | CLK_STATE_READY     | 0               |
    |   365     |    16    | DEV_SERDES_10G0_IP1_LN1_RXCLK                                                     | CLK_STATE_READY     | 0               |
    |   365     |    17    | DEV_SERDES_10G0_IP1_LN1_RXFCLK                                                    | CLK_STATE_READY     | 0               |
    |   365     |    18    | DEV_SERDES_10G0_IP1_LN1_TXCLK                                                     | CLK_STATE_NOT_READY | 0               |
    |   365     |    19    | DEV_SERDES_10G0_IP1_LN1_TXFCLK                                                    | CLK_STATE_READY     | 0               |
    |   365     |    20    | DEV_SERDES_10G0_IP1_LN1_TXMCLK                                                    | CLK_STATE_READY     | 0               |
    |   365     |    21    | DEV_SERDES_10G0_IP1_LN2_REFCLK                                                    | CLK_STATE_READY     | 0               |
    |   365     |    22    | DEV_SERDES_10G0_IP1_LN2_RXCLK                                                     | CLK_STATE_READY     | 0               |
    |   365     |    23    | DEV_SERDES_10G0_IP1_LN2_RXFCLK                                                    | CLK_STATE_READY     | 0               |
    |   365     |    24    | DEV_SERDES_10G0_IP1_LN2_TXCLK                                                     | CLK_STATE_NOT_READY | 0               |
    |   365     |    25    | DEV_SERDES_10G0_IP1_LN2_TXCLK_PARENT_K3_DSS_EDP_MAIN_0_PHY_LN2_TXCLK              | CLK_STATE_NOT_READY | 0               |
    |   365     |    26    | DEV_SERDES_10G0_IP1_LN2_TXCLK_PARENT_K3_DSS_EDP_MAIN_0_PHY_LN0_TXCLK              | CLK_STATE_NOT_READY | 0               |
    |   365     |    27    | DEV_SERDES_10G0_IP1_LN2_TXFCLK                                                    | CLK_STATE_READY     | 0               |
    |   365     |    28    | DEV_SERDES_10G0_IP1_LN2_TXMCLK                                                    | CLK_STATE_READY     | 0               |
    |   365     |    29    | DEV_SERDES_10G0_IP1_LN3_REFCLK                                                    | CLK_STATE_READY     | 0               |
    |   365     |    30    | DEV_SERDES_10G0_IP1_LN3_RXCLK                                                     | CLK_STATE_READY     | 0               |
    |   365     |    31    | DEV_SERDES_10G0_IP1_LN3_RXFCLK                                                    | CLK_STATE_READY     | 0               |
    |   365     |    32    | DEV_SERDES_10G0_IP1_LN3_TXCLK                                                     | CLK_STATE_NOT_READY | 0               |
    |   365     |    33    | DEV_SERDES_10G0_IP1_LN3_TXCLK_PARENT_K3_DSS_EDP_MAIN_0_PHY_LN3_TXCLK              | CLK_STATE_NOT_READY | 0               |
    |   365     |    34    | DEV_SERDES_10G0_IP1_LN3_TXCLK_PARENT_K3_DSS_EDP_MAIN_0_PHY_LN1_TXCLK              | CLK_STATE_NOT_READY | 0               |
    |   365     |    35    | DEV_SERDES_10G0_IP1_LN3_TXFCLK                                                    | CLK_STATE_READY     | 0               |
    |   365     |    36    | DEV_SERDES_10G0_IP1_LN3_TXMCLK                                                    | CLK_STATE_READY     | 0               |
    |   365     |    37    | DEV_SERDES_10G0_IP2_LN0_REFCLK                                                    | CLK_STATE_READY     | 0               |
    |   365     |    38    | DEV_SERDES_10G0_IP2_LN0_RXCLK                                                     | CLK_STATE_READY     | 0               |
    |   365     |    39    | DEV_SERDES_10G0_IP2_LN0_RXFCLK                                                    | CLK_STATE_READY     | 0               |
    |   365     |    40    | DEV_SERDES_10G0_IP2_LN0_TXCLK                                                     | CLK_STATE_NOT_READY | 0               |
    |   365     |    41    | DEV_SERDES_10G0_IP2_LN0_TXFCLK                                                    | CLK_STATE_READY     | 0               |
    |   365     |    42    | DEV_SERDES_10G0_IP2_LN0_TXMCLK                                                    | CLK_STATE_READY     | 0               |
    |   365     |    43    | DEV_SERDES_10G0_IP2_LN1_REFCLK                                                    | CLK_STATE_READY     | 0               |
    |   365     |    44    | DEV_SERDES_10G0_IP2_LN1_RXCLK                                                     | CLK_STATE_READY     | 0               |
    |   365     |    45    | DEV_SERDES_10G0_IP2_LN1_RXFCLK                                                    | CLK_STATE_READY     | 0               |
    |   365     |    46    | DEV_SERDES_10G0_IP2_LN1_TXCLK                                                     | CLK_STATE_NOT_READY | 0               |
    |   365     |    47    | DEV_SERDES_10G0_IP2_LN1_TXFCLK                                                    | CLK_STATE_READY     | 0               |
    |   365     |    48    | DEV_SERDES_10G0_IP2_LN1_TXMCLK                                                    | CLK_STATE_READY     | 0               |
    |   365     |    49    | DEV_SERDES_10G0_IP2_LN2_REFCLK                                                    | CLK_STATE_READY     | 0               |
    |   365     |    50    | DEV_SERDES_10G0_IP2_LN2_RXCLK                                                     | CLK_STATE_READY     | 0               |
    |   365     |    51    | DEV_SERDES_10G0_IP2_LN2_RXFCLK                                                    | CLK_STATE_READY     | 0               |
    |   365     |    52    | DEV_SERDES_10G0_IP2_LN2_TXCLK                                                     | CLK_STATE_NOT_READY | 0               |
    |   365     |    53    | DEV_SERDES_10G0_IP2_LN2_TXFCLK                                                    | CLK_STATE_READY     | 0               |
    |   365     |    54    | DEV_SERDES_10G0_IP2_LN2_TXMCLK                                                    | CLK_STATE_READY     | 0               |
    |   365     |    55    | DEV_SERDES_10G0_IP2_LN3_REFCLK                                                    | CLK_STATE_READY     | 0               |
    |   365     |    56    | DEV_SERDES_10G0_IP2_LN3_RXCLK                                                     | CLK_STATE_READY     | 0               |
    |   365     |    57    | DEV_SERDES_10G0_IP2_LN3_RXFCLK                                                    | CLK_STATE_READY     | 0               |
    |   365     |    58    | DEV_SERDES_10G0_IP2_LN3_TXCLK                                                     | CLK_STATE_NOT_READY | 0               |
    |   365     |    59    | DEV_SERDES_10G0_IP2_LN3_TXFCLK                                                    | CLK_STATE_READY     | 0               |
    |   365     |    60    | DEV_SERDES_10G0_IP2_LN3_TXMCLK                                                    | CLK_STATE_READY     | 0               |
    |   365     |    67    | DEV_SERDES_10G0_IP3_LN1_REFCLK                                                    | CLK_STATE_READY     | 0               |
    |   365     |    68    | DEV_SERDES_10G0_IP3_LN1_RXCLK                                                     | CLK_STATE_READY     | 0               |
    |   365     |    69    | DEV_SERDES_10G0_IP3_LN1_RXFCLK                                                    | CLK_STATE_READY     | 0               |
    |   365     |    70    | DEV_SERDES_10G0_IP3_LN1_TXCLK                                                     | CLK_STATE_READY     | 0               |
    |   365     |    71    | DEV_SERDES_10G0_IP3_LN1_TXFCLK                                                    | CLK_STATE_READY     | 0               |
    |   365     |    72    | DEV_SERDES_10G0_IP3_LN1_TXMCLK                                                    | CLK_STATE_READY     | 0               |
    |   365     |    79    | DEV_SERDES_10G0_IP3_LN3_REFCLK                                                    | CLK_STATE_READY     | 0               |
    |   365     |    80    | DEV_SERDES_10G0_IP3_LN3_RXCLK                                                     | CLK_STATE_READY     | 0               |
    |   365     |    81    | DEV_SERDES_10G0_IP3_LN3_RXFCLK                                                    | CLK_STATE_READY     | 0               |
    |   365     |    82    | DEV_SERDES_10G0_IP3_LN3_TXCLK                                                     | CLK_STATE_READY     | 0               |
    |   365     |    83    | DEV_SERDES_10G0_IP3_LN3_TXFCLK                                                    | CLK_STATE_READY     | 0               |
    |   365     |    84    | DEV_SERDES_10G0_IP3_LN3_TXMCLK                                                    | CLK_STATE_READY     | 0               |
    |   365     |    85    | DEV_SERDES_10G0_IP4_LN0_REFCLK                                                    | CLK_STATE_READY     | 0               |
    |   365     |    86    | DEV_SERDES_10G0_IP4_LN0_RXCLK                                                     | CLK_STATE_READY     | 0               |
    |   365     |    87    | DEV_SERDES_10G0_IP4_LN0_RXFCLK                                                    | CLK_STATE_READY     | 0               |
    |   365     |    88    | DEV_SERDES_10G0_IP4_LN0_TXCLK                                                     | CLK_STATE_NOT_READY | 0               |
    |   365     |    89    | DEV_SERDES_10G0_IP4_LN0_TXFCLK                                                    | CLK_STATE_READY     | 0               |
    |   365     |    90    | DEV_SERDES_10G0_IP4_LN0_TXMCLK                                                    | CLK_STATE_READY     | 0               |
    |   365     |    91    | DEV_SERDES_10G0_IP4_LN1_REFCLK                                                    | CLK_STATE_READY     | 0               |
    |   365     |    92    | DEV_SERDES_10G0_IP4_LN1_RXCLK                                                     | CLK_STATE_READY     | 0               |
    |   365     |    93    | DEV_SERDES_10G0_IP4_LN1_RXFCLK                                                    | CLK_STATE_READY     | 0               |
    |   365     |    94    | DEV_SERDES_10G0_IP4_LN1_TXCLK                                                     | CLK_STATE_NOT_READY | 0               |
    |   365     |    95    | DEV_SERDES_10G0_IP4_LN1_TXFCLK                                                    | CLK_STATE_READY     | 0               |
    |   365     |    96    | DEV_SERDES_10G0_IP4_LN1_TXMCLK                                                    | CLK_STATE_READY     | 0               |
    |   365     |    97    | DEV_SERDES_10G0_IP4_LN2_REFCLK                                                    | CLK_STATE_READY     | 0               |
    |   365     |    98    | DEV_SERDES_10G0_IP4_LN2_RXCLK                                                     | CLK_STATE_READY     | 0               |
    |   365     |    99    | DEV_SERDES_10G0_IP4_LN2_RXFCLK                                                    | CLK_STATE_READY     | 0               |
    |   365     |   100    | DEV_SERDES_10G0_IP4_LN2_TXCLK                                                     | CLK_STATE_NOT_READY | 0               |
    |   365     |   101    | DEV_SERDES_10G0_IP4_LN2_TXFCLK                                                    | CLK_STATE_READY     | 0               |
    |   365     |   102    | DEV_SERDES_10G0_IP4_LN2_TXMCLK                                                    | CLK_STATE_READY     | 0               |
    |   365     |   103    | DEV_SERDES_10G0_IP4_LN3_REFCLK                                                    | CLK_STATE_READY     | 0               |
    |   365     |   104    | DEV_SERDES_10G0_IP4_LN3_RXCLK                                                     | CLK_STATE_READY     | 0               |
    |   365     |   105    | DEV_SERDES_10G0_IP4_LN3_RXFCLK                                                    | CLK_STATE_READY     | 0               |
    |   365     |   106    | DEV_SERDES_10G0_IP4_LN3_TXCLK                                                     | CLK_STATE_NOT_READY | 0               |
    |   365     |   107    | DEV_SERDES_10G0_IP4_LN3_TXFCLK                                                    | CLK_STATE_READY     | 0               |
    |   365     |   108    | DEV_SERDES_10G0_IP4_LN3_TXMCLK                                                    | CLK_STATE_READY     | 0               |
    |   365     |   130    | DEV_SERDES_10G0_TAP_TCK                                                           | CLK_STATE_READY     | 0               |
    |    42     |     0    | DEV_STM0_CORE_CLK                                                                 | CLK_STATE_READY     | 250000000       |
    |    42     |     1    | DEV_STM0_VBUSP_CLK                                                                | CLK_STATE_READY     | 125000000       |
    |    42     |     2    | DEV_STM0_ATB_CLK                                                                  | CLK_STATE_READY     | 250000000       |
    |    63     |     0    | DEV_TIMER0_TIMER_PWM                                                              | CLK_STATE_READY     | 0               |
    |    63     |     1    | DEV_TIMER0_TIMER_TCLK_CLK                                                         | CLK_STATE_READY     | 19200000        |
    |    63     |     2    | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                          | CLK_STATE_READY     | 19200000        |
    |    63     |     3    | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                           | CLK_STATE_READY     | 0               |
    |    63     |     4    | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT8_CLK              | CLK_STATE_READY     | 250000000       |
    |    63     |     5    | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK     | CLK_STATE_READY     | 12500000        |
    |    63     |     6    | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK                | CLK_STATE_READY     | 250000000       |
    |    63     |     7    | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                      | CLK_STATE_READY     | 0               |
    |    63     |     8    | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT                          | CLK_STATE_READY     | 0               |
    |    63     |     9    | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                          | CLK_STATE_READY     | 32768           |
    |    63     |    10    | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT                        | CLK_STATE_READY     | 0               |
    |    63     |    11    | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK                | CLK_STATE_READY     | 192000000       |
    |    63     |    12    | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK              | CLK_STATE_READY     | 225000000       |
    |    63     |    13    | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK                | CLK_STATE_READY     | 196608000       |
    |    63     |    14    | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF2                  | CLK_STATE_READY     | 0               |
    |    63     |    15    | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF3                  | CLK_STATE_READY     | 0               |
    |    63     |    16    | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MAIN_0_CPTS_GENF0                     | CLK_STATE_NOT_READY | 0               |
    |    63     |    18    | DEV_TIMER0_TIMER_HCLK_CLK                                                         | CLK_STATE_READY     | 125000000       |
    |    64     |     1    | DEV_TIMER1_TIMER_TCLK_CLK                                                         | CLK_STATE_READY     | 19200000        |
    |    64     |     2    | DEV_TIMER1_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT1                           | CLK_STATE_READY     | 19200000        |
    |    64     |     3    | DEV_TIMER1_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_0_TIMER_PWM                  | CLK_STATE_READY     | 0               |
    |    64     |    18    | DEV_TIMER1_TIMER_HCLK_CLK                                                         | CLK_STATE_READY     | 125000000       |
    |    73     |     0    | DEV_TIMER10_TIMER_PWM                                                             | CLK_STATE_READY     | 0               |
    |    73     |     1    | DEV_TIMER10_TIMER_TCLK_CLK                                                        | CLK_STATE_READY     | 19200000        |
    |    73     |     2    | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                         | CLK_STATE_READY     | 19200000        |
    |    73     |     3    | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                          | CLK_STATE_READY     | 0               |
    |    73     |     4    | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT8_CLK             | CLK_STATE_READY     | 250000000       |
    |    73     |     5    | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK    | CLK_STATE_READY     | 12500000        |
    |    73     |     6    | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK               | CLK_STATE_READY     | 250000000       |
    |    73     |     7    | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                     | CLK_STATE_READY     | 0               |
    |    73     |     8    | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT                         | CLK_STATE_READY     | 0               |
    |    73     |     9    | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                         | CLK_STATE_READY     | 32768           |
    |    73     |    10    | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT                       | CLK_STATE_READY     | 0               |
    |    73     |    11    | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK               | CLK_STATE_READY     | 192000000       |
    |    73     |    12    | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK             | CLK_STATE_READY     | 225000000       |
    |    73     |    13    | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK               | CLK_STATE_READY     | 196608000       |
    |    73     |    14    | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF2                 | CLK_STATE_READY     | 0               |
    |    73     |    15    | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF3                 | CLK_STATE_READY     | 0               |
    |    73     |    16    | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MAIN_0_CPTS_GENF0                    | CLK_STATE_NOT_READY | 0               |
    |    73     |    18    | DEV_TIMER10_TIMER_HCLK_CLK                                                        | CLK_STATE_READY     | 125000000       |
    |    74     |     1    | DEV_TIMER11_TIMER_TCLK_CLK                                                        | CLK_STATE_READY     | 19200000        |
    |    74     |     2    | DEV_TIMER11_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT11                         | CLK_STATE_READY     | 19200000        |
    |    74     |     3    | DEV_TIMER11_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_10_TIMER_PWM                | CLK_STATE_NOT_READY | 0               |
    |    74     |    18    | DEV_TIMER11_TIMER_HCLK_CLK                                                        | CLK_STATE_READY     | 125000000       |
    |    75     |     0    | DEV_TIMER12_TIMER_PWM                                                             | CLK_STATE_READY     | 0               |
    |    75     |     1    | DEV_TIMER12_TIMER_TCLK_CLK                                                        | CLK_STATE_READY     | 19200000        |
    |    75     |     2    | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                         | CLK_STATE_READY     | 19200000        |
    |    75     |     3    | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                          | CLK_STATE_READY     | 0               |
    |    75     |     4    | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT8_CLK             | CLK_STATE_READY     | 250000000       |
    |    75     |     5    | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK    | CLK_STATE_READY     | 12500000        |
    |    75     |     6    | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK               | CLK_STATE_READY     | 250000000       |
    |    75     |     7    | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                     | CLK_STATE_READY     | 0               |
    |    75     |     8    | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT                         | CLK_STATE_READY     | 0               |
    |    75     |     9    | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                         | CLK_STATE_READY     | 32768           |
    |    75     |    10    | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT                       | CLK_STATE_READY     | 0               |
    |    75     |    11    | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK               | CLK_STATE_READY     | 192000000       |
    |    75     |    12    | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK             | CLK_STATE_READY     | 225000000       |
    |    75     |    13    | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK               | CLK_STATE_READY     | 196608000       |
    |    75     |    14    | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF2                 | CLK_STATE_READY     | 0               |
    |    75     |    15    | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF3                 | CLK_STATE_READY     | 0               |
    |    75     |    16    | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MAIN_0_CPTS_GENF0                    | CLK_STATE_NOT_READY | 0               |
    |    75     |    18    | DEV_TIMER12_TIMER_HCLK_CLK                                                        | CLK_STATE_READY     | 125000000       |
    |    76     |     1    | DEV_TIMER13_TIMER_TCLK_CLK                                                        | CLK_STATE_READY     | 19200000        |
    |    76     |     2    | DEV_TIMER13_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT13                         | CLK_STATE_READY     | 19200000        |
    |    76     |     3    | DEV_TIMER13_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_12_TIMER_PWM                | CLK_STATE_NOT_READY | 0               |
    |    76     |    18    | DEV_TIMER13_TIMER_HCLK_CLK                                                        | CLK_STATE_READY     | 125000000       |
    |    77     |     0    | DEV_TIMER14_TIMER_PWM                                                             | CLK_STATE_READY     | 0               |
    |    77     |     1    | DEV_TIMER14_TIMER_TCLK_CLK                                                        | CLK_STATE_READY     | 19200000        |
    |    77     |     2    | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                         | CLK_STATE_READY     | 19200000        |
    |    77     |     3    | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                          | CLK_STATE_READY     | 0               |
    |    77     |     4    | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT8_CLK             | CLK_STATE_READY     | 250000000       |
    |    77     |     5    | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK    | CLK_STATE_READY     | 12500000        |
    |    77     |     6    | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK               | CLK_STATE_READY     | 250000000       |
    |    77     |     7    | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                     | CLK_STATE_READY     | 0               |
    |    77     |     8    | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT                         | CLK_STATE_READY     | 0               |
    |    77     |     9    | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                         | CLK_STATE_READY     | 32768           |
    |    77     |    10    | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT                       | CLK_STATE_READY     | 0               |
    |    77     |    11    | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK               | CLK_STATE_READY     | 192000000       |
    |    77     |    12    | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK             | CLK_STATE_READY     | 225000000       |
    |    77     |    13    | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK               | CLK_STATE_READY     | 196608000       |
    |    77     |    14    | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF2                 | CLK_STATE_READY     | 0               |
    |    77     |    15    | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF3                 | CLK_STATE_READY     | 0               |
    |    77     |    16    | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MAIN_0_CPTS_GENF0                    | CLK_STATE_NOT_READY | 0               |
    |    77     |    18    | DEV_TIMER14_TIMER_HCLK_CLK                                                        | CLK_STATE_READY     | 125000000       |
    |    78     |     1    | DEV_TIMER15_TIMER_TCLK_CLK                                                        | CLK_STATE_READY     | 19200000        |
    |    78     |     2    | DEV_TIMER15_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT15                         | CLK_STATE_READY     | 19200000        |
    |    78     |     3    | DEV_TIMER15_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_14_TIMER_PWM                | CLK_STATE_NOT_READY | 0               |
    |    78     |    18    | DEV_TIMER15_TIMER_HCLK_CLK                                                        | CLK_STATE_READY     | 125000000       |
    |    79     |     0    | DEV_TIMER16_TIMER_PWM                                                             | CLK_STATE_READY     | 0               |
    |    79     |     1    | DEV_TIMER16_TIMER_TCLK_CLK                                                        | CLK_STATE_READY     | 19200000        |
    |    79     |     2    | DEV_TIMER16_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT16                         | CLK_STATE_READY     | 19200000        |
    |    79     |     3    | DEV_TIMER16_TIMER_TCLK_CLK_PARENT_MAIN_TIMER16_AFS_SEL_OUT0                       | CLK_STATE_READY     | 0               |
    |    79     |    34    | DEV_TIMER16_TIMER_HCLK_CLK                                                        | CLK_STATE_READY     | 125000000       |
    |    80     |     1    | DEV_TIMER17_TIMER_TCLK_CLK                                                        | CLK_STATE_READY     | 19200000        |
    |    80     |     2    | DEV_TIMER17_TIMER_TCLK_CLK_PARENT_MAIN_TIMER17_AFS_EN_OUT0                        | CLK_STATE_READY     | 19200000        |
    |    80     |     3    | DEV_TIMER17_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_16_TIMER_PWM                | CLK_STATE_NOT_READY | 0               |
    |    80     |    34    | DEV_TIMER17_TIMER_HCLK_CLK                                                        | CLK_STATE_READY     | 125000000       |
    |    81     |     0    | DEV_TIMER18_TIMER_PWM                                                             | CLK_STATE_READY     | 0               |
    |    81     |     1    | DEV_TIMER18_TIMER_TCLK_CLK                                                        | CLK_STATE_READY     | 19200000        |
    |    81     |     2    | DEV_TIMER18_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT18                         | CLK_STATE_READY     | 19200000        |
    |    81     |     3    | DEV_TIMER18_TIMER_TCLK_CLK_PARENT_MAIN_TIMER18_AFS_SEL_OUT0                       | CLK_STATE_READY     | 0               |
    |    81     |    34    | DEV_TIMER18_TIMER_HCLK_CLK                                                        | CLK_STATE_READY     | 125000000       |
    |    82     |     1    | DEV_TIMER19_TIMER_TCLK_CLK                                                        | CLK_STATE_READY     | 19200000        |
    |    82     |     2    | DEV_TIMER19_TIMER_TCLK_CLK_PARENT_MAIN_TIMER19_AFS_EN_OUT0                        | CLK_STATE_READY     | 19200000        |
    |    82     |     3    | DEV_TIMER19_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_18_TIMER_PWM                | CLK_STATE_NOT_READY | 0               |
    |    82     |    34    | DEV_TIMER19_TIMER_HCLK_CLK                                                        | CLK_STATE_READY     | 125000000       |
    |    65     |     0    | DEV_TIMER2_TIMER_PWM                                                              | CLK_STATE_READY     | 0               |
    |    65     |     1    | DEV_TIMER2_TIMER_TCLK_CLK                                                         | CLK_STATE_READY     | 19200000        |
    |    65     |     2    | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                          | CLK_STATE_READY     | 19200000        |
    |    65     |     3    | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                           | CLK_STATE_READY     | 0               |
    |    65     |     4    | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT8_CLK              | CLK_STATE_READY     | 250000000       |
    |    65     |     5    | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK     | CLK_STATE_READY     | 12500000        |
    |    65     |     6    | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK                | CLK_STATE_READY     | 250000000       |
    |    65     |     7    | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                      | CLK_STATE_READY     | 0               |
    |    65     |     8    | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT                          | CLK_STATE_READY     | 0               |
    |    65     |     9    | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                          | CLK_STATE_READY     | 32768           |
    |    65     |    10    | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT                        | CLK_STATE_READY     | 0               |
    |    65     |    11    | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK                | CLK_STATE_READY     | 192000000       |
    |    65     |    12    | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK              | CLK_STATE_READY     | 225000000       |
    |    65     |    13    | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK                | CLK_STATE_READY     | 196608000       |
    |    65     |    14    | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF2                  | CLK_STATE_READY     | 0               |
    |    65     |    15    | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF3                  | CLK_STATE_READY     | 0               |
    |    65     |    16    | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MAIN_0_CPTS_GENF0                     | CLK_STATE_NOT_READY | 0               |
    |    65     |    18    | DEV_TIMER2_TIMER_HCLK_CLK                                                         | CLK_STATE_READY     | 125000000       |
    |    66     |     1    | DEV_TIMER3_TIMER_TCLK_CLK                                                         | CLK_STATE_READY     | 19200000        |
    |    66     |     2    | DEV_TIMER3_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT3                           | CLK_STATE_READY     | 19200000        |
    |    66     |     3    | DEV_TIMER3_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_2_TIMER_PWM                  | CLK_STATE_READY     | 0               |
    |    66     |    18    | DEV_TIMER3_TIMER_HCLK_CLK                                                         | CLK_STATE_READY     | 125000000       |
    |    67     |     0    | DEV_TIMER4_TIMER_PWM                                                              | CLK_STATE_READY     | 0               |
    |    67     |     1    | DEV_TIMER4_TIMER_TCLK_CLK                                                         | CLK_STATE_READY     | 19200000        |
    |    67     |     2    | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                          | CLK_STATE_READY     | 19200000        |
    |    67     |     3    | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                           | CLK_STATE_READY     | 0               |
    |    67     |     4    | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT8_CLK              | CLK_STATE_READY     | 250000000       |
    |    67     |     5    | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK     | CLK_STATE_READY     | 12500000        |
    |    67     |     6    | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK                | CLK_STATE_READY     | 250000000       |
    |    67     |     7    | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                      | CLK_STATE_READY     | 0               |
    |    67     |     8    | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT                          | CLK_STATE_READY     | 0               |
    |    67     |     9    | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                          | CLK_STATE_READY     | 32768           |
    |    67     |    10    | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT                        | CLK_STATE_READY     | 0               |
    |    67     |    11    | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK                | CLK_STATE_READY     | 192000000       |
    |    67     |    12    | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK              | CLK_STATE_READY     | 225000000       |
    |    67     |    13    | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK                | CLK_STATE_READY     | 196608000       |
    |    67     |    14    | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF2                  | CLK_STATE_READY     | 0               |
    |    67     |    15    | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF3                  | CLK_STATE_READY     | 0               |
    |    67     |    16    | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MAIN_0_CPTS_GENF0                     | CLK_STATE_NOT_READY | 0               |
    |    67     |    18    | DEV_TIMER4_TIMER_HCLK_CLK                                                         | CLK_STATE_READY     | 125000000       |
    |    68     |     1    | DEV_TIMER5_TIMER_TCLK_CLK                                                         | CLK_STATE_READY     | 19200000        |
    |    68     |     2    | DEV_TIMER5_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT5                           | CLK_STATE_READY     | 19200000        |
    |    68     |     3    | DEV_TIMER5_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_4_TIMER_PWM                  | CLK_STATE_READY     | 0               |
    |    68     |    18    | DEV_TIMER5_TIMER_HCLK_CLK                                                         | CLK_STATE_READY     | 125000000       |
    |    69     |     0    | DEV_TIMER6_TIMER_PWM                                                              | CLK_STATE_READY     | 0               |
    |    69     |     1    | DEV_TIMER6_TIMER_TCLK_CLK                                                         | CLK_STATE_READY     | 19200000        |
    |    69     |     2    | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                          | CLK_STATE_READY     | 19200000        |
    |    69     |     3    | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                           | CLK_STATE_READY     | 0               |
    |    69     |     4    | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT8_CLK              | CLK_STATE_READY     | 250000000       |
    |    69     |     5    | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK     | CLK_STATE_READY     | 12500000        |
    |    69     |     6    | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK                | CLK_STATE_READY     | 250000000       |
    |    69     |     7    | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                      | CLK_STATE_READY     | 0               |
    |    69     |     8    | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT                          | CLK_STATE_READY     | 0               |
    |    69     |     9    | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                          | CLK_STATE_READY     | 32768           |
    |    69     |    10    | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT                        | CLK_STATE_READY     | 0               |
    |    69     |    11    | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK                | CLK_STATE_READY     | 192000000       |
    |    69     |    12    | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK              | CLK_STATE_READY     | 225000000       |
    |    69     |    13    | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK                | CLK_STATE_READY     | 196608000       |
    |    69     |    14    | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF2                  | CLK_STATE_READY     | 0               |
    |    69     |    15    | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF3                  | CLK_STATE_READY     | 0               |
    |    69     |    16    | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MAIN_0_CPTS_GENF0                     | CLK_STATE_NOT_READY | 0               |
    |    69     |    18    | DEV_TIMER6_TIMER_HCLK_CLK                                                         | CLK_STATE_READY     | 125000000       |
    |    70     |     1    | DEV_TIMER7_TIMER_TCLK_CLK                                                         | CLK_STATE_READY     | 19200000        |
    |    70     |     2    | DEV_TIMER7_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT7                           | CLK_STATE_READY     | 19200000        |
    |    70     |     3    | DEV_TIMER7_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_6_TIMER_PWM                  | CLK_STATE_READY     | 0               |
    |    70     |    18    | DEV_TIMER7_TIMER_HCLK_CLK                                                         | CLK_STATE_READY     | 125000000       |
    |    71     |     0    | DEV_TIMER8_TIMER_PWM                                                              | CLK_STATE_READY     | 0               |
    |    71     |     1    | DEV_TIMER8_TIMER_TCLK_CLK                                                         | CLK_STATE_READY     | 19200000        |
    |    71     |     2    | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                          | CLK_STATE_READY     | 19200000        |
    |    71     |     3    | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                           | CLK_STATE_READY     | 0               |
    |    71     |     4    | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT8_CLK              | CLK_STATE_READY     | 250000000       |
    |    71     |     5    | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK     | CLK_STATE_READY     | 12500000        |
    |    71     |     6    | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK                | CLK_STATE_READY     | 250000000       |
    |    71     |     7    | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                      | CLK_STATE_READY     | 0               |
    |    71     |     8    | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT                          | CLK_STATE_READY     | 0               |
    |    71     |     9    | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                          | CLK_STATE_READY     | 32768           |
    |    71     |    10    | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT                        | CLK_STATE_READY     | 0               |
    |    71     |    11    | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK                | CLK_STATE_READY     | 192000000       |
    |    71     |    12    | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK              | CLK_STATE_READY     | 225000000       |
    |    71     |    13    | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK                | CLK_STATE_READY     | 196608000       |
    |    71     |    14    | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF2                  | CLK_STATE_READY     | 0               |
    |    71     |    15    | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF3                  | CLK_STATE_READY     | 0               |
    |    71     |    16    | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MAIN_0_CPTS_GENF0                     | CLK_STATE_NOT_READY | 0               |
    |    71     |    18    | DEV_TIMER8_TIMER_HCLK_CLK                                                         | CLK_STATE_READY     | 125000000       |
    |    72     |     1    | DEV_TIMER9_TIMER_TCLK_CLK                                                         | CLK_STATE_READY     | 19200000        |
    |    72     |     2    | DEV_TIMER9_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT9                           | CLK_STATE_READY     | 19200000        |
    |    72     |     3    | DEV_TIMER9_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_8_TIMER_PWM                  | CLK_STATE_NOT_READY | 0               |
    |    72     |    18    | DEV_TIMER9_TIMER_HCLK_CLK                                                         | CLK_STATE_READY     | 125000000       |
    |   124     |     0    | DEV_TIMESYNC_INTRTR0_INTR_CLK                                                     | CLK_STATE_READY     | 125000000       |
    |   146     |     2    | DEV_UART0_VBUSP_CLK                                                               | CLK_STATE_READY     | 125000000       |
    |   146     |     3    | DEV_UART0_FCLK_CLK                                                                | CLK_STATE_READY     | 48000000        |
    |   350     |     2    | DEV_UART1_VBUSP_CLK                                                               | CLK_STATE_READY     | 125000000       |
    |   350     |     3    | DEV_UART1_FCLK_CLK                                                                | CLK_STATE_READY     | 48000000        |
    |   351     |     2    | DEV_UART2_VBUSP_CLK                                                               | CLK_STATE_READY     | 125000000       |
    |   351     |     3    | DEV_UART2_FCLK_CLK                                                                | CLK_STATE_READY     | 48000000        |
    |   352     |     2    | DEV_UART3_VBUSP_CLK                                                               | CLK_STATE_READY     | 125000000       |
    |   352     |     3    | DEV_UART3_FCLK_CLK                                                                | CLK_STATE_READY     | 48000000        |
    |   353     |     2    | DEV_UART4_VBUSP_CLK                                                               | CLK_STATE_READY     | 125000000       |
    |   353     |     3    | DEV_UART4_FCLK_CLK                                                                | CLK_STATE_READY     | 48000000        |
    |   354     |     2    | DEV_UART5_VBUSP_CLK                                                               | CLK_STATE_READY     | 125000000       |
    |   354     |     3    | DEV_UART5_FCLK_CLK                                                                | CLK_STATE_READY     | 48000000        |
    |   355     |     2    | DEV_UART6_VBUSP_CLK                                                               | CLK_STATE_READY     | 125000000       |
    |   355     |     3    | DEV_UART6_FCLK_CLK                                                                | CLK_STATE_READY     | 48000000        |
    |   356     |     2    | DEV_UART7_VBUSP_CLK                                                               | CLK_STATE_READY     | 125000000       |
    |   356     |     3    | DEV_UART7_FCLK_CLK                                                                | CLK_STATE_READY     | 48000000        |
    |   357     |     2    | DEV_UART8_VBUSP_CLK                                                               | CLK_STATE_READY     | 125000000       |
    |   357     |     3    | DEV_UART8_FCLK_CLK                                                                | CLK_STATE_READY     | 48000000        |
    |   358     |     2    | DEV_UART9_VBUSP_CLK                                                               | CLK_STATE_READY     | 125000000       |
    |   358     |     3    | DEV_UART9_FCLK_CLK                                                                | CLK_STATE_READY     | 48000000        |
    |   360     |     1    | DEV_USB0_PIPE_RXFCLK                                                              | CLK_STATE_READY     | 0               |
    |   360     |     2    | DEV_USB0_PIPE_RXFCLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP3_LN3_RXFCLK                    | CLK_STATE_READY     | 0               |
    |   360     |     3    | DEV_USB0_PIPE_RXFCLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP3_LN1_RXFCLK                    | CLK_STATE_READY     | 0               |
    |   360     |     4    | DEV_USB0_USB2_APB_PCLK_CLK                                                        | CLK_STATE_READY     | 125000000       |
    |   360     |     5    | DEV_USB0_PIPE_TXCLK                                                               | CLK_STATE_READY     | 0               |
    |   360     |     7    | DEV_USB0_PIPE_TXFCLK                                                              | CLK_STATE_READY     | 0               |
    |   360     |     8    | DEV_USB0_PIPE_TXFCLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP3_LN3_TXFCLK                    | CLK_STATE_READY     | 0               |
    |   360     |     9    | DEV_USB0_PIPE_TXFCLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP3_LN1_TXFCLK                    | CLK_STATE_READY     | 0               |
    |   360     |    10    | DEV_USB0_PIPE_REFCLK                                                              | CLK_STATE_READY     | 0               |
    |   360     |    11    | DEV_USB0_PIPE_REFCLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP3_LN3_REFCLK                    | CLK_STATE_READY     | 0               |
    |   360     |    12    | DEV_USB0_PIPE_REFCLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP3_LN1_REFCLK                    | CLK_STATE_READY     | 0               |
    |   360     |    13    | DEV_USB0_PCLK_CLK                                                                 | CLK_STATE_READY     | 125000000       |
    |   360     |    15    | DEV_USB0_CLK_LPM_CLK                                                              | CLK_STATE_READY     | 24000000        |
    |   360     |    16    | DEV_USB0_USB2_REFCLOCK_CLK                                                        | CLK_STATE_READY     | 19200000        |
    |   360     |    17    | DEV_USB0_USB2_REFCLOCK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                         | CLK_STATE_READY     | 19200000        |
    |   360     |    18    | DEV_USB0_USB2_REFCLOCK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                          | CLK_STATE_READY     | 0               |
    |   360     |    19    | DEV_USB0_PIPE_RXCLK                                                               | CLK_STATE_READY     | 0               |
    |   360     |    20    | DEV_USB0_PIPE_RXCLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP3_LN3_RXCLK                      | CLK_STATE_READY     | 0               |
    |   360     |    21    | DEV_USB0_PIPE_RXCLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP3_LN1_RXCLK                      | CLK_STATE_READY     | 0               |
    |   360     |    22    | DEV_USB0_ACLK_CLK                                                                 | CLK_STATE_READY     | 500000000       |
    |   360     |    23    | DEV_USB0_BUF_CLK                                                                  | CLK_STATE_READY     | 250000000       |
    |   360     |    25    | DEV_USB0_USB2_TAP_TCK                                                             | CLK_STATE_READY     | 0               |
    |   360     |    26    | DEV_USB0_PIPE_TXMCLK                                                              | CLK_STATE_READY     | 0               |
    |   360     |    27    | DEV_USB0_PIPE_TXMCLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP3_LN3_TXMCLK                    | CLK_STATE_READY     | 0               |
    |   360     |    28    | DEV_USB0_PIPE_TXMCLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP3_LN1_TXMCLK                    | CLK_STATE_READY     | 0               |
    |   361     |     0    | DEV_VPAC0_LDC0_CLK_CLK                                                            | CLK_STATE_READY     | 720000000       |
    |   361     |     1    | DEV_VPAC0_NF_CLK_CLK                                                              | CLK_STATE_READY     | 720000000       |
    |   361     |     2    | DEV_VPAC0_MAIN_CLK                                                                | CLK_STATE_READY     | 720000000       |
    |   361     |     3    | DEV_VPAC0_MAIN_CLK_PARENT_HSDIV1_16FFT_MAIN_25_HSDIVOUT1_CLK                      | CLK_STATE_READY     | 720000000       |
    |   361     |     4    | DEV_VPAC0_MAIN_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK                       | CLK_STATE_READY     | 600000000       |
    |   361     |     5    | DEV_VPAC0_VISS0_CLK_CLK                                                           | CLK_STATE_READY     | 720000000       |
    |   361     |     6    | DEV_VPAC0_PSIL_LEAF_CLK                                                           | CLK_STATE_READY     | 500000000       |
    |   361     |     7    | DEV_VPAC0_MSC_CLK                                                                 | CLK_STATE_READY     | 720000000       |
    |   362     |     0    | DEV_VUSR_DUAL0_V0_RXFL_CLK                                                        | CLK_STATE_READY     | 0               |
    |   362     |     1    | DEV_VUSR_DUAL0_VUSRX_LN0_TXFCLK                                                   | CLK_STATE_READY     | 0               |
    |   362     |     2    | DEV_VUSR_DUAL0_V0_CLK                                                             | CLK_STATE_READY     | 500000000       |
    |   362     |     3    | DEV_VUSR_DUAL0_V1_TXPM_CLK                                                        | CLK_STATE_READY     | 0               |
    |   362     |     4    | DEV_VUSR_DUAL0_VUSRX_LN1_TXMCLK                                                   | CLK_STATE_READY     | 0               |
    |   362     |     5    | DEV_VUSR_DUAL0_V1_TXFL_CLK                                                        | CLK_STATE_READY     | 0               |
    |   362     |     6    | DEV_VUSR_DUAL0_VUSRX_LN0_RXCLK                                                    | CLK_STATE_READY     | 0               |
    |   362     |     7    | DEV_VUSR_DUAL0_VUSRX_LN2_RXFCLK                                                   | CLK_STATE_READY     | 0               |
    |   362     |     8    | DEV_VUSR_DUAL0_VUSRX_LN2_REFCLK                                                   | CLK_STATE_READY     | 0               |
    |   362     |     9    | DEV_VUSR_DUAL0_VUSRX_LN3_RXCLK                                                    | CLK_STATE_READY     | 0               |
    |   362     |    10    | DEV_VUSR_DUAL0_VUSRX_LN1_RXFCLK                                                   | CLK_STATE_READY     | 0               |
    |   362     |    11    | DEV_VUSR_DUAL0_VUSRX_LN0_REFCLK                                                   | CLK_STATE_READY     | 0               |
    |   362     |    12    | DEV_VUSR_DUAL0_VUSRX_LN1_TXCLK                                                    | CLK_STATE_READY     | 0               |
    |   362     |    13    | DEV_VUSR_DUAL0_VUSRX_LN3_RXFCLK                                                   | CLK_STATE_READY     | 0               |
    |   362     |    14    | DEV_VUSR_DUAL0_VUSRX_LN3_TXCLK                                                    | CLK_STATE_READY     | 0               |
    |   362     |    15    | DEV_VUSR_DUAL0_VUSRX_LN3_TXMCLK                                                   | CLK_STATE_READY     | 0               |
    |   362     |    16    | DEV_VUSR_DUAL0_VUSRX_LN3_TXFCLK                                                   | CLK_STATE_READY     | 0               |
    |   362     |    17    | DEV_VUSR_DUAL0_VUSRX_LN0_TXCLK                                                    | CLK_STATE_READY     | 0               |
    |   362     |    18    | DEV_VUSR_DUAL0_V1_CLK                                                             | CLK_STATE_READY     | 500000000       |
    |   362     |    19    | DEV_VUSR_DUAL0_V0_TXFL_CLK                                                        | CLK_STATE_READY     | 0               |
    |   362     |    20    | DEV_VUSR_DUAL0_VUSRX_LN0_RXFCLK                                                   | CLK_STATE_READY     | 0               |
    |   362     |    21    | DEV_VUSR_DUAL0_VUSRX_LN2_RXCLK                                                    | CLK_STATE_READY     | 0               |
    |   362     |    22    | DEV_VUSR_DUAL0_V0_TXPM_CLK                                                        | CLK_STATE_READY     | 0               |
    |   362     |    23    | DEV_VUSR_DUAL0_V0_RXPM_CLK                                                        | CLK_STATE_READY     | 0               |
    |   362     |    24    | DEV_VUSR_DUAL0_VUSRX_LN1_REFCLK                                                   | CLK_STATE_READY     | 0               |
    |   362     |    25    | DEV_VUSR_DUAL0_V1_RXPM_CLK                                                        | CLK_STATE_READY     | 0               |
    |   362     |    26    | DEV_VUSR_DUAL0_V1_RXFL_CLK                                                        | CLK_STATE_READY     | 0               |
    |   362     |    27    | DEV_VUSR_DUAL0_VUSRX_LN2_TXCLK                                                    | CLK_STATE_READY     | 0               |
    |   362     |    28    | DEV_VUSR_DUAL0_VUSRX_LN2_TXFCLK                                                   | CLK_STATE_READY     | 0               |
    |   362     |    29    | DEV_VUSR_DUAL0_VUSRX_LN0_TXMCLK                                                   | CLK_STATE_READY     | 0               |
    |   362     |    30    | DEV_VUSR_DUAL0_VUSRX_LN2_TXMCLK                                                   | CLK_STATE_READY     | 0               |
    |   362     |    31    | DEV_VUSR_DUAL0_VUSRX_LN1_TXFCLK                                                   | CLK_STATE_READY     | 0               |
    |   362     |    32    | DEV_VUSR_DUAL0_VUSRX_LN3_REFCLK                                                   | CLK_STATE_READY     | 0               |
    |   362     |    33    | DEV_VUSR_DUAL0_VUSRX_LN1_RXCLK                                                    | CLK_STATE_READY     | 0               |
    |   151     |     0    | DEV_WKUP_DDPA0_DDPA_CLK                                                           | CLK_STATE_READY     | 166666666       |
    |   104     |     0    | DEV_WKUP_ESM0_CLK                                                                 | CLK_STATE_READY     | 166666666       |
    |   115     |     0    | DEV_WKUP_GPIO0_MMR_CLK                                                            | CLK_STATE_READY     | 27777777        |
    |   116     |     0    | DEV_WKUP_GPIO1_MMR_CLK                                                            | CLK_STATE_READY     | 27777777        |
    |   125     |     0    | DEV_WKUP_GPIOMUX_INTRTR0_INTR_CLK                                                 | CLK_STATE_READY     | 166666666       |
    |   304     |     0    | DEV_WKUP_HSM0_DAP_CLK                                                             | CLK_STATE_READY     | 1000000000      |
    |   223     |     0    | DEV_WKUP_I2C0_PORSCL                                                              | CLK_STATE_READY     | 0               |
    |   223     |     1    | DEV_WKUP_I2C0_PISYS_CLK                                                           | CLK_STATE_READY     | 96000000        |
    |   223     |     2    | DEV_WKUP_I2C0_PISYS_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT3_CLK                   | CLK_STATE_READY     | 96000000        |
    |   223     |     3    | DEV_WKUP_I2C0_PISYS_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                            | CLK_STATE_READY     | 19200000        |
    |   223     |     4    | DEV_WKUP_I2C0_CLK                                                                 | CLK_STATE_READY     | 166666666       |
    |   223     |     5    | DEV_WKUP_I2C0_PISCL                                                               | CLK_STATE_READY     | 0               |
    |   147     |     0    | DEV_WKUP_J7AM_WAKEUP_16FF0_PLL_CTRL_WKUP_CLK24_CLK                                | CLK_STATE_READY     | 1000000000      |
    |   147     |     1    | DEV_WKUP_J7AM_WAKEUP_16FF0_WKUP_RCOSC_12P5M_CLK                                   | CLK_STATE_READY     | 12500000        |
    |   147     |     2    | DEV_WKUP_J7AM_WAKEUP_16FF0_WKUP_RCOSC_32K_CLK                                     | CLK_STATE_READY     | 32000           |
    |   123     |     0    | DEV_WKUP_PORZ_SYNC0_CLK_12M_RC_CLK                                                | CLK_STATE_READY     | 12500000        |
    |   126     |     0    | DEV_WKUP_PSC0_SLOW_CLK                                                            | CLK_STATE_READY     | 41666666        |
    |   126     |     1    | DEV_WKUP_PSC0_CLK                                                                 | CLK_STATE_READY     | 166666666       |
    |   359     |     2    | DEV_WKUP_UART0_VBUSP_CLK                                                          | CLK_STATE_READY     | 166666666       |
    |   359     |     3    | DEV_WKUP_UART0_FCLK_CLK                                                           | CLK_STATE_READY     | 96000000        |
    |   359     |     4    | DEV_WKUP_UART0_FCLK_CLK_PARENT_WKUP_USART_CLKSEL_OUT0                             | CLK_STATE_READY     | 96000000        |
    |   359     |     5    | DEV_WKUP_UART0_FCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                            | CLK_STATE_READY     | 19200000        |
    |   180     |     0    | DEV_WKUP_VTM0_FIX_REF_CLK                                                         | CLK_STATE_READY     | 19200000        |
    |   180     |     1    | DEV_WKUP_VTM0_FIX_REF2_CLK                                                        | CLK_STATE_READY     | 12500000        |
    |   180     |     2    | DEV_WKUP_VTM0_VBUSP_CLK                                                           | CLK_STATE_READY     | 166666666       |
    |--------------------------------------------------------------------------------------------------------------------------------------------------|
    
    

    Thank you so much for your support! In the meantime, I will double-check the timing in the datasheet and in the code.

    Thanks again!

  • Hi Amandio,

    Clock looks correct. 

    Could you share the timing parameters and flags used in the driver? Most likely, the timing parameter is the cause of issue. We can take a look to see if anything looks off. 

    However, the recommendation is to check with the vendor of the display to see if they have a known working display timing. If the vendor's recommendation do not work, then you should use the recommended timings as baseline and tweak the display timings until display works.

    Regards,

    Takuma

  • HI Takuma,

    Here is the struct with the timings and flags:

    static const struct drm_display_mode feiyang_default_mode = {
    	.clock		= 51200,
    
    	.hdisplay	= 1024,
    	.hsync_start	= 1024 + 160,
    	.hsync_end	= 1024 + 160 + 80,
    	.htotal		= 1024 + 160 + 80 + 80,
    
    	.vdisplay	= 600,
    	.vsync_start	= 600 + 12,
    	.vsync_end	= 600 + 12 + 10,
    	.vtotal		= 600 + 12 + 10 + 13,
    
    	.width_mm	= 235,
    	.height_mm	= 143,
    
    	.type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
    };

    And just in case, here is the entirety of the modified driver. Apologies, it is a bit of a mess as we've been trying lots of things kind of frantically to try to get this working:

    // SPDX-License-Identifier: GPL-2.0+
    /*
     * Copyright (C) 2018 Amarula Solutions
     * Author: Jagan Teki <jagan@amarulasolutions.com>
     */
    
    #include <drm/drm_mipi_dsi.h>
    #include <drm/drm_modes.h>
    #include <drm/drm_panel.h>
    #include <linux/media-bus-format.h>
    
    #include <linux/gpio/consumer.h>
    #include <linux/delay.h>
    #include <linux/module.h>
    #include <linux/mod_devicetable.h>
    #include <linux/regulator/consumer.h>
    
    #define FEIYANG_INIT_CMD_LEN	2
    
    struct feiyang {
    	struct drm_panel	panel;
    	struct mipi_dsi_device	*dsi;
    
    	struct regulator	*dvdd;
    	struct regulator	*avdd;
    	struct gpio_desc	*reset;
    };
    
    static inline struct feiyang *panel_to_feiyang(struct drm_panel *panel)
    {
    	return container_of(panel, struct feiyang, panel);
    }
    
    struct feiyang_init_cmd {
    	u8 data[FEIYANG_INIT_CMD_LEN];
    };
    
    static const struct feiyang_init_cmd feiyang_init_cmds[] = {
    	{ .data = { 0xB2, 0x30 } },
    	{ .data = { 0x80, 0x5B } },
    	{ .data = { 0x81, 0x47 } },
    	{ .data = { 0x82, 0x84 } },
    	{ .data = { 0x83, 0x88 } },
    	{ .data = { 0x84, 0x88 } },
    	{ .data = { 0x85, 0x23 } },
    	{ .data = { 0x86, 0xB6 } },
    };
    
    static int feiyang_prepare(struct drm_panel *panel)
    {
    	struct feiyang *ctx = panel_to_feiyang(panel);
    	struct mipi_dsi_device *dsi = ctx->dsi;
    	unsigned int i;
    	int ret;
    
    	gpiod_set_value(ctx->reset, 0);
    
    	msleep(20);
    
    	gpiod_set_value(ctx->reset, 1);
    
    	msleep(30);
    
    	gpiod_set_value(ctx->reset, 0);
    
    	msleep(55);
    
    	u8 exitSleep = 0x11;
    	ret = mipi_dsi_dcs_write_buffer(dsi, &exitSleep, 1);
    
    	printk("mipi write sleep exit return: %u\n", ret);
    
    	msleep(10);
    
    	for (i = 0; i < ARRAY_SIZE(feiyang_init_cmds); i++) {
    		const struct feiyang_init_cmd *cmd =
    						&feiyang_init_cmds[i];
    
    		ret = mipi_dsi_dcs_write_buffer(dsi, cmd->data,
    						FEIYANG_INIT_CMD_LEN);
    
    		printk("mipi write return: %u\n", ret);
    
    		if (ret < 0)
    			return ret;
    	}
    
    	msleep(10);
    
    	return 0;
    }
    
    static int feiyang_enable(struct drm_panel *panel)
    {
    	struct feiyang *ctx = panel_to_feiyang(panel);
    
    	/* T12 (video & logic signal rise + backlight rise) T12 >= 200ms */
    	msleep(200);
    
    	mipi_dsi_dcs_set_display_on(ctx->dsi);
    
    	return 0;
    }
    
    static int feiyang_disable(struct drm_panel *panel)
    {
    	struct feiyang *ctx = panel_to_feiyang(panel);
    
    	return mipi_dsi_dcs_set_display_off(ctx->dsi);
    }
    
    static int feiyang_unprepare(struct drm_panel *panel)
    {
    	struct feiyang *ctx = panel_to_feiyang(panel);
    	int ret;
    
    	ret = mipi_dsi_dcs_set_display_off(ctx->dsi);
    	if (ret < 0)
    		dev_err(panel->dev, "failed to set display off: %d\n", ret);
    
    	ret = mipi_dsi_dcs_enter_sleep_mode(ctx->dsi);
    	if (ret < 0)
    		dev_err(panel->dev, "failed to enter sleep mode: %d\n", ret);
    
    	/* T13 (backlight fall + video & logic signal fall) T13 >= 200ms */
    	msleep(200);
    
    	gpiod_set_value(ctx->reset, 1);
    
    	regulator_disable(ctx->avdd);
    
    	/* T11 (dvdd rise to fall) 0 < T11 <= 10ms  */
    	msleep(10);
    
    	regulator_disable(ctx->dvdd);
    
    	return 0;
    }
    
    static const struct drm_display_mode feiyang_default_mode = {
    	.clock		= 51200,
    
    	.hdisplay	= 1024,
    	.hsync_start	= 1024 + 160,
    	.hsync_end	= 1024 + 160 + 80,
    	.htotal		= 1024 + 160 + 80 + 80,
    
    	.vdisplay	= 600,
    	.vsync_start	= 600 + 12,
    	.vsync_end	= 600 + 12 + 10,
    	.vtotal		= 600 + 12 + 10 + 13,
    
    	.width_mm	= 235,
    	.height_mm	= 143,
    
    	.type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
    };
    
    static int feiyang_get_modes(struct drm_panel *panel,
    			     struct drm_connector *connector)
    {
    	struct feiyang *ctx = panel_to_feiyang(panel);
    	struct drm_display_mode *mode;
    	static const u32 bus_format = MEDIA_BUS_FMT_RGB888_1X24;
    
    	mode = drm_mode_duplicate(connector->dev, &feiyang_default_mode);
    
    	//printk("mode: %px.\n", mode);
    
    	if (!mode) {
    		dev_err(&ctx->dsi->dev, "failed to add mode %ux%u@%u\n",
    			feiyang_default_mode.hdisplay,
    			feiyang_default_mode.vdisplay,
    			drm_mode_vrefresh(&feiyang_default_mode));
    		return -ENOMEM;
    	}
    
    	drm_mode_set_name(mode);
    
    	drm_mode_probed_add(connector, mode);
    
    	connector->display_info.bpc = 8;
    	connector->display_info.width_mm = mode->width_mm;
    	connector->display_info.height_mm = mode->height_mm;
    	connector->display_info.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE;
    
    	drm_display_info_set_bus_formats(&connector->display_info,
    					 &bus_format, 1);
    
    	return 1;
    }
    
    static const struct drm_panel_funcs feiyang_funcs = {
    	.disable = feiyang_disable,
    	.unprepare = feiyang_unprepare,
    	.prepare = feiyang_prepare,
    	.enable = feiyang_enable,
    	.get_modes = feiyang_get_modes,
    };
    
    static int feiyang_dsi_probe(struct mipi_dsi_device *dsi)
    {
    	struct feiyang *ctx;
    	int ret;
    
    	ctx = devm_kzalloc(&dsi->dev, sizeof(*ctx), GFP_KERNEL);
    	if (!ctx)
    		return -ENOMEM;
    
    	mipi_dsi_set_drvdata(dsi, ctx);
    	ctx->dsi = dsi;
    
    	drm_panel_init(&ctx->panel, &dsi->dev, &feiyang_funcs,
    		       DRM_MODE_CONNECTOR_DSI);
    
    	ctx->dvdd = devm_regulator_get(&dsi->dev, "dvdd");
    	if (IS_ERR(ctx->dvdd))
    		return dev_err_probe(&dsi->dev, PTR_ERR(ctx->dvdd),
    				     "Couldn't get dvdd regulator\n");
    
    	ctx->avdd = devm_regulator_get(&dsi->dev, "avdd");
    	if (IS_ERR(ctx->avdd))
    		return dev_err_probe(&dsi->dev, PTR_ERR(ctx->avdd),
    				     "Couldn't get avdd regulator\n");
    
    	ctx->reset = devm_gpiod_get_optional(&dsi->dev, "reset", GPIOD_OUT_LOW);
    	if (IS_ERR(ctx->reset))
    		return dev_err_probe(&dsi->dev, PTR_ERR(ctx->reset),
    				     "Couldn't get our reset GPIO\n");
    
    	ret = drm_panel_of_backlight(&ctx->panel);
    
    	printk("drm_panel_of_backlight: %u\n", ret);
    
    	if (ret)
    		return ret;
    
    	drm_panel_add(&ctx->panel);
    
    	dsi->mode_flags = MIPI_DSI_MODE_VIDEO;
    	dsi->format = MIPI_DSI_FMT_RGB888;
    	dsi->lanes = 1;
    
    	ret = mipi_dsi_attach(dsi);
    	if (ret < 0) {
    		drm_panel_remove(&ctx->panel);
    		return ret;
    	}
    
    	return 0;
    }
    
    static void feiyang_dsi_remove(struct mipi_dsi_device *dsi)
    {
    	struct feiyang *ctx = mipi_dsi_get_drvdata(dsi);
    
    	mipi_dsi_detach(dsi);
    	drm_panel_remove(&ctx->panel);
    }
    
    static const struct of_device_id feiyang_of_match[] = {
    	{ .compatible = "feiyang,fy07024di26a30d", },
    	{ /* sentinel */ }
    };
    MODULE_DEVICE_TABLE(of, feiyang_of_match);
    
    static struct mipi_dsi_driver feiyang_driver = {
    	.probe = feiyang_dsi_probe,
    	.remove = feiyang_dsi_remove,
    	.driver = {
    		.name = "feiyang-fy07024di26a30d",
    		.of_match_table = feiyang_of_match,
    	},
    };
    module_mipi_dsi_driver(feiyang_driver);
    
    MODULE_AUTHOR("Jagan Teki <jagan@amarulasolutions.com>");
    MODULE_DESCRIPTION("Feiyang FY07024DI26A30-D MIPI-DSI LCD panel");
    MODULE_LICENSE("GPL");
    

    Something else of interest. The controller for our panel is the EK79007AD3. I googled alternates for it to see if something in the Linux source tree already exists and the ronbo rb070d30 came up as a match. That panel uses the HX8282-A controller. I compared both datasheets and as far as I can tell the timings were identical. I tried using the timings from the ronbo driver as well but that does not work either.

    We have been tweaking values, flags, copying things from similar drivers all with no luck so far. I feel like if the timings were off we would still se something on the display right, even if it was distorted or garbage right? Could there be another reason besides timings that could keep the DSI from communicating to the panel?

    We are in contact with the panel manufacturer sales team in USA. Unfortunately the engineering is based in Taiwan and they are still on break for Lunar New Year.

    Again, thank you for your time!

  • Hi Amandio,

    Displays usually have some small tolerance, but if the timings are off then nothing will display as it will result in a HSYNC and/or VSYNC miss. As I mentioned in my first post before you have done register dumps and scope measurements, if the scope shows that one line is sent to the monitor before going silent, this is indication of HSYNC miss, and register dumps also have the HSYNC missed flag set. So, we can have high confidence that the timing parameters are the issue. 

    To fix this, you will need to program the correct front porch, sync, and back porch values for horizontal and vertical. 

    And the driver should be "total" = "display" + "front porch" + "sync" + "back porch" in this order for both horizontal and vertical timings. 

    Now, I have found the datasheet of the panel here: https://www.texim-europe.com/getfile.ashx?id=128316

    It is a bit hard to interpret this datasheet since it looks like some terminologies are used differently, so again, the recommendation is to get into contact with the panel's manufacturer for recommended timing. 

    But, my guess is that the datasheet is using:

    • HSYNC front porch = front porch
    • HSYNC blanking = back porch + sync
    • HSYNC pulse width = sync
    • VSYNC back porch = back porch + VSYNC pulse width
    • VSYNC pulse width = sync
    • VSYNC front porch = front porch

    So "typical" horizontal might be: 1344 = 1024 + 160 + 70 + 90

    And "typical" vertical might be: 635 = 600 + 12 + 20 + 3

    You could try these values out while you wait for a response from the manufacturers, but the best would be if we can start from a known working set of values from the manufacturer and then modify the timings until display works.

    Regards,

    Takuma

  • Hi Takuma,

    Thanks for all of this info! We tried the values you provided but they did not work. We had a call with the LCD manufacturer USA office and they were able to help a bit. They offered the same advice, that our issue appears to be a timing problem. They were able to give us more details on the timings but we have not yet found a combination of values to work. Their engineering team will be back Monday from Lunar New Year break. I'll update you with any new info or progress.

    Thanks again for your support!

  • Hi Amandio,

    Thank you for the update. I hope you get a good response!

    Regards,

    Takuma

  • Hi Takuma,

    We made a bit of progress. We discovered we need to set flags DRM_MODE_FLAG_NVSYNC and DRM_MODE_FLAG_NHSYNC in drm_display_mode struct for our panel to tell Linux that HSYNC and VSYNC are active low..Once we did this we can see some activity on the screen but it is distorted. When we run kmstest we can see RGB pattern trying to be displayed or if we run kmscube, I can see something faintly moving on the screen. Here is an example of what kmstest looks like now:

    We are still in contact with the LCD vendor because the issue still appears to be timing related but I had some additional questions.

    When I probe the each of the 4 data lanes, I see activity. Here's an example on lane 0 when the screen is idle, in other words the systems boots and no other action is taken:

    And here is the same lane if I run kmscube:

    It looks like the data lanes are active which is great, but I'm noticing no activity on the clock lane. It behaves the same in my first scope probe. I've take another, see below:

    Just that initial pulse and then nothing. Although I think it's nothing, I don't know if that floating signal after the pulse is of anything significant or if it's just noise. Can you comment on the probes and tell me if they look normal and why we are not see a clock on the clock lane?

    My other question is about the device tree. What is the assigned-clocks and assigned-clock-parents nodes in the dss node. Here is the snippet of the dss node for reference:

    &dss {
    	status = "okay";
    
    	assigned-clocks = <&k3_clks 158 2>,
    			  <&k3_clks 158 5>,
    			  <&k3_clks 158 14>,
    			  <&k3_clks 158 18>;
    	assigned-clock-parents = <&k3_clks 158 3>,
    				 <&k3_clks 158 7>,
    				 <&k3_clks 158 16>,
    				 <&k3_clks 158 22>;
    };

    In the device tree for the sk-am68 evm there was this comment in that node:

    	/*
    	 * These clock assignments are chosen to enable the following outputs:
    	 *
    	 * VP0 - DisplayPort SST
    	 * VP1 - DPI0
    	 * VP2 - DSI
    	 * VP3 - DPI1
    	 */

    I've removed and reinserted the assigned-clocks and assigned-clock-parents node and didn't find a difference. If these nodes are required to enable the output of the DSI, why do we need to put it in the dts? Shouldn't it be in the dtsi where it wouldn't be changed? 

    And my last question has to do with errors I see if I try to use certain timings. For instance, at one point the vendor recommended using these values:

    Horizontal: 1154 = 1024 + 60 + 10 + 60

    Vertical: 617 = 600 + 5 + 2 + 10

    This would also lead to a new clock value of 42721 because (1154 x 617 x 60)1000 = 42721 (kHz)

    However, I noticed no frame buffer is created and I see this error in dmesg:

    [    6.989230] tidss 4a00000.dss: [drm] Cannot find any crtc or sizes
    [    7.004696] tidss 4a00000.dss: [drm] Cannot find any crtc or sizes

    Here is the full dmesg in this case:

    dmesg_crtc_err.txt
    [    0.000000] Booting Linux on physical CPU 0x0000000000 [0x411fd080]
    [    0.000000] Linux version 6.6.32+ (amandio@DESKTOP-UJC140B) (aarch64-oe-linux-gcc (GCC) 13.3.0, GNU ld (GNU Binutils) 2.42.0.20240620) #10 SMP PREEMPT Fri Feb  7 11:59:59 EST 2025
    [    0.000000] KASLR disabled due to lack of seed
    [    0.000000] Machine model: Company Name Product Name
    [    0.000000] earlycon: ns16550a0 at MMIO32 0x0000000002830000 (options '')
    [    0.000000] printk: bootconsole [ns16550a0] enabled
    [    0.000000] efi: UEFI not found.
    [    0.000000] Reserved memory: created CMA memory pool at 0x0000000bc8000000, size 896 MiB
    [    0.000000] OF: reserved mem: initialized node linux,cma, compatible id shared-dma-pool
    [    0.000000] OF: reserved mem: 0x0000000bc8000000..0x0000000bffffffff (917504 KiB) map reusable linux,cma
    [    0.000000] OF: reserved mem: 0x000000009e800000..0x000000009fffffff (24576 KiB) nomap non-reusable optee@9e800000
    [    0.000000] Reserved memory: created DMA memory pool at 0x00000000a0000000, size 1 MiB
    [    0.000000] OF: reserved mem: initialized node r5f-dma-memory@a0000000, compatible id shared-dma-pool
    [    0.000000] OF: reserved mem: 0x00000000a0000000..0x00000000a00fffff (1024 KiB) nomap non-reusable r5f-dma-memory@a0000000
    [    0.000000] Reserved memory: created DMA memory pool at 0x00000000a0100000, size 15 MiB
    [    0.000000] OF: reserved mem: initialized node r5f-memory@a0100000, compatible id shared-dma-pool
    [    0.000000] OF: reserved mem: 0x00000000a0100000..0x00000000a0ffffff (15360 KiB) nomap non-reusable r5f-memory@a0100000
    [    0.000000] Reserved memory: created DMA memory pool at 0x00000000a1000000, size 1 MiB
    [    0.000000] OF: reserved mem: initialized node r5f-dma-memory@a1000000, compatible id shared-dma-pool
    [    0.000000] OF: reserved mem: 0x00000000a1000000..0x00000000a10fffff (1024 KiB) nomap non-reusable r5f-dma-memory@a1000000
    [    0.000000] Reserved memory: created DMA memory pool at 0x00000000a1100000, size 15 MiB
    [    0.000000] OF: reserved mem: initialized node r5f-memory@a1100000, compatible id shared-dma-pool
    [    0.000000] OF: reserved mem: 0x00000000a1100000..0x00000000a1ffffff (15360 KiB) nomap non-reusable r5f-memory@a1100000
    [    0.000000] Reserved memory: created DMA memory pool at 0x00000000a2000000, size 1 MiB
    [    0.000000] OF: reserved mem: initialized node r5f-dma-memory@a2000000, compatible id shared-dma-pool
    [    0.000000] OF: reserved mem: 0x00000000a2000000..0x00000000a20fffff (1024 KiB) nomap non-reusable r5f-dma-memory@a2000000
    [    0.000000] Reserved memory: created DMA memory pool at 0x00000000a2100000, size 15 MiB
    [    0.000000] OF: reserved mem: initialized node r5f-memory@a2100000, compatible id shared-dma-pool
    [    0.000000] OF: reserved mem: 0x00000000a2100000..0x00000000a2ffffff (15360 KiB) nomap non-reusable r5f-memory@a2100000
    [    0.000000] Reserved memory: created DMA memory pool at 0x00000000a3000000, size 1 MiB
    [    0.000000] OF: reserved mem: initialized node r5f-dma-memory@a3000000, compatible id shared-dma-pool
    [    0.000000] OF: reserved mem: 0x00000000a3000000..0x00000000a30fffff (1024 KiB) nomap non-reusable r5f-dma-memory@a3000000
    [    0.000000] Reserved memory: created DMA memory pool at 0x00000000a3100000, size 15 MiB
    [    0.000000] OF: reserved mem: initialized node r5f-memory@a3100000, compatible id shared-dma-pool
    [    0.000000] OF: reserved mem: 0x00000000a3100000..0x00000000a3ffffff (15360 KiB) nomap non-reusable r5f-memory@a3100000
    [    0.000000] Reserved memory: created DMA memory pool at 0x00000000a4000000, size 1 MiB
    [    0.000000] OF: reserved mem: initialized node r5f-dma-memory@a4000000, compatible id shared-dma-pool
    [    0.000000] OF: reserved mem: 0x00000000a4000000..0x00000000a40fffff (1024 KiB) nomap non-reusable r5f-dma-memory@a4000000
    [    0.000000] Reserved memory: created DMA memory pool at 0x00000000a4100000, size 15 MiB
    [    0.000000] OF: reserved mem: initialized node r5f-memory@a4100000, compatible id shared-dma-pool
    [    0.000000] OF: reserved mem: 0x00000000a4100000..0x00000000a4ffffff (15360 KiB) nomap non-reusable r5f-memory@a4100000
    [    0.000000] Reserved memory: created DMA memory pool at 0x00000000a5000000, size 1 MiB
    [    0.000000] OF: reserved mem: initialized node r5f-dma-memory@a5000000, compatible id shared-dma-pool
    [    0.000000] OF: reserved mem: 0x00000000a5000000..0x00000000a50fffff (1024 KiB) nomap non-reusable r5f-dma-memory@a5000000
    [    0.000000] Reserved memory: created DMA memory pool at 0x00000000a5100000, size 15 MiB
    [    0.000000] OF: reserved mem: initialized node r5f-memory@a5100000, compatible id shared-dma-pool
    [    0.000000] OF: reserved mem: 0x00000000a5100000..0x00000000a5ffffff (15360 KiB) nomap non-reusable r5f-memory@a5100000
    [    0.000000] Reserved memory: created DMA memory pool at 0x00000000a6000000, size 1 MiB
    [    0.000000] OF: reserved mem: initialized node c71-dma-memory@a6000000, compatible id shared-dma-pool
    [    0.000000] OF: reserved mem: 0x00000000a6000000..0x00000000a60fffff (1024 KiB) nomap non-reusable c71-dma-memory@a6000000
    [    0.000000] Reserved memory: created DMA memory pool at 0x00000000a6100000, size 15 MiB
    [    0.000000] OF: reserved mem: initialized node c71-memory@a6100000, compatible id shared-dma-pool
    [    0.000000] OF: reserved mem: 0x00000000a6100000..0x00000000a6ffffff (15360 KiB) nomap non-reusable c71-memory@a6100000
    [    0.000000] Reserved memory: created DMA memory pool at 0x00000000a7000000, size 1 MiB
    [    0.000000] OF: reserved mem: initialized node c71-dma-memory@a7000000, compatible id shared-dma-pool
    [    0.000000] OF: reserved mem: 0x00000000a7000000..0x00000000a70fffff (1024 KiB) nomap non-reusable c71-dma-memory@a7000000
    [    0.000000] Reserved memory: created DMA memory pool at 0x00000000a7100000, size 15 MiB
    [    0.000000] OF: reserved mem: initialized node c71-memory@a7100000, compatible id shared-dma-pool
    [    0.000000] OF: reserved mem: 0x00000000a7100000..0x00000000a7ffffff (15360 KiB) nomap non-reusable c71-memory@a7100000
    [    0.000000] OF: reserved mem: 0x00000000a8000000..0x00000000a9bfffff (28672 KiB) nomap non-reusable ipc-memories@a8000000
    [    0.000000] Zone ranges:
    [    0.000000]   DMA      [mem 0x0000000080000000-0x00000000ffffffff]
    [    0.000000]   DMA32    empty
    [    0.000000]   Normal   [mem 0x0000000100000000-0x0000000bffffffff]
    [    0.000000] Movable zone start for each node
    [    0.000000] Early memory node ranges
    [    0.000000]   node   0: [mem 0x0000000080000000-0x000000009e7fffff]
    [    0.000000]   node   0: [mem 0x000000009e800000-0x00000000a9bfffff]
    [    0.000000]   node   0: [mem 0x00000000a9c00000-0x00000000ffffffff]
    [    0.000000]   node   0: [mem 0x0000000880000000-0x0000000bffffffff]
    [    0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x0000000bffffffff]
    [    0.000000] psci: probing for conduit method from DT.
    [    0.000000] psci: PSCIv1.1 detected in firmware.
    [    0.000000] psci: Using standard PSCI v0.2 function IDs
    [    0.000000] psci: Trusted OS migration not required
    [    0.000000] psci: SMC Calling Convention v1.4
    [    0.000000] percpu: Embedded 20 pages/cpu s43112 r8192 d30616 u81920
    [    0.000000] pcpu-alloc: s43112 r8192 d30616 u81920 alloc=20*4096
    [    0.000000] pcpu-alloc: [0] 0 [0] 1 
    [    0.000000] Detected PIPT I-cache on CPU0
    [    0.000000] CPU features: detected: GIC system register CPU interface
    [    0.000000] CPU features: detected: Spectre-v3a
    [    0.000000] CPU features: detected: Spectre-BHB
    [    0.000000] CPU features: detected: ARM erratum 1742098
    [    0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
    [    0.000000] alternatives: applying boot alternatives
    [    0.000000] Kernel command line: console=ttyS3,115200n8 earlycon=ns16550a,mmio32,0x02830000 mtdparts=47040000.spi.0:512k(ospi.tiboot3),2m(ospi.tispl),4m(ospi.u-boot),256k(ospi.env),256k(ospi.env.backup),57088k@8m(ospi.rootfs),256k(ospi.phypattern);spi-nand0:512k(ospi_nand.tiboot3),2m(ospi_nand.tispl),4m(ospi_nand.u-boot),256k(ospi_nand.env),256k(ospi_nand.env.backup),98048k@32m(ospi_nand.rootfs),256k@130816k(ospi_nand.phypattern) root=PARTUUID=9dadd190-02 rw rootfstype=ext4 rootwait
    [    0.000000] Dentry cache hash table entries: 2097152 (order: 12, 16777216 bytes, linear)
    [    0.000000] Inode-cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
    [    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 4128768
    [    0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
    [    0.000000] software IO TLB: area num 2.
    [    0.000000] software IO TLB: mapped [mem 0x00000000fbfff000-0x00000000fffff000] (64MB)
    [    0.000000] Memory: 15267576K/16777216K available (12352K kernel code, 1442K rwdata, 4400K rodata, 2752K init, 506K bss, 592136K reserved, 917504K cma-reserved)
    [    0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1
    [    0.000000] rcu: Preemptible hierarchical RCU implementation.
    [    0.000000] rcu: 	RCU event tracing is enabled.
    [    0.000000] rcu: 	RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=2.
    [    0.000000] 	Trampoline variant of Tasks RCU enabled.
    [    0.000000] 	Tracing variant of Tasks RCU enabled.
    [    0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
    [    0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=2
    [    0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
    [    0.000000] GICv3: GIC: Using split EOI/Deactivate mode
    [    0.000000] GICv3: 960 SPIs implemented
    [    0.000000] GICv3: 0 Extended SPIs implemented
    [    0.000000] Root IRQ handler: gic_handle_irq
    [    0.000000] GICv3: GICv3 features: 16 PPIs
    [    0.000000] GICv3: CPU0: found redistributor 0 region 0:0x0000000001900000
    [    0.000000] ITS [mem 0x01820000-0x0182ffff]
    [    0.000000] GIC: enabling workaround for ITS: Socionext Synquacer pre-ITS
    [    0.000000] ITS@0x0000000001820000: Devices Table too large, reduce ids 20->19
    [    0.000000] ITS@0x0000000001820000: allocated 524288 Devices @880800000 (flat, esz 8, psz 64K, shr 0)
    [    0.000000] ITS: using cache flushing for cmd queue
    [    0.000000] GICv3: using LPI property table @0x0000000880040000
    [    0.000000] GIC: using cache flushing for LPI property table
    [    0.000000] GICv3: CPU0: using allocated LPI pending table @0x0000000880050000
    [    0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
    [    0.000000] arch_timer: cp15 timer(s) running at 200.00MHz (phys).
    [    0.000000] clocksource: arch_sys_counter: mask: 0x3ffffffffffffff max_cycles: 0x2e2049d3e8, max_idle_ns: 440795210634 ns
    [    0.000000] sched_clock: 58 bits at 200MHz, resolution 5ns, wraps every 4398046511102ns
    [    0.008411] Console: colour dummy device 80x25
    [    0.012991] Calibrating delay loop (skipped), value calculated using timer frequency.. 400.00 BogoMIPS (lpj=800000)
    [    0.023681] pid_max: default: 32768 minimum: 301
    [    0.028454] LSM: initializing lsm=capability,integrity
    [    0.033800] Mount-cache hash table entries: 32768 (order: 6, 262144 bytes, linear)
    [    0.041593] Mountpoint-cache hash table entries: 32768 (order: 6, 262144 bytes, linear)
    [    0.050805] RCU Tasks: Setting shift to 1 and lim to 1 rcu_task_cb_adjust=1.
    [    0.058084] RCU Tasks Trace: Setting shift to 1 and lim to 1 rcu_task_cb_adjust=1.
    [    0.065960] rcu: Hierarchical SRCU implementation.
    [    0.070872] rcu: 	Max phase no-delay instances is 1000.
    [    0.076602] Platform MSI: msi-controller@1820000 domain created
    [    0.082834] PCI/MSI: /bus@100000/interrupt-controller@1800000/msi-controller@1820000 domain created
    [    0.092262] EFI services will not be available.
    [    0.097044] smp: Bringing up secondary CPUs ...
    [    0.110177] Detected PIPT I-cache on CPU1
    [    0.110232] GICv3: CPU1: found redistributor 1 region 0:0x0000000001920000
    [    0.110247] GICv3: CPU1: using allocated LPI pending table @0x0000000880060000
    [    0.110281] CPU1: Booted secondary processor 0x0000000001 [0x411fd080]
    [    0.110349] smp: Brought up 1 node, 2 CPUs
    [    0.139751] SMP: Total of 2 processors activated.
    [    0.144565] CPU features: detected: 32-bit EL0 Support
    [    0.149832] CPU features: detected: CRC32 instructions
    [    0.155120] CPU: All CPU(s) started at EL2
    [    0.159310] alternatives: applying system-wide alternatives
    [    0.165990] devtmpfs: initialized
    [    0.176811] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
    [    0.186814] futex hash table entries: 512 (order: 3, 32768 bytes, linear)
    [    0.204900] pinctrl core: initialized pinctrl subsystem
    [    0.210616] DMI not present or invalid.
    [    0.214905] NET: Registered PF_NETLINK/PF_ROUTE protocol family
    [    0.221660] DMA: preallocated 2048 KiB GFP_KERNEL pool for atomic allocations
    [    0.229331] DMA: preallocated 2048 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
    [    0.237687] DMA: preallocated 2048 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
    [    0.245926] audit: initializing netlink subsys (disabled)
    [    0.251567] audit: type=2000 audit(0.160:1): state=initialized audit_enabled=0 res=1
    [    0.251788] thermal_sys: Registered thermal governor 'step_wise'
    [    0.259507] thermal_sys: Registered thermal governor 'power_allocator'
    [    0.265682] cpuidle: using governor menu
    [    0.276446] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
    [    0.283427] ASID allocator initialised with 65536 entries
    [    0.296635] platform 4800000.dsi: Fixed dependency cycle(s) with /bus@100000/dss@4a00000
    [    0.304958] platform 4800000.dsi: Fixed dependency cycle(s) with /bus@100000/dsi@4800000/panel@0
    [    0.314230] platform 4800000.dsi: Fixed dependency cycle(s) with /bus@100000/dss@4a00000
    [    0.322552] platform 4a00000.dss: Fixed dependency cycle(s) with /bus@100000/dsi@4800000
    [    0.331703] Modules: 27360 pages in range for non-PLT usage
    [    0.331709] Modules: 518880 pages in range for PLT usage
    [    0.337901] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
    [    0.350288] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
    [    0.356702] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
    [    0.363648] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
    [    0.370061] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
    [    0.377007] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
    [    0.383420] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
    [    0.390366] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
    [    0.397622] k3-chipinfo 43000014.chipid: Family:J721S2 rev:SR1.0 JTAGID[0x0bb7502f] Detected
    [    0.406749] iommu: Default domain type: Translated
    [    0.411680] iommu: DMA domain TLB invalidation policy: strict mode
    [    0.418156] SCSI subsystem initialized
    [    0.422107] libata version 3.00 loaded.
    [    0.422191] usbcore: registered new interface driver usbfs
    [    0.427823] usbcore: registered new interface driver hub
    [    0.433276] usbcore: registered new device driver usb
    [    0.438688] pps_core: LinuxPPS API ver. 1 registered
    [    0.443771] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
    [    0.453126] PTP clock support registered
    [    0.457234] EDAC MC: Ver: 3.0.0
    [    0.460711] scmi_core: SCMI protocol bus registered
    [    0.465865] FPGA manager framework
    [    0.469384] Advanced Linux Sound Architecture Driver Initialized.
    [    0.476097] vgaarb: loaded
    [    0.479049] clocksource: Switched to clocksource arch_sys_counter
    [    0.485442] VFS: Disk quotas dquot_6.6.0
    [    0.489481] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
    [    0.499914] NET: Registered PF_INET protocol family
    [    0.505285] IP idents hash table entries: 262144 (order: 9, 2097152 bytes, linear)
    [    0.518180] tcp_listen_portaddr_hash hash table entries: 8192 (order: 5, 131072 bytes, linear)
    [    0.527117] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
    [    0.535067] TCP established hash table entries: 131072 (order: 8, 1048576 bytes, linear)
    [    0.543763] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
    [    0.552403] TCP: Hash tables configured (established 131072 bind 65536)
    [    0.559312] UDP hash table entries: 8192 (order: 6, 262144 bytes, linear)
    [    0.566455] UDP-Lite hash table entries: 8192 (order: 6, 262144 bytes, linear)
    [    0.574139] NET: Registered PF_UNIX/PF_LOCAL protocol family
    [    0.580306] RPC: Registered named UNIX socket transport module.
    [    0.586382] RPC: Registered udp transport module.
    [    0.591194] RPC: Registered tcp transport module.
    [    0.596005] RPC: Registered tcp-with-tls transport module.
    [    0.601617] RPC: Registered tcp NFSv4.1 backchannel transport module.
    [    0.608213] NET: Registered PF_XDP protocol family
    [    0.613129] PCI: CLS 0 bytes, default 64
    [    0.617834] Initialise system trusted keyrings
    [    0.622518] workingset: timestamp_bits=46 max_order=22 bucket_order=0
    [    0.629313] squashfs: version 4.0 (2009/01/31) Phillip Lougher
    [    0.635453] NFS: Registering the id_resolver key type
    [    0.640645] Key type id_resolver registered
    [    0.644926] Key type id_legacy registered
    [    0.649037] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
    [    0.655900] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
    [    0.677134] Key type asymmetric registered
    [    0.681326] Asymmetric key parser 'x509' registered
    [    0.686348] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 244)
    [    0.694013] io scheduler mq-deadline registered
    [    0.698670] io scheduler kyber registered
    [    0.702792] io scheduler bfq registered
    [    0.708552] pinctrl-single 4301c000.pinctrl: 13 pins, size 52
    [    0.714541] pinctrl-single 4301c038.pinctrl: 11 pins, size 44
    [    0.720523] pinctrl-single 4301c068.pinctrl: 72 pins, size 288
    [    0.726616] pinctrl-single 4301c190.pinctrl: 1 pins, size 4
    [    0.732436] pinctrl-single 11c000.pinctrl: 72 pins, size 288
    [    0.738525] pinctrl-single 104200.pinctrl: 20 pins, size 80
    [    0.744300] pinctrl-single 104280.pinctrl: 8 pins, size 32
    [    0.753361] Serial: 8250/16550 driver, 12 ports, IRQ sharing enabled
    [    0.765183] loop: module loaded
    [    0.769030] megasas: 07.725.01.00-rc1
    [    0.774638] tun: Universal TUN/TAP device driver, 1.6
    [    0.780414] VFIO - User Level meta-driver version: 0.3
    [    0.786262] usbcore: registered new interface driver usb-storage
    [    0.792762] i2c_dev: i2c /dev entries driver
    [    0.797762] sdhci: Secure Digital Host Controller Interface driver
    [    0.804096] sdhci: Copyright(c) Pierre Ossman
    [    0.808660] sdhci-pltfm: SDHCI platform and OF driver helper
    [    0.814749] ledtrig-cpu: registered to indicate activity on CPUs
    [    0.821055] SMCCC: SOC_ID: ARCH_SOC_ID not implemented, skipping ....
    [    0.828056] usbcore: registered new interface driver usbhid
    [    0.833768] usbhid: USB HID core driver
    [    0.838506] hw perfevents: enabled with armv8_cortex_a72 PMU driver, 7 counters available
    [    0.847182] optee: probing for conduit method.
    [    0.851744] optee: revision 4.2 (12d7c4ee)
    [    0.868233] optee: dynamic shared memory is enabled
    [    0.877890] random: crng init done
    [    0.881443] optee: initialized driver
    [    0.886497] Initializing XFRM netlink socket
    [    0.890905] NET: Registered PF_PACKET protocol family
    [    0.896125] Key type dns_resolver registered
    [    0.904073] registered taskstats version 1
    [    0.908342] Loading compiled-in X.509 certificates
    [    0.919833] ti-sci 44083000.system-controller: ABI: 4.0 (firmware rev 0x000a '10.0.8--v10.00.08 (Fiery Fox)')
    [    0.972328] omap_i2c 42120000.i2c: bus 0 rev0.12 at 400 kHz
    [    0.978726] omap_i2c 2000000.i2c: bus 1 rev0.12 at 400 kHz
    [    0.984545] ti-sci-intr 42200000.interrupt-controller: Interrupt Router 125 domain created
    [    0.993159] ti-sci-intr bus@100000:interrupt-controller@a00000: Interrupt Router 148 domain created
    [    1.002523] ti-sci-intr 310e0000.interrupt-controller: Interrupt Router 227 domain created
    [    1.011199] ti-sci-inta 33d00000.msi-controller: Interrupt Aggregator domain 265 created
    [    1.021707] ti-udma 311a0000.dma-controller: Number of rings: 48
    [    1.028684] ti-udma 311a0000.dma-controller: Channels: 24 (bchan: 0, tchan: 8, rchan: 16)
    [    1.038105] k3-ringacc 2b800000.ringacc: Ring Accelerator probed rings:286, gp-rings[96,20] sci-dev-id:272
    [    1.048012] k3-ringacc 2b800000.ringacc: dma-ring-reset-quirk: disabled
    [    1.054784] k3-ringacc 2b800000.ringacc: RA Proxy rev. 66349100, num_proxies:64
    [    1.064225] k3-ringacc 3c000000.ringacc: Ring Accelerator probed rings:1024, gp-rings[878,128] sci-dev-id:259
    [    1.074413] k3-ringacc 3c000000.ringacc: dma-ring-reset-quirk: disabled
    [    1.081185] k3-ringacc 3c000000.ringacc: RA Proxy rev. 66349100, num_proxies:64
    [    1.089388] 2810000.serial: ttyS1 at MMIO 0x2810000 (irq = 228, base_baud = 3000000) is a 8250
    [    1.098950] 2830000.serial: ttyS3 at MMIO 0x2830000 (irq = 229, base_baud = 3000000) is a 8250
    [    1.107856] printk: console [ttyS3] enabled
    [    1.116384] printk: bootconsole [ns16550a0] disabled
    [    1.127716] davinci_mdio 46000f00.mdio: Configuring MDIO in manual mode
    [    1.171052] davinci_mdio 46000f00.mdio: davinci mdio revision 9.7, bus freq 1000000
    [    1.181087] davinci_mdio 46000f00.mdio: phy[0]: device 46000f00.mdio:00, driver TI DP83867
    [    1.189365] am65-cpsw-nuss 46000000.ethernet: initializing am65 cpsw nuss version 0x6BA02102, cpsw version 0x6BA82102 Ports: 2 quirks:00000000
    [    1.202227] am65-cpsw-nuss 46000000.ethernet: initialized cpsw ale version 1.4
    [    1.209436] am65-cpsw-nuss 46000000.ethernet: ALE Table size 64
    [    1.215768] am65-cpsw-nuss 46000000.ethernet: CPTS ver 0x4e8a010b, freq:500000000, add_val:1 pps:0
    [    1.226301] am65-cpts 310d0000.cpts: CPTS ver 0x4e8a010c, freq:200000000, add_val:4 pps:0
    [    1.234970] omap-mailbox 31f80000.mailbox: omap mailbox rev 0x66fca100
    [    1.241835] omap-mailbox 31f81000.mailbox: omap mailbox rev 0x66fca100
    [    1.248713] omap-mailbox 31f82000.mailbox: omap mailbox rev 0x66fca100
    [    1.255545] omap-mailbox 31f84000.mailbox: omap mailbox rev 0x66fca100
    [    1.265545] ti-udma 285c0000.dma-controller: Channels: 26 (tchan: 13, rchan: 13, gp-rflow: 8)
    [    1.275967] ti-udma 31150000.dma-controller: Channels: 60 (tchan: 30, rchan: 30, gp-rflow: 16)
    [    1.286343] davinci_mdio 46000f00.mdio: Configuring MDIO in manual mode
    [    1.331052] davinci_mdio 46000f00.mdio: davinci mdio revision 9.7, bus freq 1000000
    [    1.341128] davinci_mdio 46000f00.mdio: phy[0]: device 46000f00.mdio:00, driver TI DP83867
    [    1.349413] am65-cpsw-nuss 46000000.ethernet: initializing am65 cpsw nuss version 0x6BA02102, cpsw version 0x6BA82102 Ports: 2 quirks:00000000
    [    1.362279] am65-cpsw-nuss 46000000.ethernet: initialized cpsw ale version 1.4
    [    1.369491] am65-cpsw-nuss 46000000.ethernet: ALE Table size 64
    [    1.375770] am65-cpsw-nuss 46000000.ethernet: CPTS ver 0x4e8a010b, freq:500000000, add_val:1 pps:0
    [    1.390787] am65-cpsw-nuss 46000000.ethernet: set new flow-id-base 48
    [    1.400713] mmc0: CQHCI version 5.10
    [    1.402831] clk: Disabling unused clocks
    [    1.415025] ALSA device list:
    [    1.418060]   No soundcards found.
    [    1.443080] mmc0: SDHCI controller on 4fb0000.mmc [4fb0000.mmc] using ADMA 64-bit
    [    1.450730] Waiting for root device PARTUUID=9dadd190-02...
    [    1.485663] mmc0: new high speed SDHC card at address aaaa
    [    1.491568] mmcblk0: mmc0:aaaa SC16G 14.8 GiB
    [    1.500402]  mmcblk0: p1 p2
    [    1.536205] EXT4-fs (mmcblk0p2): mounted filesystem d88879a7-aaa7-46a6-ab32-21f4d3c680cd r/w with ordered data mode. Quota mode: none.
    [    1.548323] VFS: Mounted root (ext4 filesystem) on device 179:2.
    [    1.564766] devtmpfs: mounted
    [    1.568815] Freeing unused kernel memory: 2752K
    [    1.573473] Run /sbin/init as init process
    [    1.577564]   with arguments:
    [    1.577568]     /sbin/init
    [    1.577571]   with environment:
    [    1.577573]     HOME=/
    [    1.577575]     TERM=linux
    [    2.135967] systemd[1]: System time before build time, advancing clock.
    [    2.230482] NET: Registered PF_INET6 protocol family
    [    2.236174] Segment Routing with IPv6
    [    2.239857] In-situ OAM (IOAM) with IPv6
    [    2.309465] systemd[1]: systemd 255.4^ running in system mode (+PAM -AUDIT -SELINUX -APPARMOR +IMA -SMACK +SECCOMP -GCRYPT -GNUTLS -OPENSSL +ACL +BLKID -CURL -ELFUTILS -FIDO2 -IDN2 -IDN -IPTC +KMOD -LIBCRYPTSETUP +LIBFDISK -PCRE2 -PWQUALITY -P11KIT -QRENCODE -TPM2 -BZIP2 -LZ4 -XZ -ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
    [    2.341280] systemd[1]: Detected architecture arm64.
    [    2.372670] systemd[1]: Hostname set to <am68-sk>.
    [    2.490504] systemd-sysv-generator[86]: SysV service '/etc/init.d/edgeai-launcher.sh' lacks a native systemd unit file. ~ Automatically generating a unit file for compatibility. Please update package to include a native systemd unit file, in order to make it safe, robust and future-proof. ! This compatibility logic is deprecated, expect removal soon. !
    [    2.672435] systemd[1]: /usr/lib/systemd/system/bt-enable.service:9: Standard output type syslog is obsolete, automatically updating to journal. Please update your unit file, and consider removing the setting altogether.
    [    2.745220] systemd[1]: /etc/systemd/system/sync-clocks.service:11: Standard output type syslog is obsolete, automatically updating to journal. Please update your unit file, and consider removing the setting altogether.
    [    2.807932] systemd[1]: Queued start job for default target Graphical Interface.
    [    2.858462] systemd[1]: Created slice Slice /system/getty.
    [    2.880479] systemd[1]: Created slice Slice /system/modprobe.
    [    2.904352] systemd[1]: Created slice Slice /system/serial-getty.
    [    2.928081] systemd[1]: Created slice User and Session Slice.
    [    2.951328] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
    [    2.975225] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
    [    2.999142] systemd[1]: Expecting device /dev/ttyS3...
    [    3.015164] systemd[1]: Reached target Path Units.
    [    3.031123] systemd[1]: Reached target Remote File Systems.
    [    3.051114] systemd[1]: Reached target Slice Units.
    [    3.067120] systemd[1]: Reached target Swaps.
    [    3.110614] systemd[1]: Listening on RPCbind Server Activation Socket.
    [    3.135259] systemd[1]: Reached target RPC Port Mapper.
    [    3.160736] systemd[1]: Listening on Process Core Dump Socket.
    [    3.183370] systemd[1]: Listening on initctl Compatibility Named Pipe.
    [    3.207787] systemd[1]: Listening on Journal Audit Socket.
    [    3.231489] systemd[1]: Listening on Journal Socket (/dev/log).
    [    3.255497] systemd[1]: Listening on Journal Socket.
    [    3.275535] systemd[1]: Listening on Network Service Netlink Socket.
    [    3.306886] systemd[1]: Listening on udev Control Socket.
    [    3.327445] systemd[1]: Listening on udev Kernel Socket.
    [    3.347434] systemd[1]: Listening on User Database Manager Socket.
    [    3.395312] systemd[1]: Mounting Huge Pages File System...
    [    3.417635] systemd[1]: Mounting POSIX Message Queue File System...
    [    3.467014] systemd[1]: Mounting Kernel Debug File System...
    [    3.483467] systemd[1]: Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
    [    3.501782] systemd[1]: Mounting Temporary Directory /tmp...
    [    3.528863] systemd[1]: Starting Create List of Static Device Nodes...
    [    3.575711] systemd[1]: Starting Load Kernel Module configfs...
    [    3.595767] systemd[1]: Starting Load Kernel Module drm...
    [    3.619787] systemd[1]: Starting Load Kernel Module fuse...
    [    3.642704] systemd[1]: Starting Start psplash boot splash screen...
    [    3.673416] fuse: init (API version 7.39)
    [    3.685351] systemd[1]: Starting RPC Bind...
    [    3.703533] systemd[1]: File System Check on Root Device was skipped because of an unmet condition check (ConditionPathIsReadWrite=!/).
    [    3.731703] systemd[1]: Starting Journal Service...
    [    3.783681] systemd[1]: Starting Load Kernel Modules...
    [    3.820993] systemd-journald[105]: Collecting audit messages is enabled.
    [    3.831603] systemd[1]: Starting Generate network units from Kernel command line...
    [    3.862799] systemd[1]: Starting Remount Root and Kernel File Systems...
    [    3.909114] systemd[1]: Starting Coldplug All udev Devices...
    [    3.933464] systemd[1]: Started RPC Bind.
    [    3.937915] EXT4-fs (mmcblk0p2): re-mounted d88879a7-aaa7-46a6-ab32-21f4d3c680cd r/w. Quota mode: none.
    [    3.960600] systemd[1]: Started Journal Service.
    [    4.571036] systemd-journald[105]: Received client request to flush runtime journal.
    [    4.784840] audit: type=1334 audit(1709054766.644:2): prog-id=6 op=LOAD
    [    4.791921] audit: type=1334 audit(1709054766.652:3): prog-id=7 op=LOAD
    [    5.020009] audit: type=1334 audit(1709054766.876:4): prog-id=8 op=LOAD
    [    5.065453] audit: type=1334 audit(1709054766.924:5): prog-id=9 op=LOAD
    [    5.146383] audit: type=1334 audit(1709054767.004:6): prog-id=10 op=LOAD
    [    5.156128] audit: type=1334 audit(1709054767.012:7): prog-id=11 op=LOAD
    [    5.171250] audit: type=1334 audit(1709054767.012:8): prog-id=12 op=LOAD
    [    5.827520] audit: type=1334 audit(1737742319.826:9): prog-id=13 op=LOAD
    [    5.967799] mc: Linux media interface: v0.10
    [    6.072164] omap_rng 4e10000.rng: Random Number Generator ver. 241b34c
    [    6.099692] videodev: Linux video capture interface: v2.00
    [    6.108929] platform 41000000.r5f: R5F core may have been powered on by a different host, programmed state (0) != actual state (1)
    [    6.150550] cdns-dsi 4800000.dsi: Fixed dependency cycle(s) with /bus@100000/dsi@4800000/panel@0
    [    6.203241] mipi-dsi 4800000.dsi.0: Fixed dependency cycle(s) with /bus@100000/dsi@4800000
    [    6.214621] platform 41000000.r5f: configured R5F for IPC-only mode
    [    6.224332] dbus-broker-lau[255]: memfd_create() called without MFD_EXEC or MFD_NOEXEC_SEAL set
    [    6.276759] platform 41000000.r5f: assigned reserved memory node r5f-dma-memory@a0000000
    [    6.289177] remoteproc remoteproc0: 41000000.r5f is available
    [    6.304544] remoteproc remoteproc0: attaching to 41000000.r5f
    [    6.371194] platform 41000000.r5f: R5F core initialized in IPC-only mode
    [    6.391076] audit: type=1334 audit(1737742320.386:10): prog-id=14 op=LOAD
    [    6.410436] audit: type=1334 audit(1737742320.398:11): prog-id=15 op=LOAD
    [    6.431098] audit: type=1334 audit(1737742320.398:12): prog-id=16 op=LOAD
    [    6.479725] rproc-virtio rproc-virtio.0.auto: assigned reserved memory node r5f-dma-memory@a0000000
    [    6.492894] virtio_rpmsg_bus virtio0: rpmsg host is online
    [    6.503412] audit: type=1334 audit(1737742320.502:13): prog-id=17 op=LOAD
    [    6.503891] virtio_rpmsg_bus virtio0: creating channel ti.ipc4.ping-pong addr 0xd
    [    6.517872] virtio_rpmsg_bus virtio0: creating channel rpmsg_chrdev addr 0xe
    [    6.585345] rproc-virtio rproc-virtio.0.auto: registered virtio0 (type 7)
    [    6.593078] remoteproc remoteproc0: remote processor 41000000.r5f is now attached
    [    6.850831] vdec 4210000.video-codec: Added wave5 driver with caps: 'ENCODE' 'DECODE'
    [    6.858885] vdec 4210000.video-codec: Product Code:      0x521c
    [    6.866327] vdec 4210000.video-codec: Firmware Revision: 320127
    [    6.946999] feiyang_dsi_probe
    [    6.953946] drm_panel_of_backlight: 0
    [    6.964067] [drm] Initialized tidss 1.0.0 20180215 for 4a00000.dss on minor 0
    [    6.982584] feiyang_get_modes
    [    6.989230] tidss 4a00000.dss: [drm] Cannot find any crtc or sizes
    [    7.004666] feiyang_get_modes
    [    7.004696] tidss 4a00000.dss: [drm] Cannot find any crtc or sizes
    [    7.244366] cfg80211: Loading compiled-in X.509 certificates for regulatory database
    [    7.274421] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
    [    7.280447] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
    [    7.498564] Bluetooth: Core ver 2.22
    [    7.502742] NET: Registered PF_BLUETOOTH protocol family
    [    7.508344] Bluetooth: HCI device and connection manager initialized
    [    7.514927] Bluetooth: HCI socket layer initialized
    [    7.520044] Bluetooth: L2CAP socket layer initialized
    [    7.525233] Bluetooth: SCO socket layer initialized
    [    7.704575] am65-cpsw-nuss 46000000.ethernet eth0: PHY [46000f00.mdio:00] driver [TI DP83867] (irq=POLL)
    [    7.731015] am65-cpsw-nuss 46000000.ethernet eth0: configuring for phy/rgmii-rxid link mode
    [    8.964068] audit: type=1006 audit(1737742322.962:14): pid=413 uid=0 old-auid=4294967295 auid=1000 tty=(none) old-ses=4294967295 ses=1 res=1
    [    8.976736] audit: type=1300 audit(1737742322.962:14): arch=c00000b7 syscall=64 success=yes exit=4 a0=8 a1=ffffc05d9028 a2=4 a3=1 items=0 ppid=1 pid=413 auid=1000 uid=0 gid=0 euid=0 suid=0 fsuid=0 egid=0 sgid=0 fsgid=0 tty=(none) ses=1 comm="(systemd)" exe="/usr/lib/systemd/systemd-executor" key=(null)
    [    9.003869] audit: type=1327 audit(1737742322.962:14): proctitle="(systemd)"
    [    9.552257] audit: type=1006 audit(1737742323.550:15): pid=399 uid=0 old-auid=4294967295 auid=1000 tty=tty7 old-ses=4294967295 ses=2 res=1
    [    9.569394] audit: type=1300 audit(1737742323.550:15): arch=c00000b7 syscall=64 success=yes exit=4 a0=8 a1=ffffe9d08398 a2=4 a3=1 items=0 ppid=1 pid=399 auid=1000 uid=0 gid=0 euid=0 suid=0 fsuid=0 egid=0 sgid=0 fsgid=0 tty=tty7 ses=2 comm="(weston)" exe="/usr/lib/systemd/systemd-executor" key=(null)
    [   11.840113] am65-cpsw-nuss 46000000.ethernet eth0: Link is Up - 1Gbps/Full - flow control rx/tx
    [   11.950009] feiyang_get_modes
    [   12.577124] feiyang_get_modes
    [   14.446372] kauditd_printk_skb: 1 callbacks suppressed
    [   14.446379] audit: type=1701 audit(1737742328.442:16): auid=4294967295 uid=0 gid=0 ses=4294967295 pid=584 comm="edgeai-gui-app" exe="/usr/bin/edgeai-gui-app" sig=11 res=1
    [   14.476253] audit: type=1334 audit(1737742328.474:17): prog-id=18 op=LOAD
    [   14.483820] audit: type=1334 audit(1737742328.482:18): prog-id=19 op=LOAD
    [   14.491471] audit: type=1334 audit(1737742328.482:19): prog-id=20 op=LOAD
    [   14.867254] audit: type=1334 audit(1737742328.866:20): prog-id=20 op=UNLOAD
    [   14.874565] audit: type=1334 audit(1737742328.866:21): prog-id=19 op=UNLOAD
    [   14.882142] audit: type=1334 audit(1737742328.866:22): prog-id=18 op=UNLOAD
    [   15.071678] feiyang_get_modes
    [   26.330016] audit: type=1006 audit(1737742340.326:23): pid=1096 uid=0 old-auid=4294967295 auid=0 tty=(none) old-ses=4294967295 ses=3 res=1
    [   26.342595] audit: type=1300 audit(1737742340.326:23): arch=c00000b7 syscall=64 success=yes exit=1 a0=8 a1=ffffee02e578 a2=1 a3=1 items=0 ppid=1 pid=1096 auid=0 uid=0 gid=0 euid=0 suid=0 fsuid=0 egid=0 sgid=0 fsgid=0 tty=(none) ses=3 comm="(systemd)" exe="/usr/lib/systemd/systemd-executor" key=(null)
    [   26.369292] audit: type=1327 audit(1737742340.326:23): proctitle="(systemd)"
    [   26.376393] audit: type=1334 audit(1737742340.342:24): prog-id=21 op=LOAD
    [   26.383359] audit: type=1300 audit(1737742340.342:24): arch=c00000b7 syscall=280 success=yes exit=8 a0=5 a1=fffff585e8d8 a2=90 a3=0 items=0 ppid=1 pid=1096 auid=0 uid=0 gid=0 euid=0 suid=0 fsuid=0 egid=0 sgid=0 fsgid=0 tty=(none) ses=3 comm="systemd" exe="/usr/lib/systemd/systemd" key=(null)
    [   26.409217] audit: type=1327 audit(1737742340.342:24): proctitle="(systemd)"
    [   26.416342] audit: type=1334 audit(1737742340.370:25): prog-id=21 op=UNLOAD
    [   26.423430] audit: type=1300 audit(1737742340.370:25): arch=c00000b7 syscall=57 success=yes exit=0 a0=8 a1=1 a2=0 a3=ffffb1183c60 items=0 ppid=1 pid=1096 auid=0 uid=0 gid=0 euid=0 suid=0 fsuid=0 egid=0 sgid=0 fsgid=0 tty=(none) ses=3 comm="systemd" exe="/usr/lib/systemd/systemd" key=(null)
    [   26.449088] audit: type=1327 audit(1737742340.370:25): proctitle="(systemd)"
    [   26.456173] audit: type=1334 audit(1737742340.370:26): prog-id=22 op=LOAD
    [   26.904718] feiyang_get_modes
    

    Why can't DSS/DSI support some timings/clock frequencies?

    Thank you so much for your time and help!

  • Hi Amandio,

    Glad to hear you made progress!

    It's great to see there is output on the screen. Although, clock not having activity is concerning, as it should have activity.

    As for clock assignments, each video port can be routed to 1 or 2 different interfaces, so there is some flexibility. Default devicetree assumes the connections used in SK board. 

    As for the distortion, could you share two things:

    • What are the current timing parameters that are programmed to give the distorted output (in case they have changed)?
    • Could you share the output from "k3conf dump clock" again for the current timing parameters?

    It could be that the DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK clock is not getting the correct value.

    Regards,

    Takuma

  • Hi Takuma,

    These were the timings used:

    Horizontal: 1024 + 160 + 80 + 100 = 1364

    Vertical: 600 + 17 + 15 + 3 = 635

    This leads to a calculated clock value of 51206 (kHz) due to (1364 x 635 x 60)/1000

    Here is the output of k3conf:

    |------------------------------------------------------------------------------|
    | VERSION INFO                                                                 |
    |------------------------------------------------------------------------------|
    | K3CONF | (version 0.3-nogit built Thu Jul 25 14:13:02 UTC 2024)              |
    | SoC    | J721S2 SR1.0                                                        |
    | SYSFW  | ABI: 4.0 (firmware version 0x000a '10.0.8--v10.00.08 (Fiery Fox))') |
    |------------------------------------------------------------------------------|
    
    |--------------------------------------------------------------------------------------------------------------------------------------------------|
    | Device ID | Clock ID | Clock Name                                                                        | Status              | Clock Frequency |
    |--------------------------------------------------------------------------------------------------------------------------------------------------|
    |     4     |     0    | DEV_A72SS0_ARM_CLK_CLK                                                            | CLK_STATE_READY     | 2000000000      |
    |     4     |     1    | DEV_A72SS0_MSMC_CLK                                                               | CLK_STATE_READY     | 1000000000      |
    |     4     |     2    | DEV_A72SS0_PLL_CTRL_CLK                                                           | CLK_STATE_READY     | 500000000       |
    |     4     |     6    | DEV_A72SS0_A72_DIVH_CLK8_OBSCLK_OUT_CLK                                           | CLK_STATE_READY     | 0               |
    |   202     |     0    | DEV_A72SS0_CORE0_ARM_CLK_CLK                                                      | CLK_STATE_READY     | 2000000000      |
    |   203     |     0    | DEV_A72SS0_CORE1_ARM_CLK_CLK                                                      | CLK_STATE_READY     | 2000000000      |
    |   134     |     0    | DEV_AGGR_ATB0_DBG_CLK                                                             | CLK_STATE_READY     | 250000000       |
    |     2     |     0    | DEV_ATL0_ATL_IO_PORT_ATCLK_OUT                                                    | CLK_STATE_READY     | 0               |
    |     2     |     1    | DEV_ATL0_ATL_IO_PORT_ATCLK_OUT_1                                                  | CLK_STATE_READY     | 0               |
    |     2     |     2    | DEV_ATL0_ATL_IO_PORT_ATCLK_OUT_2                                                  | CLK_STATE_READY     | 0               |
    |     2     |     3    | DEV_ATL0_ATL_IO_PORT_ATCLK_OUT_3                                                  | CLK_STATE_READY     | 0               |
    |     2     |     4    | DEV_ATL0_ATL_CLK                                                                  | CLK_STATE_READY     | 294912000       |
    |     2     |     5    | DEV_ATL0_ATL_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT1_CLK                         | CLK_STATE_READY     | 294912000       |
    |     2     |     6    | DEV_ATL0_ATL_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK                         | CLK_STATE_READY     | 200000000       |
    |     2     |     9    | DEV_ATL0_ATL_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT7_CLK                       | CLK_STATE_READY     | 200000000       |
    |     2     |    10    | DEV_ATL0_ATL_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                               | CLK_STATE_READY     | 0               |
    |     2     |    11    | DEV_ATL0_ATL_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT                                   | CLK_STATE_READY     | 0               |
    |     2     |    13    | DEV_ATL0_VBUS_CLK                                                                 | CLK_STATE_READY     | 250000000       |
    |     2     |    14    | DEV_ATL0_ATL_IO_PORT_AWS                                                          | CLK_STATE_READY     | 0               |
    |     2     |    15    | DEV_ATL0_ATL_IO_PORT_AWS_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT                      | CLK_STATE_READY     | 0               |
    |     2     |    16    | DEV_ATL0_ATL_IO_PORT_AWS_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT                      | CLK_STATE_READY     | 0               |
    |     2     |    17    | DEV_ATL0_ATL_IO_PORT_AWS_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT_DUP0                 | CLK_STATE_READY     | 0               |
    |     2     |    18    | DEV_ATL0_ATL_IO_PORT_AWS_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT_DUP0                 | CLK_STATE_READY     | 0               |
    |     2     |    19    | DEV_ATL0_ATL_IO_PORT_AWS_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT_DUP0                 | CLK_STATE_READY     | 0               |
    |     2     |    27    | DEV_ATL0_ATL_IO_PORT_AWS_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT_DUP0                 | CLK_STATE_READY     | 0               |
    |     2     |    28    | DEV_ATL0_ATL_IO_PORT_AWS_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT_DUP0                 | CLK_STATE_READY     | 0               |
    |     2     |    29    | DEV_ATL0_ATL_IO_PORT_AWS_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT                      | CLK_STATE_READY     | 0               |
    |     2     |    30    | DEV_ATL0_ATL_IO_PORT_AWS_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT                      | CLK_STATE_READY     | 0               |
    |     2     |    31    | DEV_ATL0_ATL_IO_PORT_AWS_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT                      | CLK_STATE_READY     | 0               |
    |     2     |    39    | DEV_ATL0_ATL_IO_PORT_AWS_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT                     | CLK_STATE_READY     | 0               |
    |     2     |    40    | DEV_ATL0_ATL_IO_PORT_AWS_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT                     | CLK_STATE_READY     | 0               |
    |     2     |    47    | DEV_ATL0_ATL_IO_PORT_AWS_1                                                        | CLK_STATE_READY     | 0               |
    |     2     |    48    | DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT                    | CLK_STATE_READY     | 0               |
    |     2     |    49    | DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT                    | CLK_STATE_READY     | 0               |
    |     2     |    50    | DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT_DUP0               | CLK_STATE_READY     | 0               |
    |     2     |    51    | DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT_DUP0               | CLK_STATE_READY     | 0               |
    |     2     |    52    | DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT_DUP0               | CLK_STATE_READY     | 0               |
    |     2     |    60    | DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT_DUP0               | CLK_STATE_READY     | 0               |
    |     2     |    61    | DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT_DUP0               | CLK_STATE_READY     | 0               |
    |     2     |    62    | DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT                    | CLK_STATE_READY     | 0               |
    |     2     |    63    | DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT                    | CLK_STATE_READY     | 0               |
    |     2     |    64    | DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT                    | CLK_STATE_READY     | 0               |
    |     2     |    72    | DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT                   | CLK_STATE_READY     | 0               |
    |     2     |    73    | DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT                   | CLK_STATE_READY     | 0               |
    |     2     |    80    | DEV_ATL0_ATL_IO_PORT_AWS_2                                                        | CLK_STATE_READY     | 0               |
    |     2     |    81    | DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT                    | CLK_STATE_READY     | 0               |
    |     2     |    82    | DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT                    | CLK_STATE_READY     | 0               |
    |     2     |    83    | DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT_DUP0               | CLK_STATE_READY     | 0               |
    |     2     |    84    | DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT_DUP0               | CLK_STATE_READY     | 0               |
    |     2     |    85    | DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT_DUP0               | CLK_STATE_READY     | 0               |
    |     2     |    93    | DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT_DUP0               | CLK_STATE_READY     | 0               |
    |     2     |    94    | DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT_DUP0               | CLK_STATE_READY     | 0               |
    |     2     |    95    | DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT                    | CLK_STATE_READY     | 0               |
    |     2     |    96    | DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT                    | CLK_STATE_READY     | 0               |
    |     2     |    97    | DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT                    | CLK_STATE_READY     | 0               |
    |     2     |   105    | DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT                   | CLK_STATE_READY     | 0               |
    |     2     |   106    | DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT                   | CLK_STATE_READY     | 0               |
    |     2     |   113    | DEV_ATL0_ATL_IO_PORT_AWS_3                                                        | CLK_STATE_READY     | 0               |
    |     2     |   114    | DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT                    | CLK_STATE_READY     | 0               |
    |     2     |   115    | DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT                    | CLK_STATE_READY     | 0               |
    |     2     |   116    | DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT_DUP0               | CLK_STATE_READY     | 0               |
    |     2     |   117    | DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT_DUP0               | CLK_STATE_READY     | 0               |
    |     2     |   118    | DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT_DUP0               | CLK_STATE_READY     | 0               |
    |     2     |   126    | DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT_DUP0               | CLK_STATE_READY     | 0               |
    |     2     |   127    | DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT_DUP0               | CLK_STATE_READY     | 0               |
    |     2     |   128    | DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT                    | CLK_STATE_READY     | 0               |
    |     2     |   129    | DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT                    | CLK_STATE_READY     | 0               |
    |     2     |   130    | DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT                    | CLK_STATE_READY     | 0               |
    |     2     |   138    | DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT                   | CLK_STATE_READY     | 0               |
    |     2     |   139    | DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT                   | CLK_STATE_READY     | 0               |
    |     2     |   146    | DEV_ATL0_ATL_IO_PORT_BWS                                                          | CLK_STATE_READY     | 0               |
    |     2     |   147    | DEV_ATL0_ATL_IO_PORT_BWS_PARENT_MCASP_MAIN_0_MCASP_AFSR_POUT                      | CLK_STATE_READY     | 0               |
    |     2     |   148    | DEV_ATL0_ATL_IO_PORT_BWS_PARENT_MCASP_MAIN_1_MCASP_AFSR_POUT                      | CLK_STATE_READY     | 0               |
    |     2     |   149    | DEV_ATL0_ATL_IO_PORT_BWS_PARENT_MCASP_MAIN_2_MCASP_AFSR_POUT                      | CLK_STATE_READY     | 0               |
    |     2     |   150    | DEV_ATL0_ATL_IO_PORT_BWS_PARENT_MCASP_MAIN_3_MCASP_AFSR_POUT                      | CLK_STATE_READY     | 0               |
    |     2     |   151    | DEV_ATL0_ATL_IO_PORT_BWS_PARENT_MCASP_MAIN_4_MCASP_AFSR_POUT                      | CLK_STATE_READY     | 0               |
    |     2     |   159    | DEV_ATL0_ATL_IO_PORT_BWS_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT                      | CLK_STATE_READY     | 0               |
    |     2     |   160    | DEV_ATL0_ATL_IO_PORT_BWS_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT                      | CLK_STATE_READY     | 0               |
    |     2     |   161    | DEV_ATL0_ATL_IO_PORT_BWS_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT                      | CLK_STATE_READY     | 0               |
    |     2     |   162    | DEV_ATL0_ATL_IO_PORT_BWS_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT                      | CLK_STATE_READY     | 0               |
    |     2     |   163    | DEV_ATL0_ATL_IO_PORT_BWS_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT                      | CLK_STATE_READY     | 0               |
    |     2     |   171    | DEV_ATL0_ATL_IO_PORT_BWS_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT                     | CLK_STATE_READY     | 0               |
    |     2     |   172    | DEV_ATL0_ATL_IO_PORT_BWS_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT                     | CLK_STATE_READY     | 0               |
    |     2     |   179    | DEV_ATL0_ATL_IO_PORT_BWS_1                                                        | CLK_STATE_READY     | 0               |
    |     2     |   180    | DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_MCASP_MAIN_0_MCASP_AFSR_POUT                    | CLK_STATE_READY     | 0               |
    |     2     |   181    | DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_MCASP_MAIN_1_MCASP_AFSR_POUT                    | CLK_STATE_READY     | 0               |
    |     2     |   182    | DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_MCASP_MAIN_2_MCASP_AFSR_POUT                    | CLK_STATE_READY     | 0               |
    |     2     |   183    | DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_MCASP_MAIN_3_MCASP_AFSR_POUT                    | CLK_STATE_READY     | 0               |
    |     2     |   184    | DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_MCASP_MAIN_4_MCASP_AFSR_POUT                    | CLK_STATE_READY     | 0               |
    |     2     |   192    | DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT                    | CLK_STATE_READY     | 0               |
    |     2     |   193    | DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT                    | CLK_STATE_READY     | 0               |
    |     2     |   194    | DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT                    | CLK_STATE_READY     | 0               |
    |     2     |   195    | DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT                    | CLK_STATE_READY     | 0               |
    |     2     |   196    | DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT                    | CLK_STATE_READY     | 0               |
    |     2     |   204    | DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT                   | CLK_STATE_READY     | 0               |
    |     2     |   205    | DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT                   | CLK_STATE_READY     | 0               |
    |     2     |   212    | DEV_ATL0_ATL_IO_PORT_BWS_2                                                        | CLK_STATE_READY     | 0               |
    |     2     |   213    | DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_MCASP_MAIN_0_MCASP_AFSR_POUT                    | CLK_STATE_READY     | 0               |
    |     2     |   214    | DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_MCASP_MAIN_1_MCASP_AFSR_POUT                    | CLK_STATE_READY     | 0               |
    |     2     |   215    | DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_MCASP_MAIN_2_MCASP_AFSR_POUT                    | CLK_STATE_READY     | 0               |
    |     2     |   216    | DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_MCASP_MAIN_3_MCASP_AFSR_POUT                    | CLK_STATE_READY     | 0               |
    |     2     |   217    | DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_MCASP_MAIN_4_MCASP_AFSR_POUT                    | CLK_STATE_READY     | 0               |
    |     2     |   225    | DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT                    | CLK_STATE_READY     | 0               |
    |     2     |   226    | DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT                    | CLK_STATE_READY     | 0               |
    |     2     |   227    | DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT                    | CLK_STATE_READY     | 0               |
    |     2     |   228    | DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT                    | CLK_STATE_READY     | 0               |
    |     2     |   229    | DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT                    | CLK_STATE_READY     | 0               |
    |     2     |   237    | DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT                   | CLK_STATE_READY     | 0               |
    |     2     |   238    | DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT                   | CLK_STATE_READY     | 0               |
    |     2     |   245    | DEV_ATL0_ATL_IO_PORT_BWS_3                                                        | CLK_STATE_READY     | 0               |
    |     2     |   246    | DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_MCASP_MAIN_0_MCASP_AFSR_POUT                    | CLK_STATE_READY     | 0               |
    |     2     |   247    | DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_MCASP_MAIN_1_MCASP_AFSR_POUT                    | CLK_STATE_READY     | 0               |
    |     2     |   248    | DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_MCASP_MAIN_2_MCASP_AFSR_POUT                    | CLK_STATE_READY     | 0               |
    |     2     |   249    | DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_MCASP_MAIN_3_MCASP_AFSR_POUT                    | CLK_STATE_READY     | 0               |
    |     2     |   250    | DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_MCASP_MAIN_4_MCASP_AFSR_POUT                    | CLK_STATE_READY     | 0               |
    |     2     |   258    | DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT                    | CLK_STATE_READY     | 0               |
    |     2     |   259    | DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT                    | CLK_STATE_READY     | 0               |
    |     2     |   260    | DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT                    | CLK_STATE_READY     | 0               |
    |     2     |   261    | DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT                    | CLK_STATE_READY     | 0               |
    |     2     |   262    | DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT                    | CLK_STATE_READY     | 0               |
    |     2     |   270    | DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT                   | CLK_STATE_READY     | 0               |
    |     2     |   271    | DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT                   | CLK_STATE_READY     | 0               |
    |   157     |     1    | DEV_BOARD0_DSI0_TXCLKN_IN                                                         | CLK_STATE_READY     | 0               |
    |   157     |     2    | DEV_BOARD0_I2C4_SCL_OUT                                                           | CLK_STATE_READY     | 0               |
    |   157     |     4    | DEV_BOARD0_CSI0_TXCLKN_IN                                                         | CLK_STATE_READY     | 0               |
    |   157     |     5    | DEV_BOARD0_CSI0_RXCLKP_OUT                                                        | CLK_STATE_READY     | 0               |
    |   157     |     6    | DEV_BOARD0_HYP0_TXPMCLK_IN                                                        | CLK_STATE_NOT_READY | 0               |
    |   157     |     7    | DEV_BOARD0_MCAN1_RX_OUT                                                           | CLK_STATE_READY     | 0               |
    |   157     |     8    | DEV_BOARD0_MCAN17_RX_OUT                                                          | CLK_STATE_READY     | 0               |
    |   157     |     9    | DEV_BOARD0_MMC1_CLK_IN                                                            | CLK_STATE_READY     | 0               |
    |   157     |    10    | DEV_BOARD0_MCU_OBSCLK0_IN                                                         | CLK_STATE_READY     | 1000000000      |
    |   157     |    11    | DEV_BOARD0_MCU_OBSCLK0_IN_PARENT_MCU_OBSCLK_DIV_OUT0                              | CLK_STATE_READY     | 1000000000      |
    |   157     |    12    | DEV_BOARD0_MCU_OBSCLK0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT                          | CLK_STATE_READY     | 19200000        |
    |   157     |    43    | DEV_BOARD0_I2C0_SCL_IN                                                            | CLK_STATE_NOT_READY | 0               |
    |   157     |    44    | DEV_BOARD0_SPI7_CLK_OUT                                                           | CLK_STATE_READY     | 0               |
    |   157     |    45    | DEV_BOARD0_MCU_CPTS0_RFT_CLK_OUT                                                  | CLK_STATE_READY     | 0               |
    |   157     |    46    | DEV_BOARD0_MCASP3_ACLKR_IN                                                        | CLK_STATE_READY     | 0               |
    |   157     |    47    | DEV_BOARD0_AUDIO_EXT_REFCLK1_OUT                                                  | CLK_STATE_READY     | 0               |
    |   157     |    48    | DEV_BOARD0_MCU_OSPI0_DQS_OUT                                                      | CLK_STATE_READY     | 0               |
    |   157     |    49    | DEV_BOARD0_HYP0_TXFLCLK_OUT                                                       | CLK_STATE_READY     | 0               |
    |   157     |    50    | DEV_BOARD0_MCU_OSPI0_LBCLKO_OUT                                                   | CLK_STATE_READY     | 0               |
    |   157     |    51    | DEV_BOARD0_MCASP3_ACLKX_IN                                                        | CLK_STATE_READY     | 0               |
    |   157     |    52    | DEV_BOARD0_HYP0_RXPMCLK_OUT                                                       | CLK_STATE_READY     | 0               |
    |   157     |    54    | DEV_BOARD0_MCASP1_ACLKX_IN                                                        | CLK_STATE_READY     | 0               |
    |   157     |    55    | DEV_BOARD0_MCU_SPI1_CLK_IN                                                        | CLK_STATE_READY     | 0               |
    |   157     |    56    | DEV_BOARD0_MCAN9_RX_OUT                                                           | CLK_STATE_READY     | 0               |
    |   157     |    57    | DEV_BOARD0_I2C6_SCL_OUT                                                           | CLK_STATE_READY     | 0               |
    |   157     |    58    | DEV_BOARD0_MCU_SPI0_CLK_OUT                                                       | CLK_STATE_READY     | 0               |
    |   157     |    59    | DEV_BOARD0_OBSCLK1_IN                                                             | CLK_STATE_READY     | 500000000       |
    |   157     |    60    | DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK                    | CLK_STATE_READY     | 500000000       |
    |   157     |    61    | DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT0_CLK                    | CLK_STATE_READY     | 192000000       |
    |   157     |    62    | DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK                    | CLK_STATE_READY     | 600000000       |
    |   157     |    63    | DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT0_CLK                    | CLK_STATE_READY     | 250000000       |
    |   157     |    64    | DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT0_CLK                    | CLK_STATE_READY     | 196608000       |
    |   157     |    65    | DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV1_16FFT_MAIN_5_HSDIVOUT0_CLK                    | CLK_STATE_READY     | 400000000       |
    |   157     |    66    | DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV0_16FFT_MAIN_6_HSDIVOUT0_CLK                    | CLK_STATE_READY     | 800000000       |
    |   157     |    67    | DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV0_16FFT_MAIN_26_HSDIVOUT0_CLK                   | CLK_STATE_READY     | 1066500000      |
    |   157     |    72    | DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV0_16FFT_MAIN_12_HSDIVOUT0_CLK                   | CLK_STATE_READY     | 1066500000      |
    |   157     |    73    | DEV_BOARD0_OBSCLK1_IN_PARENT_OBSCLK1_MUX_OUT0                                     | CLK_STATE_READY     | 0               |
    |   157     |    74    | DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV2_16FFT_MAIN_14_HSDIVOUT0_CLK                   | CLK_STATE_READY     | 1000000000      |
    |   157     |    76    | DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK                   | CLK_STATE_READY     | 594000000       |
    |   157     |    77    | DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT0_CLK                   | CLK_STATE_READY     | 51200000        |
    |   157     |    79    | DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV1_16FFT_MAIN_19_HSDIVOUT0_CLK                   | CLK_STATE_READY     | 600000000       |
    |   157     |    85    | DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV1_16FFT_MAIN_25_HSDIVOUT0_CLK                   | CLK_STATE_READY     | 480000000       |
    |   157     |    86    | DEV_BOARD0_OBSCLK1_IN_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF3                      | CLK_STATE_READY     | 0               |
    |   157     |    87    | DEV_BOARD0_OBSCLK1_IN_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK         | CLK_STATE_READY     | 12500000        |
    |   157     |    88    | DEV_BOARD0_OBSCLK1_IN_PARENT_GLUELOGIC_LPXOSC_CLKOUT                              | CLK_STATE_READY     | 32768           |
    |   157     |    89    | DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK_DUP0               | CLK_STATE_READY     | 500000000       |
    |   157     |    90    | DEV_BOARD0_OBSCLK1_IN_PARENT_BOARD_0_HFOSC1_CLK_OUT                               | CLK_STATE_READY     | 0               |
    |   157     |    91    | DEV_BOARD0_OBSCLK1_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT                              | CLK_STATE_READY     | 19200000        |
    |   157     |    92    | DEV_BOARD0_MCU_OSPI1_LBCLKO_OUT                                                   | CLK_STATE_READY     | 0               |
    |   157     |    93    | DEV_BOARD0_MCASP3_ACLKX_OUT                                                       | CLK_STATE_READY     | 0               |
    |   157     |    95    | DEV_BOARD0_MCASP2_AFSR_OUT                                                        | CLK_STATE_READY     | 0               |
    |   157     |    96    | DEV_BOARD0_TRC_CLK_IN                                                             | CLK_STATE_READY     | 0               |
    |   157     |   100    | DEV_BOARD0_CSI1_RXCLKN_OUT                                                        | CLK_STATE_READY     | 0               |
    |   157     |   102    | DEV_BOARD0_MCASP0_ACLKX_OUT                                                       | CLK_STATE_READY     | 0               |
    |   157     |   103    | DEV_BOARD0_MCU_OSPI0_CLK_IN                                                       | CLK_STATE_READY     | 0               |
    |   157     |   105    | DEV_BOARD0_GPMC0_FCLK_MUX_IN                                                      | CLK_STATE_READY     | 133333333       |
    |   157     |   106    | DEV_BOARD0_MCU_SPI0_CLK_IN                                                        | CLK_STATE_READY     | 0               |
    |   157     |   108    | DEV_BOARD0_MCU_RGMII1_RXC_OUT                                                     | CLK_STATE_READY     | 0               |
    |   157     |   109    | DEV_BOARD0_MCASP0_AFSR_OUT                                                        | CLK_STATE_READY     | 0               |
    |   157     |   110    | DEV_BOARD0_CSI1_RXCLKP_OUT                                                        | CLK_STATE_READY     | 0               |
    |   157     |   111    | DEV_BOARD0_MCU_SYSCLKOUT0_IN                                                      | CLK_STATE_READY     | 250000000       |
    |   157     |   112    | DEV_BOARD0_SPI5_CLK_OUT                                                           | CLK_STATE_READY     | 0               |
    |   157     |   113    | DEV_BOARD0_MCU_RMII1_REF_CLK_OUT                                                  | CLK_STATE_READY     | 0               |
    |   157     |   114    | DEV_BOARD0_SPI0_CLK_OUT                                                           | CLK_STATE_READY     | 0               |
    |   157     |   116    | DEV_BOARD0_SPI6_CLK_OUT                                                           | CLK_STATE_READY     | 0               |
    |   157     |   117    | DEV_BOARD0_I2C1_SCL_IN                                                            | CLK_STATE_NOT_READY | 0               |
    |   157     |   118    | DEV_BOARD0_DSI1_TXCLKP_IN                                                         | CLK_STATE_NOT_READY | 0               |
    |   157     |   119    | DEV_BOARD0_MCAN0_RX_OUT                                                           | CLK_STATE_READY     | 0               |
    |   157     |   120    | DEV_BOARD0_MCASP0_ACLKR_OUT                                                       | CLK_STATE_READY     | 0               |
    |   157     |   121    | DEV_BOARD0_RMII_REF_CLK_OUT                                                       | CLK_STATE_READY     | 0               |
    |   157     |   123    | DEV_BOARD0_MCAN14_RX_OUT                                                          | CLK_STATE_READY     | 0               |
    |   157     |   125    | DEV_BOARD0_MCU_I2C0_SCL_OUT                                                       | CLK_STATE_READY     | 0               |
    |   157     |   126    | DEV_BOARD0_SPI6_CLK_IN                                                            | CLK_STATE_NOT_READY | 0               |
    |   157     |   128    | DEV_BOARD0_MCASP3_AFSX_OUT                                                        | CLK_STATE_READY     | 0               |
    |   157     |   129    | DEV_BOARD0_MCU_SPI1_CLK_OUT                                                       | CLK_STATE_READY     | 0               |
    |   157     |   130    | DEV_BOARD0_SERDES0_REFCLK_P_IN                                                    | CLK_STATE_READY     | 0               |
    |   157     |   131    | DEV_BOARD0_SERDES0_REFCLK_P_OUT                                                   | CLK_STATE_READY     | 0               |
    |   157     |   132    | DEV_BOARD0_MCASP1_ACLKR_IN                                                        | CLK_STATE_READY     | 0               |
    |   157     |   134    | DEV_BOARD0_MCASP1_AFSX_OUT                                                        | CLK_STATE_READY     | 0               |
    |   157     |   135    | DEV_BOARD0_SPI1_CLK_OUT                                                           | CLK_STATE_READY     | 0               |
    |   157     |   136    | DEV_BOARD0_I2C3_SCL_IN                                                            | CLK_STATE_NOT_READY | 0               |
    |   157     |   137    | DEV_BOARD0_MCU_I2C0_SCL_IN                                                        | CLK_STATE_READY     | 0               |
    |   157     |   138    | DEV_BOARD0_HYP1_TXPMCLK_IN                                                        | CLK_STATE_NOT_READY | 0               |
    |   157     |   139    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN                                                   | CLK_STATE_NOT_READY | 0               |
    |   157     |   140    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT             | CLK_STATE_READY     | 0               |
    |   157     |   141    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT             | CLK_STATE_READY     | 0               |
    |   157     |   142    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT             | CLK_STATE_READY     | 0               |
    |   157     |   143    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKR_POUT             | CLK_STATE_READY     | 0               |
    |   157     |   144    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKR_POUT             | CLK_STATE_READY     | 0               |
    |   157     |   152    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT             | CLK_STATE_READY     | 0               |
    |   157     |   153    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT             | CLK_STATE_READY     | 0               |
    |   157     |   154    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT             | CLK_STATE_READY     | 0               |
    |   157     |   155    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKX_POUT             | CLK_STATE_READY     | 0               |
    |   157     |   156    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKX_POUT             | CLK_STATE_READY     | 0               |
    |   157     |   164    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT           | CLK_STATE_NOT_READY | 0               |
    |   157     |   165    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1         | CLK_STATE_NOT_READY | 0               |
    |   157     |   166    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2         | CLK_STATE_NOT_READY | 0               |
    |   157     |   167    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3         | CLK_STATE_NOT_READY | 0               |
    |   157     |   168    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK          | CLK_STATE_READY     | 196608000       |
    |   157     |   173    | DEV_BOARD0_MCASP2_ACLKX_OUT                                                       | CLK_STATE_READY     | 0               |
    |   157     |   175    | DEV_BOARD0_MMC1_CLKLB_OUT                                                         | CLK_STATE_READY     | 0               |
    |   157     |   176    | DEV_BOARD0_WKUP_I2C0_SCL_OUT                                                      | CLK_STATE_READY     | 0               |
    |   157     |   177    | DEV_BOARD0_SYSCLKOUT0_IN                                                          | CLK_STATE_READY     | 125000000       |
    |   157     |   178    | DEV_BOARD0_I2C1_SCL_OUT                                                           | CLK_STATE_READY     | 0               |
    |   157     |   179    | DEV_BOARD0_MCU_OSPI0_LBCLKO_IN                                                    | CLK_STATE_READY     | 0               |
    |   157     |   180    | DEV_BOARD0_SPI3_CLK_IN                                                            | CLK_STATE_NOT_READY | 0               |
    |   157     |   181    | DEV_BOARD0_MCAN13_RX_OUT                                                          | CLK_STATE_READY     | 0               |
    |   157     |   182    | DEV_BOARD0_WKUP_I2C0_SCL_IN                                                       | CLK_STATE_READY     | 0               |
    |   157     |   183    | DEV_BOARD0_DSI1_TXCLKN_IN                                                         | CLK_STATE_NOT_READY | 0               |
    |   157     |   184    | DEV_BOARD0_CPTS0_RFT_CLK_OUT                                                      | CLK_STATE_READY     | 0               |
    |   157     |   185    | DEV_BOARD0_MCU_I2C1_SCL_OUT                                                       | CLK_STATE_READY     | 0               |
    |   157     |   186    | DEV_BOARD0_MCASP0_ACLKR_IN                                                        | CLK_STATE_READY     | 0               |
    |   157     |   187    | DEV_BOARD0_MCU_OSPI1_LBCLKO_IN                                                    | CLK_STATE_READY     | 0               |
    |   157     |   188    | DEV_BOARD0_MCASP0_AFSX_OUT                                                        | CLK_STATE_READY     | 0               |
    |   157     |   190    | DEV_BOARD0_MCU_I3C0_SDA_OUT                                                       | CLK_STATE_READY     | 0               |
    |   157     |   191    | DEV_BOARD0_MCASP0_ACLKX_IN                                                        | CLK_STATE_READY     | 0               |
    |   157     |   192    | DEV_BOARD0_AUDIO_EXT_REFCLK0_OUT                                                  | CLK_STATE_READY     | 0               |
    |   157     |   193    | DEV_BOARD0_MCAN3_RX_OUT                                                           | CLK_STATE_READY     | 0               |
    |   157     |   194    | DEV_BOARD0_MMC1_CLKLB_IN                                                          | CLK_STATE_READY     | 0               |
    |   157     |   195    | DEV_BOARD0_MCASP2_ACLKR_OUT                                                       | CLK_STATE_READY     | 0               |
    |   157     |   198    | DEV_BOARD0_HFOSC1_CLK_OUT                                                         | CLK_STATE_READY     | 0               |
    |   157     |   199    | DEV_BOARD0_MCASP1_ACLKR_OUT                                                       | CLK_STATE_READY     | 0               |
    |   157     |   200    | DEV_BOARD0_MCAN4_RX_OUT                                                           | CLK_STATE_READY     | 0               |
    |   157     |   201    | DEV_BOARD0_MCASP4_ACLKX_OUT                                                       | CLK_STATE_READY     | 0               |
    |   157     |   202    | DEV_BOARD0_CSI1_TXCLKP_IN                                                         | CLK_STATE_NOT_READY | 0               |
    |   157     |   203    | DEV_BOARD0_MCASP3_AFSR_OUT                                                        | CLK_STATE_READY     | 0               |
    |   157     |   204    | DEV_BOARD0_LED_CLK_OUT                                                            | CLK_STATE_READY     | 0               |
    |   157     |   206    | DEV_BOARD0_MCAN7_RX_OUT                                                           | CLK_STATE_READY     | 0               |
    |   157     |   207    | DEV_BOARD0_MCU_MDIO0_MDC_IN                                                       | CLK_STATE_READY     | 0               |
    |   157     |   209    | DEV_BOARD0_MCASP4_ACLKR_IN                                                        | CLK_STATE_READY     | 0               |
    |   157     |   210    | DEV_BOARD0_I2C2_SCL_IN                                                            | CLK_STATE_NOT_READY | 0               |
    |   157     |   212    | DEV_BOARD0_SPI1_CLK_IN                                                            | CLK_STATE_NOT_READY | 0               |
    |   157     |   213    | DEV_BOARD0_HYP1_RXPMCLK_OUT                                                       | CLK_STATE_READY     | 0               |
    |   157     |   214    | DEV_BOARD0_MCU_HYPERBUS0_CK_IN                                                    | CLK_STATE_READY     | 0               |
    |   157     |   215    | DEV_BOARD0_MCASP2_AFSX_OUT                                                        | CLK_STATE_READY     | 0               |
    |   157     |   216    | DEV_BOARD0_MCASP3_ACLKR_OUT                                                       | CLK_STATE_READY     | 0               |
    |   157     |   217    | DEV_BOARD0_MCAN15_RX_OUT                                                          | CLK_STATE_READY     | 0               |
    |   157     |   218    | DEV_BOARD0_SPI0_CLK_IN                                                            | CLK_STATE_NOT_READY | 0               |
    |   157     |   219    | DEV_BOARD0_MCAN12_RX_OUT                                                          | CLK_STATE_READY     | 0               |
    |   157     |   220    | DEV_BOARD0_MCASP2_ACLKR_IN                                                        | CLK_STATE_READY     | 0               |
    |   157     |   221    | DEV_BOARD0_MCU_CLKOUT0_IN                                                         | CLK_STATE_READY     | 50000000        |
    |   157     |   222    | DEV_BOARD0_MCU_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT0_CLK5                | CLK_STATE_READY     | 50000000        |
    |   157     |   223    | DEV_BOARD0_MCU_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT0_CLK10               | CLK_STATE_READY     | 25000000        |
    |   157     |   224    | DEV_BOARD0_MCU_OSPI1_DQS_OUT                                                      | CLK_STATE_READY     | 0               |
    |   157     |   226    | DEV_BOARD0_CSI0_RXCLKN_OUT                                                        | CLK_STATE_READY     | 0               |
    |   157     |   227    | DEV_BOARD0_TCK_OUT                                                                | CLK_STATE_READY     | 0               |
    |   157     |   228    | DEV_BOARD0_CSI1_TXCLKN_IN                                                         | CLK_STATE_NOT_READY | 0               |
    |   157     |   229    | DEV_BOARD0_MCU_MCAN0_RX_OUT                                                       | CLK_STATE_READY     | 0               |
    |   157     |   230    | DEV_BOARD0_MCASP4_AFSR_OUT                                                        | CLK_STATE_READY     | 0               |
    |   157     |   231    | DEV_BOARD0_MCU_HYPERBUS0_CKN_IN                                                   | CLK_STATE_READY     | 0               |
    |   157     |   232    | DEV_BOARD0_MCASP4_ACLKR_OUT                                                       | CLK_STATE_READY     | 0               |
    |   157     |   233    | DEV_BOARD0_MCAN11_RX_OUT                                                          | CLK_STATE_READY     | 0               |
    |   157     |   234    | DEV_BOARD0_I2C5_SCL_IN                                                            | CLK_STATE_NOT_READY | 0               |
    |   157     |   235    | DEV_BOARD0_MCU_I2C1_SCL_IN                                                        | CLK_STATE_READY     | 0               |
    |   157     |   236    | DEV_BOARD0_I2C0_SCL_OUT                                                           | CLK_STATE_READY     | 0               |
    |   157     |   237    | DEV_BOARD0_MCAN6_RX_OUT                                                           | CLK_STATE_READY     | 0               |
    |   157     |   238    | DEV_BOARD0_MCU_I3C0_SCL_IN                                                        | CLK_STATE_NOT_READY | 0               |
    |   157     |   239    | DEV_BOARD0_MMC1_CLK_OUT                                                           | CLK_STATE_READY     | 0               |
    |   157     |   240    | DEV_BOARD0_VOUT0_EXTPCLKIN_OUT                                                    | CLK_STATE_READY     | 0               |
    |   157     |   241    | DEV_BOARD0_EXT_REFCLK1_OUT                                                        | CLK_STATE_READY     | 0               |
    |   157     |   242    | DEV_BOARD0_I2C5_SCL_OUT                                                           | CLK_STATE_READY     | 0               |
    |   157     |   243    | DEV_BOARD0_MCAN16_RX_OUT                                                          | CLK_STATE_READY     | 0               |
    |   157     |   244    | DEV_BOARD0_MCU_RGMII1_TXC_IN                                                      | CLK_STATE_READY     | 0               |
    |   157     |   245    | DEV_BOARD0_MCASP4_ACLKX_IN                                                        | CLK_STATE_READY     | 0               |
    |   157     |   246    | DEV_BOARD0_GPMC0_CLKOUT_IN                                                        | CLK_STATE_NOT_READY | 0               |
    |   157     |   247    | DEV_BOARD0_GPMC0_CLK_OUT                                                          | CLK_STATE_READY     | 0               |
    |   157     |   248    | DEV_BOARD0_I2C6_SCL_IN                                                            | CLK_STATE_NOT_READY | 0               |
    |   157     |   249    | DEV_BOARD0_I2C4_SCL_IN                                                            | CLK_STATE_NOT_READY | 0               |
    |   157     |   250    | DEV_BOARD0_SERDES0_REFCLK_N_IN                                                    | CLK_STATE_READY     | 0               |
    |   157     |   251    | DEV_BOARD0_OBSCLK0_IN                                                             | CLK_STATE_READY     | 500000000       |
    |   157     |   252    | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK                    | CLK_STATE_READY     | 500000000       |
    |   157     |   253    | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT0_CLK                    | CLK_STATE_READY     | 192000000       |
    |   157     |   254    | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK                    | CLK_STATE_READY     | 600000000       |
    |   157     |   255    | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT0_CLK                    | CLK_STATE_READY     | 250000000       |
    |   157     |   256    | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT0_CLK                    | CLK_STATE_READY     | 196608000       |
    |   157     |   257    | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_5_HSDIVOUT0_CLK                    | CLK_STATE_READY     | 400000000       |
    |   157     |   258    | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MAIN_6_HSDIVOUT0_CLK                    | CLK_STATE_READY     | 800000000       |
    |   157     |   259    | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MAIN_26_HSDIVOUT0_CLK                   | CLK_STATE_READY     | 1066500000      |
    |   157     |   264    | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MAIN_12_HSDIVOUT0_CLK                   | CLK_STATE_READY     | 1066500000      |
    |   157     |   265    | DEV_BOARD0_OBSCLK0_IN_PARENT_OBSCLK1_MUX_OUT0                                     | CLK_STATE_READY     | 0               |
    |   157     |   266    | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV2_16FFT_MAIN_14_HSDIVOUT0_CLK                   | CLK_STATE_READY     | 1000000000      |
    |   157     |   268    | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK                   | CLK_STATE_READY     | 594000000       |
    |   157     |   269    | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT0_CLK                   | CLK_STATE_READY     | 51200000        |
    |   157     |   271    | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_19_HSDIVOUT0_CLK                   | CLK_STATE_READY     | 600000000       |
    |   157     |   277    | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_25_HSDIVOUT0_CLK                   | CLK_STATE_READY     | 480000000       |
    |   157     |   278    | DEV_BOARD0_OBSCLK0_IN_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF3                      | CLK_STATE_READY     | 0               |
    |   157     |   279    | DEV_BOARD0_OBSCLK0_IN_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK         | CLK_STATE_READY     | 12500000        |
    |   157     |   280    | DEV_BOARD0_OBSCLK0_IN_PARENT_GLUELOGIC_LPXOSC_CLKOUT                              | CLK_STATE_READY     | 32768           |
    |   157     |   281    | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK_DUP0               | CLK_STATE_READY     | 500000000       |
    |   157     |   282    | DEV_BOARD0_OBSCLK0_IN_PARENT_BOARD_0_HFOSC1_CLK_OUT                               | CLK_STATE_READY     | 0               |
    |   157     |   283    | DEV_BOARD0_OBSCLK0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT                              | CLK_STATE_READY     | 19200000        |
    |   157     |   284    | DEV_BOARD0_MCAN2_RX_OUT                                                           | CLK_STATE_READY     | 0               |
    |   157     |   285    | DEV_BOARD0_MCASP2_ACLKX_IN                                                        | CLK_STATE_READY     | 0               |
    |   157     |   287    | DEV_BOARD0_MCU_EXT_REFCLK0_OUT                                                    | CLK_STATE_READY     | 0               |
    |   157     |   288    | DEV_BOARD0_MCASP1_ACLKX_OUT                                                       | CLK_STATE_READY     | 0               |
    |   157     |   289    | DEV_BOARD0_SPI2_CLK_OUT                                                           | CLK_STATE_READY     | 0               |
    |   157     |   290    | DEV_BOARD0_HYP0_RXFLCLK_IN                                                        | CLK_STATE_NOT_READY | 0               |
    |   157     |   291    | DEV_BOARD0_SPI3_CLK_OUT                                                           | CLK_STATE_READY     | 0               |
    |   157     |   292    | DEV_BOARD0_MCASP1_AFSR_OUT                                                        | CLK_STATE_READY     | 0               |
    |   157     |   293    | DEV_BOARD0_I2C2_SCL_OUT                                                           | CLK_STATE_READY     | 0               |
    |   157     |   294    | DEV_BOARD0_MCAN10_RX_OUT                                                          | CLK_STATE_READY     | 0               |
    |   157     |   295    | DEV_BOARD0_MCAN5_RX_OUT                                                           | CLK_STATE_READY     | 0               |
    |   157     |   296    | DEV_BOARD0_MCU_I3C0_SCL_OUT                                                       | CLK_STATE_READY     | 0               |
    |   157     |   297    | DEV_BOARD0_MCU_MCAN1_RX_OUT                                                       | CLK_STATE_READY     | 0               |
    |   157     |   299    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN                                                   | CLK_STATE_NOT_READY | 0               |
    |   157     |   300    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT             | CLK_STATE_READY     | 0               |
    |   157     |   301    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT             | CLK_STATE_READY     | 0               |
    |   157     |   302    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT             | CLK_STATE_READY     | 0               |
    |   157     |   303    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKR_POUT             | CLK_STATE_READY     | 0               |
    |   157     |   304    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKR_POUT             | CLK_STATE_READY     | 0               |
    |   157     |   312    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT             | CLK_STATE_READY     | 0               |
    |   157     |   313    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT             | CLK_STATE_READY     | 0               |
    |   157     |   314    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT             | CLK_STATE_READY     | 0               |
    |   157     |   315    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKX_POUT             | CLK_STATE_READY     | 0               |
    |   157     |   316    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKX_POUT             | CLK_STATE_READY     | 0               |
    |   157     |   324    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT           | CLK_STATE_NOT_READY | 0               |
    |   157     |   325    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1         | CLK_STATE_NOT_READY | 0               |
    |   157     |   326    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2         | CLK_STATE_NOT_READY | 0               |
    |   157     |   327    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3         | CLK_STATE_NOT_READY | 0               |
    |   157     |   328    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK          | CLK_STATE_READY     | 196608000       |
    |   157     |   333    | DEV_BOARD0_HYP1_TXFLCLK_OUT                                                       | CLK_STATE_READY     | 0               |
    |   157     |   334    | DEV_BOARD0_SPI5_CLK_IN                                                            | CLK_STATE_NOT_READY | 0               |
    |   157     |   335    | DEV_BOARD0_I2C3_SCL_OUT                                                           | CLK_STATE_READY     | 0               |
    |   157     |   336    | DEV_BOARD0_MCAN8_RX_OUT                                                           | CLK_STATE_READY     | 0               |
    |   157     |   338    | DEV_BOARD0_RGMII1_RXC_OUT                                                         | CLK_STATE_READY     | 0               |
    |   157     |   339    | DEV_BOARD0_SERDES0_REFCLK_N_OUT                                                   | CLK_STATE_READY     | 0               |
    |   157     |   340    | DEV_BOARD0_CSI0_TXCLKP_IN                                                         | CLK_STATE_READY     | 0               |
    |   157     |   341    | DEV_BOARD0_SPI7_CLK_IN                                                            | CLK_STATE_NOT_READY | 0               |
    |   157     |   342    | DEV_BOARD0_RGMII1_TXC_IN                                                          | CLK_STATE_NOT_READY | 0               |
    |   157     |   343    | DEV_BOARD0_HYP1_RXFLCLK_IN                                                        | CLK_STATE_NOT_READY | 0               |
    |   157     |   344    | DEV_BOARD0_MDIO1_MDC_IN                                                           | CLK_STATE_NOT_READY | 0               |
    |   157     |   345    | DEV_BOARD0_SPI2_CLK_IN                                                            | CLK_STATE_NOT_READY | 0               |
    |   157     |   346    | DEV_BOARD0_DSI0_TXCLKP_IN                                                         | CLK_STATE_READY     | 0               |
    |   157     |   347    | DEV_BOARD0_MCASP4_AFSX_OUT                                                        | CLK_STATE_READY     | 0               |
    |   157     |   352    | DEV_BOARD0_VOUT0_PCLK_IN                                                          | CLK_STATE_READY     | 600000000       |
    |   150     |     0    | DEV_CMPEVENT_INTRTR0_INTR_CLK                                                     | CLK_STATE_READY     | 125000000       |
    |   179     |     0    | DEV_CODEC0_VPU_PCLK_CLK                                                           | CLK_STATE_READY     | 600000000       |
    |   179     |     1    | DEV_CODEC0_VPU_BCLK_CLK                                                           | CLK_STATE_READY     | 400000000       |
    |   179     |     2    | DEV_CODEC0_VPU_CCLK_CLK                                                           | CLK_STATE_READY     | 600000000       |
    |   179     |     3    | DEV_CODEC0_VPU_ACLK_CLK                                                           | CLK_STATE_READY     | 600000000       |
    |     8     |     0    | DEV_COMPUTE_CLUSTER0_C71SS0_0_C7X_CLK                                             | CLK_STATE_READY     | 1000000000      |
    |     8     |     1    | DEV_COMPUTE_CLUSTER0_C71SS0_0_PLL_CTRL_CLK                                        | CLK_STATE_READY     | 500000000       |
    |     8     |     3    | DEV_COMPUTE_CLUSTER0_C71SS0_0_C7X_DIVH_CLK4_OBSCLK_OUT_CLK                        | CLK_STATE_READY     | 0               |
    |    11     |     0    | DEV_COMPUTE_CLUSTER0_C71SS1_0_C7X_CLK                                             | CLK_STATE_READY     | 1000000000      |
    |    11     |     1    | DEV_COMPUTE_CLUSTER0_C71SS1_0_PLL_CTRL_CLK                                        | CLK_STATE_READY     | 500000000       |
    |    14     |     1    | DEV_COMPUTE_CLUSTER0_CLEC_CLK1_CLK                                                | CLK_STATE_READY     | 500000000       |
    |    15     |     1    | DEV_COMPUTE_CLUSTER0_CORE_CORE_CLK1_CLK                                           | CLK_STATE_READY     | 500000000       |
    |    15     |     2    | DEV_COMPUTE_CLUSTER0_CORE_CORE_PSIL_LEAF_CLK                                      | CLK_STATE_READY     | 500000000       |
    |    18     |     0    | DEV_COMPUTE_CLUSTER0_DEBUG_WRAP_0_CLK1_CLK_CLK                                    | CLK_STATE_READY     | 1000000000      |
    |    18     |     1    | DEV_COMPUTE_CLUSTER0_DEBUG_WRAP_0_CLK2_CLK_CLK                                    | CLK_STATE_READY     | 500000000       |
    |    25     |     0    | DEV_COMPUTE_CLUSTER0_EN_MSMC_DOMAIN_0_MSMC_CLK1_CLK                               | CLK_STATE_READY     | 500000000       |
    |    26     |     0    | DEV_COMPUTE_CLUSTER0_GIC500SS_VCLK_CLK                                            | CLK_STATE_READY     | 500000000       |
    |    27     |     3    | DEV_COMPUTE_CLUSTER0_PBIST_WRAP_0_DIVP_CLK1_CLK_CLK                               | CLK_STATE_READY     | 1000000000      |
    |    27     |     4    | DEV_COMPUTE_CLUSTER0_PBIST_WRAP_0_DIVH_CLK2_CLK_CLK                               | CLK_STATE_READY     | 500000000       |
    |    28     |     0    | DEV_CPSW1_MDIO_MDCLK_O                                                            | CLK_STATE_READY     | 0               |
    |    28     |     1    | DEV_CPSW1_CPTS_GENF0                                                              | CLK_STATE_READY     | 0               |
    |    28     |     3    | DEV_CPSW1_CPTS_RFT_CLK                                                            | CLK_STATE_READY     | 250000000       |
    |    28     |     4    | DEV_CPSW1_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK                   | CLK_STATE_READY     | 250000000       |
    |    28     |     5    | DEV_CPSW1_CPTS_RFT_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK                 | CLK_STATE_READY     | 200000000       |
    |    28     |     6    | DEV_CPSW1_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT                       | CLK_STATE_READY     | 0               |
    |    28     |     7    | DEV_CPSW1_CPTS_RFT_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT                           | CLK_STATE_READY     | 0               |
    |    28     |     8    | DEV_CPSW1_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                         | CLK_STATE_READY     | 0               |
    |    28     |     9    | DEV_CPSW1_CPTS_RFT_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT                             | CLK_STATE_READY     | 0               |
    |    28     |    10    | DEV_CPSW1_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN0_TXMCLK                  | CLK_STATE_READY     | 0               |
    |    28     |    11    | DEV_CPSW1_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN1_TXMCLK                  | CLK_STATE_READY     | 0               |
    |    28     |    12    | DEV_CPSW1_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN2_TXMCLK                  | CLK_STATE_READY     | 0               |
    |    28     |    13    | DEV_CPSW1_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN3_TXMCLK                  | CLK_STATE_READY     | 0               |
    |    28     |    18    | DEV_CPSW1_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK                    | CLK_STATE_READY     | 500000000       |
    |    28     |    19    | DEV_CPSW1_CPTS_RFT_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK           | CLK_STATE_READY     | 500000000       |
    |    28     |    20    | DEV_CPSW1_GMII1_MR_CLK                                                            | CLK_STATE_READY     | 25000000        |
    |    28     |    21    | DEV_CPSW1_GMII_RFT_CLK                                                            | CLK_STATE_READY     | 125000000       |
    |    28     |    22    | DEV_CPSW1_RGMII1_RXC_I                                                            | CLK_STATE_READY     | 0               |
    |    28     |    26    | DEV_CPSW1_RMII_MHZ_50_CLK                                                         | CLK_STATE_READY     | 0               |
    |    28     |    27    | DEV_CPSW1_RGMII1_TXC_O                                                            | CLK_STATE_READY     | 0               |
    |    28     |    28    | DEV_CPSW1_CPPI_CLK_CLK                                                            | CLK_STATE_READY     | 320000000       |
    |    28     |    29    | DEV_CPSW1_RGMII_MHZ_5_CLK                                                         | CLK_STATE_READY     | 5000000         |
    |    28     |    30    | DEV_CPSW1_GMII1_MT_CLK                                                            | CLK_STATE_READY     | 25000000        |
    |    28     |    32    | DEV_CPSW1_RGMII_MHZ_50_CLK                                                        | CLK_STATE_READY     | 50000000        |
    |    28     |    33    | DEV_CPSW1_RGMII_MHZ_250_CLK                                                       | CLK_STATE_READY     | 250000000       |
    |    36     |     0    | DEV_CPT2_AGGR0_VCLK_CLK                                                           | CLK_STATE_READY     | 250000000       |
    |    30     |     0    | DEV_CPT2_AGGR1_VCLK_CLK                                                           | CLK_STATE_READY     | 250000000       |
    |    32     |     0    | DEV_CPT2_AGGR2_VCLK_CLK                                                           | CLK_STATE_READY     | 250000000       |
    |    34     |     0    | DEV_CPT2_AGGR3_VCLK_CLK                                                           | CLK_STATE_READY     | 250000000       |
    |    33     |     0    | DEV_CPT2_AGGR4_VCLK_CLK                                                           | CLK_STATE_READY     | 250000000       |
    |    31     |     0    | DEV_CPT2_AGGR5_VCLK_CLK                                                           | CLK_STATE_READY     | 250000000       |
    |   136     |     0    | DEV_CSI_PSILSS0_MAIN_CLK                                                          | CLK_STATE_READY     | 125000000       |
    |    38     |     0    | DEV_CSI_RX_IF0_PPI_D_RX_ULPS_ESC                                                  | CLK_STATE_NOT_READY | 0               |
    |    38     |     1    | DEV_CSI_RX_IF0_VBUS_CLK_CLK                                                       | CLK_STATE_READY     | 250000000       |
    |    38     |     2    | DEV_CSI_RX_IF0_PPI_RX_BYTE_CLK                                                    | CLK_STATE_NOT_READY | 0               |
    |    38     |     3    | DEV_CSI_RX_IF0_MAIN_CLK_CLK                                                       | CLK_STATE_READY     | 500000000       |
    |    38     |     4    | DEV_CSI_RX_IF0_VP_CLK_CLK                                                         | CLK_STATE_READY     | 720000000       |
    |    39     |     0    | DEV_CSI_RX_IF1_PPI_D_RX_ULPS_ESC                                                  | CLK_STATE_NOT_READY | 0               |
    |    39     |     1    | DEV_CSI_RX_IF1_VBUS_CLK_CLK                                                       | CLK_STATE_READY     | 250000000       |
    |    39     |     2    | DEV_CSI_RX_IF1_PPI_RX_BYTE_CLK                                                    | CLK_STATE_NOT_READY | 0               |
    |    39     |     3    | DEV_CSI_RX_IF1_MAIN_CLK_CLK                                                       | CLK_STATE_READY     | 500000000       |
    |    39     |     4    | DEV_CSI_RX_IF1_VP_CLK_CLK                                                         | CLK_STATE_READY     | 720000000       |
    |    40     |     1    | DEV_CSI_TX_IF_V2_0_VBUS_CLK_CLK                                                   | CLK_STATE_READY     | 250000000       |
    |    40     |     2    | DEV_CSI_TX_IF_V2_0_MAIN_CLK_CLK                                                   | CLK_STATE_READY     | 500000000       |
    |    40     |     3    | DEV_CSI_TX_IF_V2_0_DPHY_TXBYTECLKHS_CL_CLK                                        | CLK_STATE_READY     | 0               |
    |    40     |     5    | DEV_CSI_TX_IF_V2_0_ESC_CLK_CLK                                                    | CLK_STATE_READY     | 20000000        |
    |    41     |     1    | DEV_CSI_TX_IF_V2_1_VBUS_CLK_CLK                                                   | CLK_STATE_READY     | 250000000       |
    |    41     |     2    | DEV_CSI_TX_IF_V2_1_MAIN_CLK_CLK                                                   | CLK_STATE_READY     | 500000000       |
    |    41     |     3    | DEV_CSI_TX_IF_V2_1_DPHY_TXBYTECLKHS_CL_CLK                                        | CLK_STATE_NOT_READY | 0               |
    |    41     |     5    | DEV_CSI_TX_IF_V2_1_ESC_CLK_CLK                                                    | CLK_STATE_READY     | 20000000        |
    |    43     |     0    | DEV_DCC0_DCC_CLKSRC0_CLK                                                          | CLK_STATE_READY     | 250000000       |
    |    43     |     1    | DEV_DCC0_DCC_CLKSRC1_CLK                                                          | CLK_STATE_READY     | 200000000       |
    |    43     |     2    | DEV_DCC0_DCC_CLKSRC2_CLK                                                          | CLK_STATE_READY     | 133333333       |
    |    43     |     3    | DEV_DCC0_DCC_CLKSRC3_CLK                                                          | CLK_STATE_READY     | 80000000        |
    |    43     |     4    | DEV_DCC0_DCC_CLKSRC4_CLK                                                          | CLK_STATE_READY     | 19200000        |
    |    43     |     5    | DEV_DCC0_DCC_CLKSRC5_CLK                                                          | CLK_STATE_READY     | 0               |
    |    43     |     6    | DEV_DCC0_DCC_CLKSRC6_CLK                                                          | CLK_STATE_READY     | 500000000       |
    |    43     |     7    | DEV_DCC0_DCC_CLKSRC7_CLK                                                          | CLK_STATE_NOT_READY | 0               |
    |    43     |     8    | DEV_DCC0_DCC_INPUT00_CLK                                                          | CLK_STATE_READY     | 19200000        |
    |    43     |     9    | DEV_DCC0_DCC_INPUT01_CLK                                                          | CLK_STATE_READY     | 0               |
    |    43     |    10    | DEV_DCC0_DCC_INPUT02_CLK                                                          | CLK_STATE_READY     | 12500000        |
    |    43     |    11    | DEV_DCC0_DCC_INPUT10_CLK                                                          | CLK_STATE_READY     | 250000000       |
    |    43     |    12    | DEV_DCC0_VBUS_CLK                                                                 | CLK_STATE_READY     | 125000000       |
    |    44     |     0    | DEV_DCC1_DCC_CLKSRC0_CLK                                                          | CLK_STATE_READY     | 50000000        |
    |    44     |     1    | DEV_DCC1_DCC_CLKSRC1_CLK                                                          | CLK_STATE_READY     | 200000000       |
    |    44     |     2    | DEV_DCC1_DCC_CLKSRC2_CLK                                                          | CLK_STATE_READY     | 200000000       |
    |    44     |     3    | DEV_DCC1_DCC_CLKSRC3_CLK                                                          | CLK_STATE_READY     | 192000000       |
    |    44     |     4    | DEV_DCC1_DCC_CLKSRC4_CLK                                                          | CLK_STATE_READY     | 320000000       |
    |    44     |     5    | DEV_DCC1_DCC_CLKSRC5_CLK                                                          | CLK_STATE_READY     | 192000000       |
    |    44     |     6    | DEV_DCC1_DCC_CLKSRC6_CLK                                                          | CLK_STATE_READY     | 192000000       |
    |    44     |     7    | DEV_DCC1_DCC_CLKSRC7_CLK                                                          | CLK_STATE_READY     | 19200000        |
    |    44     |     8    | DEV_DCC1_DCC_INPUT00_CLK                                                          | CLK_STATE_READY     | 19200000        |
    |    44     |     9    | DEV_DCC1_DCC_INPUT01_CLK                                                          | CLK_STATE_READY     | 0               |
    |    44     |    10    | DEV_DCC1_DCC_INPUT02_CLK                                                          | CLK_STATE_READY     | 12500000        |
    |    44     |    11    | DEV_DCC1_DCC_INPUT10_CLK                                                          | CLK_STATE_READY     | 125000000       |
    |    44     |    12    | DEV_DCC1_VBUS_CLK                                                                 | CLK_STATE_READY     | 125000000       |
    |    45     |     0    | DEV_DCC2_DCC_CLKSRC0_CLK                                                          | CLK_STATE_READY     | 24000000        |
    |    45     |     1    | DEV_DCC2_DCC_CLKSRC1_CLK                                                          | CLK_STATE_READY     | 20000000        |
    |    45     |     3    | DEV_DCC2_DCC_CLKSRC3_CLK                                                          | CLK_STATE_READY     | 100000000       |
    |    45     |     4    | DEV_DCC2_DCC_CLKSRC4_CLK                                                          | CLK_STATE_READY     | 225000000       |
    |    45     |     5    | DEV_DCC2_DCC_CLKSRC5_CLK                                                          | CLK_STATE_READY     | 300000000       |
    |    45     |     6    | DEV_DCC2_DCC_CLKSRC6_CLK                                                          | CLK_STATE_READY     | 200000000       |
    |    45     |     7    | DEV_DCC2_DCC_CLKSRC7_CLK                                                          | CLK_STATE_READY     | 250000000       |
    |    45     |     8    | DEV_DCC2_DCC_INPUT00_CLK                                                          | CLK_STATE_READY     | 19200000        |
    |    45     |     9    | DEV_DCC2_DCC_INPUT01_CLK                                                          | CLK_STATE_READY     | 0               |
    |    45     |    10    | DEV_DCC2_DCC_INPUT02_CLK                                                          | CLK_STATE_READY     | 12500000        |
    |    45     |    11    | DEV_DCC2_DCC_INPUT10_CLK                                                          | CLK_STATE_READY     | 125000000       |
    |    45     |    12    | DEV_DCC2_VBUS_CLK                                                                 | CLK_STATE_READY     | 125000000       |
    |    46     |     0    | DEV_DCC3_DCC_CLKSRC0_CLK                                                          | CLK_STATE_READY     | 196608000       |
    |    46     |     1    | DEV_DCC3_DCC_CLKSRC1_CLK                                                          | CLK_STATE_READY     | 200000000       |
    |    46     |     2    | DEV_DCC3_DCC_CLKSRC2_CLK                                                          | CLK_STATE_READY     | 300000000       |
    |    46     |     5    | DEV_DCC3_DCC_CLKSRC5_CLK                                                          | CLK_STATE_READY     | 200000000       |
    |    46     |     6    | DEV_DCC3_DCC_CLKSRC6_CLK                                                          | CLK_STATE_READY     | 250000000       |
    |    46     |     7    | DEV_DCC3_DCC_CLKSRC7_CLK                                                          | CLK_STATE_READY     | 500000000       |
    |    46     |     8    | DEV_DCC3_DCC_INPUT00_CLK                                                          | CLK_STATE_READY     | 19200000        |
    |    46     |     9    | DEV_DCC3_DCC_INPUT01_CLK                                                          | CLK_STATE_READY     | 0               |
    |    46     |    10    | DEV_DCC3_DCC_INPUT02_CLK                                                          | CLK_STATE_READY     | 12500000        |
    |    46     |    11    | DEV_DCC3_DCC_INPUT10_CLK                                                          | CLK_STATE_READY     | 125000000       |
    |    46     |    12    | DEV_DCC3_VBUS_CLK                                                                 | CLK_STATE_READY     | 125000000       |
    |    47     |     0    | DEV_DCC4_DCC_CLKSRC0_CLK                                                          | CLK_STATE_READY     | 200000000       |
    |    47     |     2    | DEV_DCC4_DCC_CLKSRC2_CLK                                                          | CLK_STATE_READY     | 266625000       |
    |    47     |     3    | DEV_DCC4_DCC_CLKSRC3_CLK                                                          | CLK_STATE_READY     | 266625000       |
    |    47     |     4    | DEV_DCC4_DCC_CLKSRC4_CLK                                                          | CLK_STATE_READY     | 250000000       |
    |    47     |     5    | DEV_DCC4_DCC_CLKSRC5_CLK                                                          | CLK_STATE_READY     | 250000000       |
    |    47     |     7    | DEV_DCC4_DCC_CLKSRC7_CLK                                                          | CLK_STATE_READY     | 297000000       |
    |    47     |     8    | DEV_DCC4_DCC_INPUT00_CLK                                                          | CLK_STATE_READY     | 19200000        |
    |    47     |     9    | DEV_DCC4_DCC_INPUT01_CLK                                                          | CLK_STATE_READY     | 0               |
    |    47     |    10    | DEV_DCC4_DCC_INPUT02_CLK                                                          | CLK_STATE_READY     | 12500000        |
    |    47     |    11    | DEV_DCC4_DCC_INPUT10_CLK                                                          | CLK_STATE_READY     | 250000000       |
    |    47     |    12    | DEV_DCC4_VBUS_CLK                                                                 | CLK_STATE_READY     | 125000000       |
    |    48     |     1    | DEV_DCC5_DCC_CLKSRC1_CLK                                                          | CLK_STATE_READY     | 300000000       |
    |    48     |     2    | DEV_DCC5_DCC_CLKSRC2_CLK                                                          | CLK_STATE_READY     | 25600000        |
    |    48     |     3    | DEV_DCC5_DCC_CLKSRC3_CLK                                                          | CLK_STATE_READY     | 240000000       |
    |    48     |     4    | DEV_DCC5_DCC_CLKSRC4_CLK                                                          | CLK_STATE_READY     | 360000000       |
    |    48     |     6    | DEV_DCC5_DCC_CLKSRC6_CLK                                                          | CLK_STATE_READY     | 0               |
    |    48     |     7    | DEV_DCC5_DCC_CLKSRC7_CLK                                                          | CLK_STATE_READY     | 0               |
    |    48     |     8    | DEV_DCC5_DCC_INPUT00_CLK                                                          | CLK_STATE_READY     | 19200000        |
    |    48     |     9    | DEV_DCC5_DCC_INPUT01_CLK                                                          | CLK_STATE_READY     | 0               |
    |    48     |    10    | DEV_DCC5_DCC_INPUT02_CLK                                                          | CLK_STATE_READY     | 12500000        |
    |    48     |    11    | DEV_DCC5_DCC_INPUT10_CLK                                                          | CLK_STATE_READY     | 500000000       |
    |    48     |    12    | DEV_DCC5_VBUS_CLK                                                                 | CLK_STATE_READY     | 125000000       |
    |    49     |     0    | DEV_DCC6_DCC_CLKSRC0_CLK                                                          | CLK_STATE_READY     | 0               |
    |    49     |     1    | DEV_DCC6_DCC_CLKSRC1_CLK                                                          | CLK_STATE_READY     | 0               |
    |    49     |     2    | DEV_DCC6_DCC_CLKSRC2_CLK                                                          | CLK_STATE_READY     | 0               |
    |    49     |     3    | DEV_DCC6_DCC_CLKSRC3_CLK                                                          | CLK_STATE_READY     | 0               |
    |    49     |     4    | DEV_DCC6_DCC_CLKSRC4_CLK                                                          | CLK_STATE_READY     | 0               |
    |    49     |     5    | DEV_DCC6_DCC_CLKSRC5_CLK                                                          | CLK_STATE_READY     | 0               |
    |    49     |     6    | DEV_DCC6_DCC_CLKSRC6_CLK                                                          | CLK_STATE_READY     | 0               |
    |    49     |     7    | DEV_DCC6_DCC_CLKSRC7_CLK                                                          | CLK_STATE_READY     | 0               |
    |    49     |     8    | DEV_DCC6_DCC_INPUT00_CLK                                                          | CLK_STATE_READY     | 19200000        |
    |    49     |     9    | DEV_DCC6_DCC_INPUT01_CLK                                                          | CLK_STATE_READY     | 0               |
    |    49     |    10    | DEV_DCC6_DCC_INPUT02_CLK                                                          | CLK_STATE_READY     | 12500000        |
    |    49     |    11    | DEV_DCC6_DCC_INPUT10_CLK                                                          | CLK_STATE_READY     | 125000000       |
    |    49     |    12    | DEV_DCC6_VBUS_CLK                                                                 | CLK_STATE_READY     | 125000000       |
    |    50     |     0    | DEV_DCC7_DCC_CLKSRC0_CLK                                                          | CLK_STATE_READY     | 0               |
    |    50     |     1    | DEV_DCC7_DCC_CLKSRC1_CLK                                                          | CLK_STATE_READY     | 0               |
    |    50     |     2    | DEV_DCC7_DCC_CLKSRC2_CLK                                                          | CLK_STATE_READY     | 500000000       |
    |    50     |     5    | DEV_DCC7_DCC_CLKSRC5_CLK                                                          | CLK_STATE_READY     | 0               |
    |    50     |     6    | DEV_DCC7_DCC_CLKSRC6_CLK                                                          | CLK_STATE_READY     | 120000000       |
    |    50     |     7    | DEV_DCC7_DCC_CLKSRC7_CLK                                                          | CLK_STATE_READY     | 0               |
    |    50     |     8    | DEV_DCC7_DCC_INPUT00_CLK                                                          | CLK_STATE_READY     | 19200000        |
    |    50     |     9    | DEV_DCC7_DCC_INPUT01_CLK                                                          | CLK_STATE_READY     | 0               |
    |    50     |    10    | DEV_DCC7_DCC_INPUT02_CLK                                                          | CLK_STATE_READY     | 12500000        |
    |    50     |    11    | DEV_DCC7_DCC_INPUT10_CLK                                                          | CLK_STATE_READY     | 250000000       |
    |    50     |    12    | DEV_DCC7_VBUS_CLK                                                                 | CLK_STATE_READY     | 125000000       |
    |    51     |     0    | DEV_DCC8_DCC_CLKSRC0_CLK                                                          | CLK_STATE_READY     | 32000           |
    |    51     |     1    | DEV_DCC8_DCC_CLKSRC1_CLK                                                          | CLK_STATE_READY     | 32768           |
    |    51     |     2    | DEV_DCC8_DCC_CLKSRC2_CLK                                                          | CLK_STATE_READY     | 0               |
    |    51     |     3    | DEV_DCC8_DCC_CLKSRC3_CLK                                                          | CLK_STATE_NOT_READY | 0               |
    |    51     |     4    | DEV_DCC8_DCC_CLKSRC4_CLK                                                          | CLK_STATE_NOT_READY | 0               |
    |    51     |     6    | DEV_DCC8_DCC_CLKSRC6_CLK                                                          | CLK_STATE_READY     | 250000000       |
    |    51     |     7    | DEV_DCC8_DCC_CLKSRC7_CLK                                                          | CLK_STATE_READY     | 200000000       |
    |    51     |     8    | DEV_DCC8_DCC_INPUT00_CLK                                                          | CLK_STATE_READY     | 19200000        |
    |    51     |     9    | DEV_DCC8_DCC_INPUT01_CLK                                                          | CLK_STATE_READY     | 0               |
    |    51     |    10    | DEV_DCC8_DCC_INPUT02_CLK                                                          | CLK_STATE_READY     | 12500000        |
    |    51     |    11    | DEV_DCC8_DCC_INPUT10_CLK                                                          | CLK_STATE_READY     | 250000000       |
    |    51     |    12    | DEV_DCC8_VBUS_CLK                                                                 | CLK_STATE_READY     | 125000000       |
    |    52     |     0    | DEV_DCC9_DCC_CLKSRC0_CLK                                                          | CLK_STATE_READY     | 250000000       |
    |    52     |     1    | DEV_DCC9_DCC_CLKSRC1_CLK                                                          | CLK_STATE_READY     | 125000000       |
    |    52     |     2    | DEV_DCC9_DCC_CLKSRC2_CLK                                                          | CLK_STATE_READY     | 0               |
    |    52     |     3    | DEV_DCC9_DCC_CLKSRC3_CLK                                                          | CLK_STATE_READY     | 0               |
    |    52     |     4    | DEV_DCC9_DCC_CLKSRC4_CLK                                                          | CLK_STATE_READY     | 0               |
    |    52     |     5    | DEV_DCC9_DCC_CLKSRC5_CLK                                                          | CLK_STATE_READY     | 294912000       |
    |    52     |     6    | DEV_DCC9_DCC_CLKSRC6_CLK                                                          | CLK_STATE_READY     | 196608000       |
    |    52     |     8    | DEV_DCC9_DCC_INPUT00_CLK                                                          | CLK_STATE_READY     | 19200000        |
    |    52     |     9    | DEV_DCC9_DCC_INPUT01_CLK                                                          | CLK_STATE_READY     | 0               |
    |    52     |    10    | DEV_DCC9_DCC_INPUT02_CLK                                                          | CLK_STATE_READY     | 12500000        |
    |    52     |    11    | DEV_DCC9_DCC_INPUT10_CLK                                                          | CLK_STATE_READY     | 250000000       |
    |    52     |    12    | DEV_DCC9_VBUS_CLK                                                                 | CLK_STATE_READY     | 125000000       |
    |   138     |     0    | DEV_DDR0_DDRSS_DDR_PLL_CLK                                                        | CLK_STATE_READY     | 1066500000      |
    |   138     |     1    | DEV_DDR0_DDRSS_VBUS_CLK                                                           | CLK_STATE_READY     | 250000000       |
    |   138     |     2    | DEV_DDR0_PLL_CTRL_CLK                                                             | CLK_STATE_READY     | 500000000       |
    |   138     |     7    | DEV_DDR0_DDRSS_CFG_CLK                                                            | CLK_STATE_READY     | 125000000       |
    |   139     |     0    | DEV_DDR1_DDRSS_DDR_PLL_CLK                                                        | CLK_STATE_READY     | 1066500000      |
    |   139     |     1    | DEV_DDR1_DDRSS_VBUS_CLK                                                           | CLK_STATE_READY     | 250000000       |
    |   139     |     2    | DEV_DDR1_PLL_CTRL_CLK                                                             | CLK_STATE_READY     | 500000000       |
    |   139     |     7    | DEV_DDR1_DDRSS_CFG_CLK                                                            | CLK_STATE_READY     | 125000000       |
    |    57     |     1    | DEV_DEBUGSS_WRAP0_ATB_CLK                                                         | CLK_STATE_READY     | 250000000       |
    |    57     |    16    | DEV_DEBUGSS_WRAP0_CSTPIU_TRACECLK                                                 | CLK_STATE_READY     | 0               |
    |    57     |    17    | DEV_DEBUGSS_WRAP0_CORE_CLK                                                        | CLK_STATE_READY     | 125000000       |
    |    57     |    28    | DEV_DEBUGSS_WRAP0_TREXPT_CLK                                                      | CLK_STATE_READY     | 300000000       |
    |    57     |    41    | DEV_DEBUGSS_WRAP0_JTAG_TCK                                                        | CLK_STATE_READY     | 0               |
    |   137     |     0    | DEV_DEBUGSUSPENDRTR0_INTR_CLK                                                     | CLK_STATE_READY     | 125000000       |
    |    58     |     0    | DEV_DMPAC0_CLK                                                                    | CLK_STATE_READY     | 480000000       |
    |    62     |     0    | DEV_DMPAC0_SDE_0_CLK                                                              | CLK_STATE_READY     | 480000000       |
    |   374     |     0    | DEV_DMPAC0_UTC_0_PSIL_LEAF_CLK                                                    | CLK_STATE_READY     | 480000000       |
    |   140     |     0    | DEV_DMPAC_VPAC_PSILSS0_MAIN_CLK                                                   | CLK_STATE_READY     | 250000000       |
    |   152     |     0    | DEV_DPHY_RX0_IO_RX_CL_L_M                                                         | CLK_STATE_READY     | 0               |
    |   152     |     1    | DEV_DPHY_RX0_PPI_RX_BYTE_CLK                                                      | CLK_STATE_READY     | 0               |
    |   152     |     2    | DEV_DPHY_RX0_MAIN_CLK_CLK                                                         | CLK_STATE_READY     | 125000000       |
    |   152     |     3    | DEV_DPHY_RX0_IO_RX_CL_L_P                                                         | CLK_STATE_READY     | 0               |
    |   152     |     4    | DEV_DPHY_RX0_JTAG_TCK                                                             | CLK_STATE_READY     | 0               |
    |   152     |     8    | DEV_DPHY_RX0_PPI_D_RX_ULPS_ESC                                                    | CLK_STATE_READY     | 0               |
    |   153     |     0    | DEV_DPHY_RX1_IO_RX_CL_L_M                                                         | CLK_STATE_READY     | 0               |
    |   153     |     1    | DEV_DPHY_RX1_PPI_RX_BYTE_CLK                                                      | CLK_STATE_READY     | 0               |
    |   153     |     2    | DEV_DPHY_RX1_MAIN_CLK_CLK                                                         | CLK_STATE_READY     | 125000000       |
    |   153     |     3    | DEV_DPHY_RX1_IO_RX_CL_L_P                                                         | CLK_STATE_READY     | 0               |
    |   153     |     4    | DEV_DPHY_RX1_JTAG_TCK                                                             | CLK_STATE_READY     | 0               |
    |   153     |     8    | DEV_DPHY_RX1_PPI_D_RX_ULPS_ESC                                                    | CLK_STATE_READY     | 0               |
    |   363     |     1    | DEV_DPHY_TX0_IP2_PPI_TXBYTECLKHS_CL_CLK                                           | CLK_STATE_READY     | 0               |
    |   363     |     2    | DEV_DPHY_TX0_IP1_PPI_TXBYTECLKHS_CL_CLK                                           | CLK_STATE_READY     | 0               |
    |   363     |     5    | DEV_DPHY_TX0_CLK                                                                  | CLK_STATE_READY     | 125000000       |
    |   363     |     8    | DEV_DPHY_TX0_PSM_CLK                                                              | CLK_STATE_READY     | 20000000        |
    |   363     |    12    | DEV_DPHY_TX0_CK_M                                                                 | CLK_STATE_READY     | 0               |
    |   363     |    14    | DEV_DPHY_TX0_DPHY_REF_CLK                                                         | CLK_STATE_READY     | 19200000        |
    |   363     |    15    | DEV_DPHY_TX0_DPHY_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                          | CLK_STATE_READY     | 19200000        |
    |   363     |    16    | DEV_DPHY_TX0_DPHY_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                           | CLK_STATE_READY     | 0               |
    |   363     |    17    | DEV_DPHY_TX0_DPHY_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK                | CLK_STATE_READY     | 125000000       |
    |   363     |    18    | DEV_DPHY_TX0_DPHY_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK                | CLK_STATE_READY     | 100000000       |
    |   363     |    19    | DEV_DPHY_TX0_TAP_TCK                                                              | CLK_STATE_READY     | 0               |
    |   363     |    20    | DEV_DPHY_TX0_CK_P                                                                 | CLK_STATE_READY     | 0               |
    |   363     |    22    | DEV_DPHY_TX0_IP1_PPI_M_TXCLKESC_CLK                                               | CLK_STATE_READY     | 20000000        |
    |   363     |    23    | DEV_DPHY_TX0_IP1_PPI_M_RXCLKESC_CLK                                               | CLK_STATE_READY     | 0               |
    |   363     |    24    | DEV_DPHY_TX0_IP2_PPI_M_TXCLKESC_CLK                                               | CLK_STATE_READY     | 20000000        |
    |   364     |     1    | DEV_DPHY_TX1_IP2_PPI_TXBYTECLKHS_CL_CLK                                           | CLK_STATE_READY     | 0               |
    |   364     |     2    | DEV_DPHY_TX1_IP1_PPI_TXBYTECLKHS_CL_CLK                                           | CLK_STATE_READY     | 0               |
    |   364     |     5    | DEV_DPHY_TX1_CLK                                                                  | CLK_STATE_READY     | 125000000       |
    |   364     |     8    | DEV_DPHY_TX1_PSM_CLK                                                              | CLK_STATE_READY     | 20000000        |
    |   364     |    12    | DEV_DPHY_TX1_CK_M                                                                 | CLK_STATE_READY     | 0               |
    |   364     |    14    | DEV_DPHY_TX1_DPHY_REF_CLK                                                         | CLK_STATE_READY     | 19200000        |
    |   364     |    15    | DEV_DPHY_TX1_DPHY_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                          | CLK_STATE_READY     | 19200000        |
    |   364     |    16    | DEV_DPHY_TX1_DPHY_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                           | CLK_STATE_READY     | 0               |
    |   364     |    17    | DEV_DPHY_TX1_DPHY_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK                | CLK_STATE_READY     | 125000000       |
    |   364     |    18    | DEV_DPHY_TX1_DPHY_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK                | CLK_STATE_READY     | 100000000       |
    |   364     |    19    | DEV_DPHY_TX1_TAP_TCK                                                              | CLK_STATE_READY     | 0               |
    |   364     |    20    | DEV_DPHY_TX1_CK_P                                                                 | CLK_STATE_READY     | 0               |
    |   364     |    22    | DEV_DPHY_TX1_IP1_PPI_M_TXCLKESC_CLK                                               | CLK_STATE_READY     | 20000000        |
    |   364     |    23    | DEV_DPHY_TX1_IP1_PPI_M_RXCLKESC_CLK                                               | CLK_STATE_READY     | 0               |
    |   158     |     0    | DEV_DSS0_DSS_FUNC_CLK                                                             | CLK_STATE_READY     | 600000000       |
    |   158     |     1    | DEV_DSS0_DSS_INST0_DPI_0_IN_CLK                                                   | CLK_STATE_READY     | 297000000       |
    |   158     |     2    | DEV_DSS0_DSS_INST0_DPI_0_IN_2X_CLK                                                | CLK_STATE_READY     | 594000000       |
    |   158     |     3    | DEV_DSS0_DSS_INST0_DPI_0_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK      | CLK_STATE_READY     | 594000000       |
    |   158     |     4    | DEV_DSS0_DSS_INST0_DPI_0_IN_2X_CLK_PARENT_DPI_1_PCLK_SEL_OUT0                     | CLK_STATE_READY     | 600000000       |
    |   158     |     5    | DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK                                                | CLK_STATE_READY     | 600000000       |
    |   158     |     6    | DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT0_CLK      | CLK_STATE_READY     | 51200000        |
    |   158     |     7    | DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK_PARENT_DPI0_EXT_CLKSEL_OUT0                    | CLK_STATE_READY     | 600000000       |
    |   158     |     8    | DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK_PARENT_DPI0_EXT_CLKSEL_OUT0_DUP0               | CLK_STATE_READY     | 600000000       |
    |   158     |     9    | DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK      | CLK_STATE_READY     | 594000000       |
    |   158     |    10    | DEV_DSS0_DSS_INST0_DPI_2_IN_CLK                                                   | CLK_STATE_READY     | 25600000        |
    |   158     |    11    | DEV_DSS0_DSS_INST0_DPI_2_IN_CLK_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK         | CLK_STATE_READY     | 297000000       |
    |   158     |    12    | DEV_DSS0_DSS_INST0_DPI_2_IN_CLK_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT0_CLK         | CLK_STATE_READY     | 25600000        |
    |   158     |    13    | DEV_DSS0_DSS_INST0_DPI_2_IN_CLK_PARENT_DPI0_EXT_CLKSEL_OUT0                       | CLK_STATE_READY     | 300000000       |
    |   158     |    14    | DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK                                                | CLK_STATE_READY     | 51200000        |
    |   158     |    15    | DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK      | CLK_STATE_READY     | 594000000       |
    |   158     |    16    | DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT0_CLK      | CLK_STATE_READY     | 51200000        |
    |   158     |    17    | DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK_PARENT_DPI0_EXT_CLKSEL_OUT0                    | CLK_STATE_READY     | 600000000       |
    |   158     |    18    | DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK                                                | CLK_STATE_READY     | 600000000       |
    |   158     |    19    | DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT1_CLK      | CLK_STATE_READY     | 594000000       |
    |   158     |    20    | DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT1_CLK      | CLK_STATE_READY     | 276480000       |
    |   158     |    21    | DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT1_CLK_DUP0 | CLK_STATE_READY     | 276480000       |
    |   158     |    22    | DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_DPI0_EXT_CLKSEL_OUT0                    | CLK_STATE_READY     | 600000000       |
    |   158     |    23    | DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_DPI0_EXT_CLKSEL_OUT0_DUP0               | CLK_STATE_READY     | 600000000       |
    |   158     |    24    | DEV_DSS0_DSS_INST0_PARA_1_OUT_CLK                                                 | CLK_STATE_READY     | 0               |
    |   158     |    25    | DEV_DSS0_DSS_INST0_PARA_3_OUT_CLK                                                 | CLK_STATE_READY     | 0               |
    |   158     |    26    | DEV_DSS0_DSS_INST0_DPI_0_OUT_CLK                                                  | CLK_STATE_READY     | 0               |
    |   158     |    27    | DEV_DSS0_DSS_INST0_DPI_1_OUT_CLK                                                  | CLK_STATE_READY     | 0               |
    |   158     |    28    | DEV_DSS0_DSS_INST0_DPI_2_OUT_CLK                                                  | CLK_STATE_READY     | 0               |
    |   158     |    29    | DEV_DSS0_DSS_INST0_DPI_3_OUT_CLK                                                  | CLK_STATE_READY     | 0               |
    |   158     |    30    | DEV_DSS0_DSS_INST0_DPI_0_OUT_2X_CLK                                               | CLK_STATE_READY     | 0               |
    |   154     |     0    | DEV_DSS_DSI0_PLL_CTRL_CLK                                                         | CLK_STATE_READY     | 500000000       |
    |   154     |     1    | DEV_DSS_DSI0_SYS_CLK                                                              | CLK_STATE_READY     | 250000000       |
    |   154     |     2    | DEV_DSS_DSI0_DPHY_0_RX_ESC_CLK                                                    | CLK_STATE_READY     | 0               |
    |   154     |     3    | DEV_DSS_DSI0_DPHY_0_TX_ESC_CLK                                                    | CLK_STATE_READY     | 20000000        |
    |   154     |     4    | DEV_DSS_DSI0_DPI_0_CLK                                                            | CLK_STATE_READY     | 0               |
    |   154     |     5    | DEV_DSS_DSI0_PPI_0_TXBYTECLKHS_CL_CLK                                             | CLK_STATE_READY     | 0               |
    |   155     |     0    | DEV_DSS_DSI1_PLL_CTRL_CLK                                                         | CLK_STATE_READY     | 500000000       |
    |   155     |     1    | DEV_DSS_DSI1_SYS_CLK                                                              | CLK_STATE_READY     | 250000000       |
    |   155     |     2    | DEV_DSS_DSI1_DPHY_0_RX_ESC_CLK                                                    | CLK_STATE_NOT_READY | 0               |
    |   155     |     3    | DEV_DSS_DSI1_DPHY_0_TX_ESC_CLK                                                    | CLK_STATE_READY     | 20000000        |
    |   155     |     4    | DEV_DSS_DSI1_DPI_0_CLK                                                            | CLK_STATE_NOT_READY | 0               |
    |   155     |     5    | DEV_DSS_DSI1_PPI_0_TXBYTECLKHS_CL_CLK                                             | CLK_STATE_NOT_READY | 0               |
    |   156     |     0    | DEV_DSS_EDP0_PHY_LN0_RXCLK                                                        | CLK_STATE_READY     | 0               |
    |   156     |     1    | DEV_DSS_EDP0_PHY_LN2_TXCLK                                                        | CLK_STATE_READY     | 0               |
    |   156     |     2    | DEV_DSS_EDP0_PHY_LN3_RXFCLK                                                       | CLK_STATE_READY     | 0               |
    |   156     |     3    | DEV_DSS_EDP0_PHY_LN2_TXMCLK                                                       | CLK_STATE_READY     | 0               |
    |   156     |     4    | DEV_DSS_EDP0_PHY_LN3_REFCLK                                                       | CLK_STATE_READY     | 0               |
    |   156     |     6    | DEV_DSS_EDP0_DPI_2_2X_CLK                                                         | CLK_STATE_READY     | 0               |
    |   156     |     7    | DEV_DSS_EDP0_PHY_LN0_TXCLK                                                        | CLK_STATE_READY     | 0               |
    |   156     |     8    | DEV_DSS_EDP0_PHY_LN2_TXFCLK                                                       | CLK_STATE_READY     | 0               |
    |   156     |     9    | DEV_DSS_EDP0_DPI_3_CLK                                                            | CLK_STATE_READY     | 0               |
    |   156     |    10    | DEV_DSS_EDP0_PHY_LN1_RXCLK                                                        | CLK_STATE_READY     | 0               |
    |   156     |    11    | DEV_DSS_EDP0_PHY_LN1_TXCLK                                                        | CLK_STATE_READY     | 0               |
    |   156     |    12    | DEV_DSS_EDP0_PHY_LN1_RXFCLK                                                       | CLK_STATE_READY     | 0               |
    |   156     |    13    | DEV_DSS_EDP0_DPI_5_CLK                                                            | CLK_STATE_READY     | 0               |
    |   156     |    14    | DEV_DSS_EDP0_PHY_LN2_RXCLK                                                        | CLK_STATE_READY     | 0               |
    |   156     |    16    | DEV_DSS_EDP0_PHY_LN1_TXMCLK                                                       | CLK_STATE_READY     | 0               |
    |   156     |    18    | DEV_DSS_EDP0_DPI_2_CLK                                                            | CLK_STATE_READY     | 0               |
    |   156     |    19    | DEV_DSS_EDP0_DPTX_MOD_CLK                                                         | CLK_STATE_READY     | 125000000       |
    |   156     |    20    | DEV_DSS_EDP0_PHY_LN1_REFCLK                                                       | CLK_STATE_READY     | 0               |
    |   156     |    21    | DEV_DSS_EDP0_PHY_LN1_TXFCLK                                                       | CLK_STATE_READY     | 0               |
    |   156     |    22    | DEV_DSS_EDP0_PHY_LN0_RXFCLK                                                       | CLK_STATE_READY     | 0               |
    |   156     |    24    | DEV_DSS_EDP0_PHY_LN3_TXMCLK                                                       | CLK_STATE_READY     | 0               |
    |   156     |    25    | DEV_DSS_EDP0_PLL_CTRL_CLK                                                         | CLK_STATE_READY     | 500000000       |
    |   156     |    26    | DEV_DSS_EDP0_PHY_LN0_TXFCLK                                                       | CLK_STATE_READY     | 0               |
    |   156     |    27    | DEV_DSS_EDP0_PHY_LN3_TXFCLK                                                       | CLK_STATE_READY     | 0               |
    |   156     |    28    | DEV_DSS_EDP0_PHY_LN3_TXCLK                                                        | CLK_STATE_READY     | 0               |
    |   156     |    29    | DEV_DSS_EDP0_PHY_LN2_REFCLK                                                       | CLK_STATE_READY     | 0               |
    |   156     |    30    | DEV_DSS_EDP0_DPI_4_CLK                                                            | CLK_STATE_READY     | 0               |
    |   156     |    31    | DEV_DSS_EDP0_PHY_LN0_TXMCLK                                                       | CLK_STATE_READY     | 0               |
    |   156     |    33    | DEV_DSS_EDP0_PHY_LN0_REFCLK                                                       | CLK_STATE_READY     | 0               |
    |   156     |    34    | DEV_DSS_EDP0_PHY_LN3_RXCLK                                                        | CLK_STATE_READY     | 0               |
    |   156     |    35    | DEV_DSS_EDP0_AIF_I2S_CLK                                                          | CLK_STATE_READY     | 0               |
    |   156     |    36    | DEV_DSS_EDP0_PHY_LN2_RXFCLK                                                       | CLK_STATE_READY     | 0               |
    |    92     |     0    | DEV_ECAP0_VBUS_CLK                                                                | CLK_STATE_READY     | 125000000       |
    |    93     |     0    | DEV_ECAP1_VBUS_CLK                                                                | CLK_STATE_READY     | 125000000       |
    |    94     |     0    | DEV_ECAP2_VBUS_CLK                                                                | CLK_STATE_READY     | 125000000       |
    |    95     |     0    | DEV_ELM0_VBUSP_CLK                                                                | CLK_STATE_READY     | 125000000       |
    |   160     |     0    | DEV_EPWM0_VBUSP_CLK                                                               | CLK_STATE_READY     | 125000000       |
    |   161     |     0    | DEV_EPWM1_VBUSP_CLK                                                               | CLK_STATE_READY     | 125000000       |
    |   162     |     0    | DEV_EPWM2_VBUSP_CLK                                                               | CLK_STATE_READY     | 125000000       |
    |   163     |     0    | DEV_EPWM3_VBUSP_CLK                                                               | CLK_STATE_READY     | 125000000       |
    |   164     |     0    | DEV_EPWM4_VBUSP_CLK                                                               | CLK_STATE_READY     | 125000000       |
    |   165     |     0    | DEV_EPWM5_VBUSP_CLK                                                               | CLK_STATE_READY     | 125000000       |
    |   100     |     0    | DEV_EQEP0_VBUS_CLK                                                                | CLK_STATE_READY     | 125000000       |
    |   101     |     0    | DEV_EQEP1_VBUS_CLK                                                                | CLK_STATE_READY     | 125000000       |
    |   102     |     0    | DEV_EQEP2_VBUS_CLK                                                                | CLK_STATE_READY     | 125000000       |
    |   103     |     0    | DEV_ESM0_CLK                                                                      | CLK_STATE_READY     | 125000000       |
    |   111     |     0    | DEV_GPIO0_MMR_CLK                                                                 | CLK_STATE_READY     | 125000000       |
    |   112     |     0    | DEV_GPIO2_MMR_CLK                                                                 | CLK_STATE_READY     | 125000000       |
    |   113     |     0    | DEV_GPIO4_MMR_CLK                                                                 | CLK_STATE_READY     | 125000000       |
    |   114     |     0    | DEV_GPIO6_MMR_CLK                                                                 | CLK_STATE_READY     | 125000000       |
    |   148     |     0    | DEV_GPIOMUX_INTRTR0_INTR_CLK                                                      | CLK_STATE_READY     | 125000000       |
    |   117     |     0    | DEV_GPMC0_VBUSM_CLK                                                               | CLK_STATE_READY     | 250000000       |
    |   117     |     1    | DEV_GPMC0_PO_GPMC_DEV_CLK                                                         | CLK_STATE_READY     | 0               |
    |   117     |     2    | DEV_GPMC0_FUNC_CLK                                                                | CLK_STATE_READY     | 133333333       |
    |   117     |     3    | DEV_GPMC0_FUNC_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT3_CLK                       | CLK_STATE_READY     | 133333333       |
    |   117     |     4    | DEV_GPMC0_FUNC_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK6                      | CLK_STATE_READY     | 100000000       |
    |   117     |     5    | DEV_GPMC0_FUNC_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK4                      | CLK_STATE_READY     | 150000000       |
    |   117     |     6    | DEV_GPMC0_FUNC_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK4              | CLK_STATE_READY     | 125000000       |
    |   117     |     7    | DEV_GPMC0_PI_GPMC_RET_CLK                                                         | CLK_STATE_READY     | 0               |
    |    61     |     0    | DEV_GTC0_VBUSP_CLK                                                                | CLK_STATE_READY     | 125000000       |
    |    61     |     1    | DEV_GTC0_GTC_CLK                                                                  | CLK_STATE_READY     | 200000000       |
    |    61     |     2    | DEV_GTC0_GTC_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK                         | CLK_STATE_READY     | 250000000       |
    |    61     |     3    | DEV_GTC0_GTC_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK                       | CLK_STATE_READY     | 200000000       |
    |    61     |     4    | DEV_GTC0_GTC_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT                             | CLK_STATE_READY     | 0               |
    |    61     |     5    | DEV_GTC0_GTC_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT                                 | CLK_STATE_READY     | 0               |
    |    61     |     6    | DEV_GTC0_GTC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                               | CLK_STATE_READY     | 0               |
    |    61     |     7    | DEV_GTC0_GTC_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT                                   | CLK_STATE_READY     | 0               |
    |    61     |     8    | DEV_GTC0_GTC_CLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN0_TXMCLK                        | CLK_STATE_READY     | 0               |
    |    61     |     9    | DEV_GTC0_GTC_CLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN1_TXMCLK                        | CLK_STATE_READY     | 0               |
    |    61     |    10    | DEV_GTC0_GTC_CLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN2_TXMCLK                        | CLK_STATE_READY     | 0               |
    |    61     |    11    | DEV_GTC0_GTC_CLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN3_TXMCLK                        | CLK_STATE_READY     | 0               |
    |    61     |    16    | DEV_GTC0_GTC_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK                          | CLK_STATE_READY     | 500000000       |
    |    61     |    17    | DEV_GTC0_GTC_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK                 | CLK_STATE_READY     | 500000000       |
    |   214     |     0    | DEV_I2C0_PORSCL                                                                   | CLK_STATE_READY     | 0               |
    |   214     |     1    | DEV_I2C0_PISYS_CLK                                                                | CLK_STATE_READY     | 96000000        |
    |   214     |     2    | DEV_I2C0_CLK                                                                      | CLK_STATE_READY     | 125000000       |
    |   214     |     3    | DEV_I2C0_PISCL                                                                    | CLK_STATE_READY     | 0               |
    |   215     |     0    | DEV_I2C1_PORSCL                                                                   | CLK_STATE_READY     | 0               |
    |   215     |     1    | DEV_I2C1_PISYS_CLK                                                                | CLK_STATE_READY     | 96000000        |
    |   215     |     2    | DEV_I2C1_CLK                                                                      | CLK_STATE_READY     | 125000000       |
    |   215     |     3    | DEV_I2C1_PISCL                                                                    | CLK_STATE_READY     | 0               |
    |   216     |     0    | DEV_I2C2_PORSCL                                                                   | CLK_STATE_READY     | 0               |
    |   216     |     1    | DEV_I2C2_PISYS_CLK                                                                | CLK_STATE_READY     | 96000000        |
    |   216     |     2    | DEV_I2C2_CLK                                                                      | CLK_STATE_READY     | 125000000       |
    |   216     |     3    | DEV_I2C2_PISCL                                                                    | CLK_STATE_READY     | 0               |
    |   217     |     0    | DEV_I2C3_PORSCL                                                                   | CLK_STATE_READY     | 0               |
    |   217     |     1    | DEV_I2C3_PISYS_CLK                                                                | CLK_STATE_READY     | 96000000        |
    |   217     |     2    | DEV_I2C3_CLK                                                                      | CLK_STATE_READY     | 125000000       |
    |   217     |     3    | DEV_I2C3_PISCL                                                                    | CLK_STATE_READY     | 0               |
    |   218     |     0    | DEV_I2C4_PORSCL                                                                   | CLK_STATE_READY     | 0               |
    |   218     |     1    | DEV_I2C4_PISYS_CLK                                                                | CLK_STATE_READY     | 96000000        |
    |   218     |     2    | DEV_I2C4_CLK                                                                      | CLK_STATE_READY     | 125000000       |
    |   218     |     3    | DEV_I2C4_PISCL                                                                    | CLK_STATE_READY     | 0               |
    |   219     |     0    | DEV_I2C5_PORSCL                                                                   | CLK_STATE_READY     | 0               |
    |   219     |     1    | DEV_I2C5_PISYS_CLK                                                                | CLK_STATE_READY     | 96000000        |
    |   219     |     2    | DEV_I2C5_CLK                                                                      | CLK_STATE_READY     | 125000000       |
    |   219     |     3    | DEV_I2C5_PISCL                                                                    | CLK_STATE_READY     | 0               |
    |   220     |     0    | DEV_I2C6_PORSCL                                                                   | CLK_STATE_READY     | 0               |
    |   220     |     1    | DEV_I2C6_PISYS_CLK                                                                | CLK_STATE_READY     | 96000000        |
    |   220     |     2    | DEV_I2C6_CLK                                                                      | CLK_STATE_READY     | 125000000       |
    |   220     |     3    | DEV_I2C6_PISCL                                                                    | CLK_STATE_READY     | 0               |
    |   130     |     0    | DEV_J7AEP_GPU_BXS464_WRAP0_GPU_SS_0_PLL_CTRL_CLK                                  | CLK_STATE_READY     | 500000000       |
    |   130     |     1    | DEV_J7AEP_GPU_BXS464_WRAP0_GPU_SS_0_GPU_PLL_CLK                                   | CLK_STATE_READY     | 800000000       |
    |   131     |     0    | DEV_J7AM_32_64_ATB_FUNNEL0_DBG_CLK                                                | CLK_STATE_READY     | 250000000       |
    |   132     |     0    | DEV_J7AM_32_64_ATB_FUNNEL1_DBG_CLK                                                | CLK_STATE_READY     | 250000000       |
    |   133     |     0    | DEV_J7AM_32_64_ATB_FUNNEL2_DBG_CLK                                                | CLK_STATE_READY     | 250000000       |
    |   135     |     0    | DEV_J7AM_BOLT_PGD0_WKUP_OSC0_CLK                                                  | CLK_STATE_READY     | 19200000        |
    |   141     |     0    | DEV_J7AM_HWA_ATB_FUNNEL0_DBG_CLK                                                  | CLK_STATE_READY     | 250000000       |
    |   142     |     0    | DEV_J7AM_MAIN_16FF0_WKUP_OSC0_CLK                                                 | CLK_STATE_READY     | 19200000        |
    |   144     |     0    | DEV_J7AM_PULSAR_ATB_FUNNEL0_DBG_CLK                                               | CLK_STATE_READY     | 250000000       |
    |   120     |     0    | DEV_LED0_VBUS_CLK                                                                 | CLK_STATE_READY     | 250000000       |
    |   120     |     1    | DEV_LED0_LED_CLK                                                                  | CLK_STATE_READY     | 0               |
    |   121     |     0    | DEV_MAIN2MCU_LVL_INTRTR0_INTR_CLK                                                 | CLK_STATE_READY     | 125000000       |
    |   122     |     0    | DEV_MAIN2MCU_PLS_INTRTR0_INTR_CLK                                                 | CLK_STATE_READY     | 125000000       |
    |   182     |     0    | DEV_MCAN0_MCANSS_HCLK_CLK                                                         | CLK_STATE_READY     | 125000000       |
    |   182     |     1    | DEV_MCAN0_MCANSS_CCLK_CLK                                                         | CLK_STATE_READY     | 80000000        |
    |   182     |     2    | DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK                | CLK_STATE_READY     | 80000000        |
    |   182     |     3    | DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                      | CLK_STATE_READY     | 0               |
    |   182     |     4    | DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                           | CLK_STATE_READY     | 0               |
    |   182     |     5    | DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                          | CLK_STATE_READY     | 19200000        |
    |   182     |     6    | DEV_MCAN0_MCANSS_CAN_RXD                                                          | CLK_STATE_READY     | 0               |
    |   183     |     0    | DEV_MCAN1_MCANSS_HCLK_CLK                                                         | CLK_STATE_READY     | 125000000       |
    |   183     |     1    | DEV_MCAN1_MCANSS_CCLK_CLK                                                         | CLK_STATE_READY     | 80000000        |
    |   183     |     2    | DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK                | CLK_STATE_READY     | 80000000        |
    |   183     |     3    | DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                      | CLK_STATE_READY     | 0               |
    |   183     |     4    | DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                           | CLK_STATE_READY     | 0               |
    |   183     |     5    | DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                          | CLK_STATE_READY     | 19200000        |
    |   183     |     6    | DEV_MCAN1_MCANSS_CAN_RXD                                                          | CLK_STATE_READY     | 0               |
    |   192     |     0    | DEV_MCAN10_MCANSS_HCLK_CLK                                                        | CLK_STATE_READY     | 125000000       |
    |   192     |     1    | DEV_MCAN10_MCANSS_CCLK_CLK                                                        | CLK_STATE_READY     | 80000000        |
    |   192     |     2    | DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK               | CLK_STATE_READY     | 80000000        |
    |   192     |     3    | DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                     | CLK_STATE_READY     | 0               |
    |   192     |     4    | DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                          | CLK_STATE_READY     | 0               |
    |   192     |     5    | DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                         | CLK_STATE_READY     | 19200000        |
    |   192     |     6    | DEV_MCAN10_MCANSS_CAN_RXD                                                         | CLK_STATE_READY     | 0               |
    |   193     |     0    | DEV_MCAN11_MCANSS_HCLK_CLK                                                        | CLK_STATE_READY     | 125000000       |
    |   193     |     1    | DEV_MCAN11_MCANSS_CCLK_CLK                                                        | CLK_STATE_READY     | 80000000        |
    |   193     |     2    | DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK               | CLK_STATE_READY     | 80000000        |
    |   193     |     3    | DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                     | CLK_STATE_READY     | 0               |
    |   193     |     4    | DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                          | CLK_STATE_READY     | 0               |
    |   193     |     5    | DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                         | CLK_STATE_READY     | 19200000        |
    |   193     |     6    | DEV_MCAN11_MCANSS_CAN_RXD                                                         | CLK_STATE_READY     | 0               |
    |   194     |     0    | DEV_MCAN12_MCANSS_HCLK_CLK                                                        | CLK_STATE_READY     | 125000000       |
    |   194     |     1    | DEV_MCAN12_MCANSS_CCLK_CLK                                                        | CLK_STATE_READY     | 80000000        |
    |   194     |     2    | DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK               | CLK_STATE_READY     | 80000000        |
    |   194     |     3    | DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                     | CLK_STATE_READY     | 0               |
    |   194     |     4    | DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                          | CLK_STATE_READY     | 0               |
    |   194     |     5    | DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                         | CLK_STATE_READY     | 19200000        |
    |   194     |     6    | DEV_MCAN12_MCANSS_CAN_RXD                                                         | CLK_STATE_READY     | 0               |
    |   195     |     0    | DEV_MCAN13_MCANSS_HCLK_CLK                                                        | CLK_STATE_READY     | 125000000       |
    |   195     |     1    | DEV_MCAN13_MCANSS_CCLK_CLK                                                        | CLK_STATE_READY     | 80000000        |
    |   195     |     2    | DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK               | CLK_STATE_READY     | 80000000        |
    |   195     |     3    | DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                     | CLK_STATE_READY     | 0               |
    |   195     |     4    | DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                          | CLK_STATE_READY     | 0               |
    |   195     |     5    | DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                         | CLK_STATE_READY     | 19200000        |
    |   195     |     6    | DEV_MCAN13_MCANSS_CAN_RXD                                                         | CLK_STATE_READY     | 0               |
    |   197     |     0    | DEV_MCAN14_MCANSS_HCLK_CLK                                                        | CLK_STATE_READY     | 125000000       |
    |   197     |     1    | DEV_MCAN14_MCANSS_CCLK_CLK                                                        | CLK_STATE_READY     | 80000000        |
    |   197     |     2    | DEV_MCAN14_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK               | CLK_STATE_READY     | 80000000        |
    |   197     |     3    | DEV_MCAN14_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                     | CLK_STATE_READY     | 0               |
    |   197     |     4    | DEV_MCAN14_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                          | CLK_STATE_READY     | 0               |
    |   197     |     5    | DEV_MCAN14_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                         | CLK_STATE_READY     | 19200000        |
    |   197     |     6    | DEV_MCAN14_MCANSS_CAN_RXD                                                         | CLK_STATE_READY     | 0               |
    |   199     |     0    | DEV_MCAN15_MCANSS_HCLK_CLK                                                        | CLK_STATE_READY     | 125000000       |
    |   199     |     1    | DEV_MCAN15_MCANSS_CCLK_CLK                                                        | CLK_STATE_READY     | 80000000        |
    |   199     |     2    | DEV_MCAN15_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK               | CLK_STATE_READY     | 80000000        |
    |   199     |     3    | DEV_MCAN15_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                     | CLK_STATE_READY     | 0               |
    |   199     |     4    | DEV_MCAN15_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                          | CLK_STATE_READY     | 0               |
    |   199     |     5    | DEV_MCAN15_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                         | CLK_STATE_READY     | 19200000        |
    |   199     |     6    | DEV_MCAN15_MCANSS_CAN_RXD                                                         | CLK_STATE_READY     | 0               |
    |   201     |     0    | DEV_MCAN16_MCANSS_HCLK_CLK                                                        | CLK_STATE_READY     | 125000000       |
    |   201     |     1    | DEV_MCAN16_MCANSS_CCLK_CLK                                                        | CLK_STATE_READY     | 80000000        |
    |   201     |     2    | DEV_MCAN16_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK               | CLK_STATE_READY     | 80000000        |
    |   201     |     3    | DEV_MCAN16_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                     | CLK_STATE_READY     | 0               |
    |   201     |     4    | DEV_MCAN16_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                          | CLK_STATE_READY     | 0               |
    |   201     |     5    | DEV_MCAN16_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                         | CLK_STATE_READY     | 19200000        |
    |   201     |     6    | DEV_MCAN16_MCANSS_CAN_RXD                                                         | CLK_STATE_READY     | 0               |
    |   206     |     0    | DEV_MCAN17_MCANSS_HCLK_CLK                                                        | CLK_STATE_READY     | 125000000       |
    |   206     |     1    | DEV_MCAN17_MCANSS_CCLK_CLK                                                        | CLK_STATE_READY     | 80000000        |
    |   206     |     2    | DEV_MCAN17_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK               | CLK_STATE_READY     | 80000000        |
    |   206     |     3    | DEV_MCAN17_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                     | CLK_STATE_READY     | 0               |
    |   206     |     4    | DEV_MCAN17_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                          | CLK_STATE_READY     | 0               |
    |   206     |     5    | DEV_MCAN17_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                         | CLK_STATE_READY     | 19200000        |
    |   206     |     6    | DEV_MCAN17_MCANSS_CAN_RXD                                                         | CLK_STATE_READY     | 0               |
    |   184     |     0    | DEV_MCAN2_MCANSS_HCLK_CLK                                                         | CLK_STATE_READY     | 125000000       |
    |   184     |     1    | DEV_MCAN2_MCANSS_CCLK_CLK                                                         | CLK_STATE_READY     | 80000000        |
    |   184     |     2    | DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK                | CLK_STATE_READY     | 80000000        |
    |   184     |     3    | DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                      | CLK_STATE_READY     | 0               |
    |   184     |     4    | DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                           | CLK_STATE_READY     | 0               |
    |   184     |     5    | DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                          | CLK_STATE_READY     | 19200000        |
    |   184     |     6    | DEV_MCAN2_MCANSS_CAN_RXD                                                          | CLK_STATE_READY     | 0               |
    |   185     |     0    | DEV_MCAN3_MCANSS_HCLK_CLK                                                         | CLK_STATE_READY     | 125000000       |
    |   185     |     1    | DEV_MCAN3_MCANSS_CCLK_CLK                                                         | CLK_STATE_READY     | 80000000        |
    |   185     |     2    | DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK                | CLK_STATE_READY     | 80000000        |
    |   185     |     3    | DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                      | CLK_STATE_READY     | 0               |
    |   185     |     4    | DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                           | CLK_STATE_READY     | 0               |
    |   185     |     5    | DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                          | CLK_STATE_READY     | 19200000        |
    |   185     |     6    | DEV_MCAN3_MCANSS_CAN_RXD                                                          | CLK_STATE_READY     | 0               |
    |   186     |     0    | DEV_MCAN4_MCANSS_HCLK_CLK                                                         | CLK_STATE_READY     | 125000000       |
    |   186     |     1    | DEV_MCAN4_MCANSS_CCLK_CLK                                                         | CLK_STATE_READY     | 80000000        |
    |   186     |     2    | DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK                | CLK_STATE_READY     | 80000000        |
    |   186     |     3    | DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                      | CLK_STATE_READY     | 0               |
    |   186     |     4    | DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                           | CLK_STATE_READY     | 0               |
    |   186     |     5    | DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                          | CLK_STATE_READY     | 19200000        |
    |   186     |     6    | DEV_MCAN4_MCANSS_CAN_RXD                                                          | CLK_STATE_READY     | 0               |
    |   187     |     0    | DEV_MCAN5_MCANSS_HCLK_CLK                                                         | CLK_STATE_READY     | 125000000       |
    |   187     |     1    | DEV_MCAN5_MCANSS_CCLK_CLK                                                         | CLK_STATE_READY     | 80000000        |
    |   187     |     2    | DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK                | CLK_STATE_READY     | 80000000        |
    |   187     |     3    | DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                      | CLK_STATE_READY     | 0               |
    |   187     |     4    | DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                           | CLK_STATE_READY     | 0               |
    |   187     |     5    | DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                          | CLK_STATE_READY     | 19200000        |
    |   187     |     6    | DEV_MCAN5_MCANSS_CAN_RXD                                                          | CLK_STATE_READY     | 0               |
    |   188     |     0    | DEV_MCAN6_MCANSS_HCLK_CLK                                                         | CLK_STATE_READY     | 125000000       |
    |   188     |     1    | DEV_MCAN6_MCANSS_CCLK_CLK                                                         | CLK_STATE_READY     | 80000000        |
    |   188     |     2    | DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK                | CLK_STATE_READY     | 80000000        |
    |   188     |     3    | DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                      | CLK_STATE_READY     | 0               |
    |   188     |     4    | DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                           | CLK_STATE_READY     | 0               |
    |   188     |     5    | DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                          | CLK_STATE_READY     | 19200000        |
    |   188     |     6    | DEV_MCAN6_MCANSS_CAN_RXD                                                          | CLK_STATE_READY     | 0               |
    |   189     |     0    | DEV_MCAN7_MCANSS_HCLK_CLK                                                         | CLK_STATE_READY     | 125000000       |
    |   189     |     1    | DEV_MCAN7_MCANSS_CCLK_CLK                                                         | CLK_STATE_READY     | 80000000        |
    |   189     |     2    | DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK                | CLK_STATE_READY     | 80000000        |
    |   189     |     3    | DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                      | CLK_STATE_READY     | 0               |
    |   189     |     4    | DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                           | CLK_STATE_READY     | 0               |
    |   189     |     5    | DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                          | CLK_STATE_READY     | 19200000        |
    |   189     |     6    | DEV_MCAN7_MCANSS_CAN_RXD                                                          | CLK_STATE_READY     | 0               |
    |   190     |     0    | DEV_MCAN8_MCANSS_HCLK_CLK                                                         | CLK_STATE_READY     | 125000000       |
    |   190     |     1    | DEV_MCAN8_MCANSS_CCLK_CLK                                                         | CLK_STATE_READY     | 80000000        |
    |   190     |     2    | DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK                | CLK_STATE_READY     | 80000000        |
    |   190     |     3    | DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                      | CLK_STATE_READY     | 0               |
    |   190     |     4    | DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                           | CLK_STATE_READY     | 0               |
    |   190     |     5    | DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                          | CLK_STATE_READY     | 19200000        |
    |   190     |     6    | DEV_MCAN8_MCANSS_CAN_RXD                                                          | CLK_STATE_READY     | 0               |
    |   191     |     0    | DEV_MCAN9_MCANSS_HCLK_CLK                                                         | CLK_STATE_READY     | 125000000       |
    |   191     |     1    | DEV_MCAN9_MCANSS_CCLK_CLK                                                         | CLK_STATE_READY     | 80000000        |
    |   191     |     2    | DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK                | CLK_STATE_READY     | 80000000        |
    |   191     |     3    | DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                      | CLK_STATE_READY     | 0               |
    |   191     |     4    | DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                           | CLK_STATE_READY     | 0               |
    |   191     |     5    | DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                          | CLK_STATE_READY     | 19200000        |
    |   191     |     6    | DEV_MCAN9_MCANSS_CAN_RXD                                                          | CLK_STATE_READY     | 0               |
    |   209     |     0    | DEV_MCASP0_AUX_CLK                                                                | CLK_STATE_READY     | 196608000       |
    |   209     |     1    | DEV_MCASP0_AUX_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT0_CLK                       | CLK_STATE_READY     | 196608000       |
    |   209     |     2    | DEV_MCASP0_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK                       | CLK_STATE_READY     | 200000000       |
    |   209     |     5    | DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT                        | CLK_STATE_NOT_READY | 0               |
    |   209     |     6    | DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1                      | CLK_STATE_NOT_READY | 0               |
    |   209     |     7    | DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2                      | CLK_STATE_NOT_READY | 0               |
    |   209     |     8    | DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3                      | CLK_STATE_NOT_READY | 0               |
    |   209     |     9    | DEV_MCASP0_MCASP_AFSX_POUT                                                        | CLK_STATE_READY     | 0               |
    |   209     |    10    | DEV_MCASP0_MCASP_AHCLKR_POUT                                                      | CLK_STATE_READY     | 0               |
    |   209     |    11    | DEV_MCASP0_MCASP_AHCLKR_PIN                                                       | CLK_STATE_READY     | 0               |
    |   209     |    12    | DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT                         | CLK_STATE_READY     | 0               |
    |   209     |    13    | DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT                        | CLK_STATE_READY     | 19200000        |
    |   209     |    14    | DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT                  | CLK_STATE_READY     | 0               |
    |   209     |    15    | DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT                  | CLK_STATE_READY     | 0               |
    |   209     |    20    | DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT               | CLK_STATE_NOT_READY | 0               |
    |   209     |    21    | DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1             | CLK_STATE_NOT_READY | 0               |
    |   209     |    22    | DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2             | CLK_STATE_NOT_READY | 0               |
    |   209     |    23    | DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3             | CLK_STATE_NOT_READY | 0               |
    |   209     |    28    | DEV_MCASP0_MCASP_ACLKX_POUT                                                       | CLK_STATE_READY     | 0               |
    |   209     |    29    | DEV_MCASP0_MCASP_AFSR_POUT                                                        | CLK_STATE_READY     | 0               |
    |   209     |    30    | DEV_MCASP0_VBUSP_CLK                                                              | CLK_STATE_READY     | 250000000       |
    |   209     |    31    | DEV_MCASP0_MCASP_ACLKR_POUT                                                       | CLK_STATE_READY     | 0               |
    |   209     |    32    | DEV_MCASP0_MCASP_AHCLKX_POUT                                                      | CLK_STATE_READY     | 0               |
    |   209     |    33    | DEV_MCASP0_MCASP_ACLKX_PIN                                                        | CLK_STATE_READY     | 0               |
    |   209     |    34    | DEV_MCASP0_MCASP_AHCLKX_PIN                                                       | CLK_STATE_READY     | 0               |
    |   209     |    35    | DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT                         | CLK_STATE_READY     | 0               |
    |   209     |    36    | DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT                        | CLK_STATE_READY     | 19200000        |
    |   209     |    37    | DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT                  | CLK_STATE_READY     | 0               |
    |   209     |    38    | DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT                  | CLK_STATE_READY     | 0               |
    |   209     |    43    | DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT               | CLK_STATE_NOT_READY | 0               |
    |   209     |    44    | DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1             | CLK_STATE_NOT_READY | 0               |
    |   209     |    45    | DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2             | CLK_STATE_NOT_READY | 0               |
    |   209     |    46    | DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3             | CLK_STATE_NOT_READY | 0               |
    |   209     |    51    | DEV_MCASP0_MCASP_ACLKR_PIN                                                        | CLK_STATE_READY     | 0               |
    |   210     |     0    | DEV_MCASP1_AUX_CLK                                                                | CLK_STATE_READY     | 196608000       |
    |   210     |     1    | DEV_MCASP1_AUX_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT0_CLK                       | CLK_STATE_READY     | 196608000       |
    |   210     |     2    | DEV_MCASP1_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK                       | CLK_STATE_READY     | 200000000       |
    |   210     |     5    | DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT                        | CLK_STATE_NOT_READY | 0               |
    |   210     |     6    | DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1                      | CLK_STATE_NOT_READY | 0               |
    |   210     |     7    | DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2                      | CLK_STATE_NOT_READY | 0               |
    |   210     |     8    | DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3                      | CLK_STATE_NOT_READY | 0               |
    |   210     |     9    | DEV_MCASP1_MCASP_AFSX_POUT                                                        | CLK_STATE_READY     | 0               |
    |   210     |    10    | DEV_MCASP1_MCASP_AHCLKR_POUT                                                      | CLK_STATE_READY     | 0               |
    |   210     |    11    | DEV_MCASP1_MCASP_AHCLKR_PIN                                                       | CLK_STATE_READY     | 0               |
    |   210     |    12    | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT                         | CLK_STATE_READY     | 0               |
    |   210     |    13    | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT                        | CLK_STATE_READY     | 19200000        |
    |   210     |    14    | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT                  | CLK_STATE_READY     | 0               |
    |   210     |    15    | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT                  | CLK_STATE_READY     | 0               |
    |   210     |    20    | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT               | CLK_STATE_NOT_READY | 0               |
    |   210     |    21    | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1             | CLK_STATE_NOT_READY | 0               |
    |   210     |    22    | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2             | CLK_STATE_NOT_READY | 0               |
    |   210     |    23    | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3             | CLK_STATE_NOT_READY | 0               |
    |   210     |    28    | DEV_MCASP1_MCASP_ACLKX_POUT                                                       | CLK_STATE_READY     | 0               |
    |   210     |    29    | DEV_MCASP1_MCASP_AFSR_POUT                                                        | CLK_STATE_READY     | 0               |
    |   210     |    30    | DEV_MCASP1_VBUSP_CLK                                                              | CLK_STATE_READY     | 250000000       |
    |   210     |    31    | DEV_MCASP1_MCASP_ACLKR_POUT                                                       | CLK_STATE_READY     | 0               |
    |   210     |    32    | DEV_MCASP1_MCASP_AHCLKX_POUT                                                      | CLK_STATE_READY     | 0               |
    |   210     |    33    | DEV_MCASP1_MCASP_ACLKX_PIN                                                        | CLK_STATE_READY     | 0               |
    |   210     |    34    | DEV_MCASP1_MCASP_AHCLKX_PIN                                                       | CLK_STATE_READY     | 0               |
    |   210     |    35    | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT                         | CLK_STATE_READY     | 0               |
    |   210     |    36    | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT                        | CLK_STATE_READY     | 19200000        |
    |   210     |    37    | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT                  | CLK_STATE_READY     | 0               |
    |   210     |    38    | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT                  | CLK_STATE_READY     | 0               |
    |   210     |    43    | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT               | CLK_STATE_NOT_READY | 0               |
    |   210     |    44    | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1             | CLK_STATE_NOT_READY | 0               |
    |   210     |    45    | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2             | CLK_STATE_NOT_READY | 0               |
    |   210     |    46    | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3             | CLK_STATE_NOT_READY | 0               |
    |   210     |    51    | DEV_MCASP1_MCASP_ACLKR_PIN                                                        | CLK_STATE_READY     | 0               |
    |   211     |     0    | DEV_MCASP2_AUX_CLK                                                                | CLK_STATE_READY     | 196608000       |
    |   211     |     1    | DEV_MCASP2_AUX_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT0_CLK                       | CLK_STATE_READY     | 196608000       |
    |   211     |     2    | DEV_MCASP2_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK                       | CLK_STATE_READY     | 200000000       |
    |   211     |     5    | DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT                        | CLK_STATE_NOT_READY | 0               |
    |   211     |     6    | DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1                      | CLK_STATE_NOT_READY | 0               |
    |   211     |     7    | DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2                      | CLK_STATE_NOT_READY | 0               |
    |   211     |     8    | DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3                      | CLK_STATE_NOT_READY | 0               |
    |   211     |     9    | DEV_MCASP2_MCASP_AFSX_POUT                                                        | CLK_STATE_READY     | 0               |
    |   211     |    10    | DEV_MCASP2_MCASP_AHCLKR_POUT                                                      | CLK_STATE_READY     | 0               |
    |   211     |    11    | DEV_MCASP2_MCASP_AHCLKR_PIN                                                       | CLK_STATE_READY     | 0               |
    |   211     |    12    | DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT                         | CLK_STATE_READY     | 0               |
    |   211     |    13    | DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT                        | CLK_STATE_READY     | 19200000        |
    |   211     |    14    | DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT                  | CLK_STATE_READY     | 0               |
    |   211     |    15    | DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT                  | CLK_STATE_READY     | 0               |
    |   211     |    20    | DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT               | CLK_STATE_NOT_READY | 0               |
    |   211     |    21    | DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1             | CLK_STATE_NOT_READY | 0               |
    |   211     |    22    | DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2             | CLK_STATE_NOT_READY | 0               |
    |   211     |    23    | DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3             | CLK_STATE_NOT_READY | 0               |
    |   211     |    28    | DEV_MCASP2_MCASP_ACLKX_POUT                                                       | CLK_STATE_READY     | 0               |
    |   211     |    29    | DEV_MCASP2_MCASP_AFSR_POUT                                                        | CLK_STATE_READY     | 0               |
    |   211     |    30    | DEV_MCASP2_VBUSP_CLK                                                              | CLK_STATE_READY     | 250000000       |
    |   211     |    31    | DEV_MCASP2_MCASP_ACLKR_POUT                                                       | CLK_STATE_READY     | 0               |
    |   211     |    32    | DEV_MCASP2_MCASP_AHCLKX_POUT                                                      | CLK_STATE_READY     | 0               |
    |   211     |    33    | DEV_MCASP2_MCASP_ACLKX_PIN                                                        | CLK_STATE_READY     | 0               |
    |   211     |    34    | DEV_MCASP2_MCASP_AHCLKX_PIN                                                       | CLK_STATE_READY     | 0               |
    |   211     |    35    | DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT                         | CLK_STATE_READY     | 0               |
    |   211     |    36    | DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT                        | CLK_STATE_READY     | 19200000        |
    |   211     |    37    | DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT                  | CLK_STATE_READY     | 0               |
    |   211     |    38    | DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT                  | CLK_STATE_READY     | 0               |
    |   211     |    43    | DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT               | CLK_STATE_NOT_READY | 0               |
    |   211     |    44    | DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1             | CLK_STATE_NOT_READY | 0               |
    |   211     |    45    | DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2             | CLK_STATE_NOT_READY | 0               |
    |   211     |    46    | DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3             | CLK_STATE_NOT_READY | 0               |
    |   211     |    51    | DEV_MCASP2_MCASP_ACLKR_PIN                                                        | CLK_STATE_READY     | 0               |
    |   212     |     0    | DEV_MCASP3_AUX_CLK                                                                | CLK_STATE_READY     | 196608000       |
    |   212     |     1    | DEV_MCASP3_AUX_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT0_CLK                       | CLK_STATE_READY     | 196608000       |
    |   212     |     2    | DEV_MCASP3_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK                       | CLK_STATE_READY     | 200000000       |
    |   212     |     5    | DEV_MCASP3_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT                        | CLK_STATE_NOT_READY | 0               |
    |   212     |     6    | DEV_MCASP3_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1                      | CLK_STATE_NOT_READY | 0               |
    |   212     |     7    | DEV_MCASP3_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2                      | CLK_STATE_NOT_READY | 0               |
    |   212     |     8    | DEV_MCASP3_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3                      | CLK_STATE_NOT_READY | 0               |
    |   212     |     9    | DEV_MCASP3_MCASP_AFSX_POUT                                                        | CLK_STATE_READY     | 0               |
    |   212     |    10    | DEV_MCASP3_MCASP_AHCLKR_POUT                                                      | CLK_STATE_READY     | 0               |
    |   212     |    11    | DEV_MCASP3_MCASP_AHCLKR_PIN                                                       | CLK_STATE_READY     | 0               |
    |   212     |    12    | DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT                         | CLK_STATE_READY     | 0               |
    |   212     |    13    | DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT                        | CLK_STATE_READY     | 19200000        |
    |   212     |    14    | DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT                  | CLK_STATE_READY     | 0               |
    |   212     |    15    | DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT                  | CLK_STATE_READY     | 0               |
    |   212     |    20    | DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT               | CLK_STATE_NOT_READY | 0               |
    |   212     |    21    | DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1             | CLK_STATE_NOT_READY | 0               |
    |   212     |    22    | DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2             | CLK_STATE_NOT_READY | 0               |
    |   212     |    23    | DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3             | CLK_STATE_NOT_READY | 0               |
    |   212     |    28    | DEV_MCASP3_MCASP_ACLKX_POUT                                                       | CLK_STATE_READY     | 0               |
    |   212     |    29    | DEV_MCASP3_MCASP_AFSR_POUT                                                        | CLK_STATE_READY     | 0               |
    |   212     |    30    | DEV_MCASP3_VBUSP_CLK                                                              | CLK_STATE_READY     | 250000000       |
    |   212     |    31    | DEV_MCASP3_MCASP_ACLKR_POUT                                                       | CLK_STATE_READY     | 0               |
    |   212     |    32    | DEV_MCASP3_MCASP_AHCLKX_POUT                                                      | CLK_STATE_READY     | 0               |
    |   212     |    33    | DEV_MCASP3_MCASP_ACLKX_PIN                                                        | CLK_STATE_READY     | 0               |
    |   212     |    34    | DEV_MCASP3_MCASP_AHCLKX_PIN                                                       | CLK_STATE_READY     | 0               |
    |   212     |    35    | DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT                         | CLK_STATE_READY     | 0               |
    |   212     |    36    | DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT                        | CLK_STATE_READY     | 19200000        |
    |   212     |    37    | DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT                  | CLK_STATE_READY     | 0               |
    |   212     |    38    | DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT                  | CLK_STATE_READY     | 0               |
    |   212     |    43    | DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT               | CLK_STATE_NOT_READY | 0               |
    |   212     |    44    | DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1             | CLK_STATE_NOT_READY | 0               |
    |   212     |    45    | DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2             | CLK_STATE_NOT_READY | 0               |
    |   212     |    46    | DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3             | CLK_STATE_NOT_READY | 0               |
    |   212     |    51    | DEV_MCASP3_MCASP_ACLKR_PIN                                                        | CLK_STATE_READY     | 0               |
    |   213     |     0    | DEV_MCASP4_AUX_CLK                                                                | CLK_STATE_READY     | 196608000       |
    |   213     |     1    | DEV_MCASP4_AUX_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT0_CLK                       | CLK_STATE_READY     | 196608000       |
    |   213     |     2    | DEV_MCASP4_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK                       | CLK_STATE_READY     | 200000000       |
    |   213     |     5    | DEV_MCASP4_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT                        | CLK_STATE_NOT_READY | 0               |
    |   213     |     6    | DEV_MCASP4_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1                      | CLK_STATE_NOT_READY | 0               |
    |   213     |     7    | DEV_MCASP4_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2                      | CLK_STATE_NOT_READY | 0               |
    |   213     |     8    | DEV_MCASP4_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3                      | CLK_STATE_NOT_READY | 0               |
    |   213     |     9    | DEV_MCASP4_MCASP_AFSX_POUT                                                        | CLK_STATE_READY     | 0               |
    |   213     |    10    | DEV_MCASP4_MCASP_AHCLKR_POUT                                                      | CLK_STATE_READY     | 0               |
    |   213     |    11    | DEV_MCASP4_MCASP_AHCLKR_PIN                                                       | CLK_STATE_READY     | 0               |
    |   213     |    12    | DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT                         | CLK_STATE_READY     | 0               |
    |   213     |    13    | DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT                        | CLK_STATE_READY     | 19200000        |
    |   213     |    14    | DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT                  | CLK_STATE_READY     | 0               |
    |   213     |    15    | DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT                  | CLK_STATE_READY     | 0               |
    |   213     |    20    | DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT               | CLK_STATE_NOT_READY | 0               |
    |   213     |    21    | DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1             | CLK_STATE_NOT_READY | 0               |
    |   213     |    22    | DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2             | CLK_STATE_NOT_READY | 0               |
    |   213     |    23    | DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3             | CLK_STATE_NOT_READY | 0               |
    |   213     |    28    | DEV_MCASP4_MCASP_ACLKX_POUT                                                       | CLK_STATE_READY     | 0               |
    |   213     |    29    | DEV_MCASP4_MCASP_AFSR_POUT                                                        | CLK_STATE_READY     | 0               |
    |   213     |    30    | DEV_MCASP4_VBUSP_CLK                                                              | CLK_STATE_READY     | 250000000       |
    |   213     |    31    | DEV_MCASP4_MCASP_ACLKR_POUT                                                       | CLK_STATE_READY     | 0               |
    |   213     |    32    | DEV_MCASP4_MCASP_AHCLKX_POUT                                                      | CLK_STATE_READY     | 0               |
    |   213     |    33    | DEV_MCASP4_MCASP_ACLKX_PIN                                                        | CLK_STATE_READY     | 0               |
    |   213     |    34    | DEV_MCASP4_MCASP_AHCLKX_PIN                                                       | CLK_STATE_READY     | 0               |
    |   213     |    35    | DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT                         | CLK_STATE_READY     | 0               |
    |   213     |    36    | DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT                        | CLK_STATE_READY     | 19200000        |
    |   213     |    37    | DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT                  | CLK_STATE_READY     | 0               |
    |   213     |    38    | DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT                  | CLK_STATE_READY     | 0               |
    |   213     |    43    | DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT               | CLK_STATE_NOT_READY | 0               |
    |   213     |    44    | DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1             | CLK_STATE_NOT_READY | 0               |
    |   213     |    45    | DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2             | CLK_STATE_NOT_READY | 0               |
    |   213     |    46    | DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3             | CLK_STATE_NOT_READY | 0               |
    |   213     |    51    | DEV_MCASP4_MCASP_ACLKR_PIN                                                        | CLK_STATE_READY     | 0               |
    |   339     |     0    | DEV_MCSPI0_IO_CLKSPIO_CLK                                                         | CLK_STATE_READY     | 0               |
    |   339     |     1    | DEV_MCSPI0_VBUSP_CLK                                                              | CLK_STATE_READY     | 125000000       |
    |   339     |     2    | DEV_MCSPI0_CLKSPIREF_CLK                                                          | CLK_STATE_READY     | 50000000        |
    |   339     |     3    | DEV_MCSPI0_IO_CLKSPII_CLK                                                         | CLK_STATE_READY     | 0               |
    |   339     |     4    | DEV_MCSPI0_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI0_CLK_OUT                             | CLK_STATE_READY     | 0               |
    |   339     |     5    | DEV_MCSPI0_IO_CLKSPII_CLK_PARENT_SPI_MAIN_0_IO_CLKSPIO_CLK                        | CLK_STATE_NOT_READY | 0               |
    |   340     |     0    | DEV_MCSPI1_IO_CLKSPIO_CLK                                                         | CLK_STATE_READY     | 0               |
    |   340     |     1    | DEV_MCSPI1_VBUSP_CLK                                                              | CLK_STATE_READY     | 125000000       |
    |   340     |     2    | DEV_MCSPI1_CLKSPIREF_CLK                                                          | CLK_STATE_READY     | 50000000        |
    |   340     |     3    | DEV_MCSPI1_IO_CLKSPII_CLK                                                         | CLK_STATE_READY     | 0               |
    |   340     |     4    | DEV_MCSPI1_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI1_CLK_OUT                             | CLK_STATE_READY     | 0               |
    |   340     |     5    | DEV_MCSPI1_IO_CLKSPII_CLK_PARENT_SPI_MAIN_1_IO_CLKSPIO_CLK                        | CLK_STATE_NOT_READY | 0               |
    |   341     |     0    | DEV_MCSPI2_IO_CLKSPIO_CLK                                                         | CLK_STATE_READY     | 0               |
    |   341     |     1    | DEV_MCSPI2_VBUSP_CLK                                                              | CLK_STATE_READY     | 125000000       |
    |   341     |     2    | DEV_MCSPI2_CLKSPIREF_CLK                                                          | CLK_STATE_READY     | 50000000        |
    |   341     |     3    | DEV_MCSPI2_IO_CLKSPII_CLK                                                         | CLK_STATE_READY     | 0               |
    |   341     |     4    | DEV_MCSPI2_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI2_CLK_OUT                             | CLK_STATE_READY     | 0               |
    |   341     |     5    | DEV_MCSPI2_IO_CLKSPII_CLK_PARENT_SPI_MAIN_2_IO_CLKSPIO_CLK                        | CLK_STATE_NOT_READY | 0               |
    |   342     |     0    | DEV_MCSPI3_IO_CLKSPIO_CLK                                                         | CLK_STATE_READY     | 0               |
    |   342     |     1    | DEV_MCSPI3_VBUSP_CLK                                                              | CLK_STATE_READY     | 125000000       |
    |   342     |     2    | DEV_MCSPI3_CLKSPIREF_CLK                                                          | CLK_STATE_READY     | 50000000        |
    |   342     |     3    | DEV_MCSPI3_IO_CLKSPII_CLK                                                         | CLK_STATE_NOT_READY | 0               |
    |   342     |     4    | DEV_MCSPI3_IO_CLKSPII_CLK_PARENT_SPI_MAIN_3_IO_CLKSPIO_CLK                        | CLK_STATE_NOT_READY | 0               |
    |   342     |     5    | DEV_MCSPI3_IO_CLKSPII_CLK_PARENT_SPI3_CLK_LPBK_MUX_OUT0                           | CLK_STATE_READY     | 0               |
    |   343     |     0    | DEV_MCSPI4_IO_CLKSPIO_CLK                                                         | CLK_STATE_READY     | 0               |
    |   343     |     1    | DEV_MCSPI4_VBUSP_CLK                                                              | CLK_STATE_READY     | 125000000       |
    |   343     |     2    | DEV_MCSPI4_CLKSPIREF_CLK                                                          | CLK_STATE_READY     | 50000000        |
    |   343     |     3    | DEV_MCSPI4_IO_CLKSPII_CLK                                                         | CLK_STATE_NOT_READY | 0               |
    |   344     |     0    | DEV_MCSPI5_IO_CLKSPIO_CLK                                                         | CLK_STATE_READY     | 0               |
    |   344     |     1    | DEV_MCSPI5_VBUSP_CLK                                                              | CLK_STATE_READY     | 125000000       |
    |   344     |     2    | DEV_MCSPI5_CLKSPIREF_CLK                                                          | CLK_STATE_READY     | 50000000        |
    |   344     |     3    | DEV_MCSPI5_IO_CLKSPII_CLK                                                         | CLK_STATE_READY     | 0               |
    |   344     |     4    | DEV_MCSPI5_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI5_CLK_OUT                             | CLK_STATE_READY     | 0               |
    |   344     |     5    | DEV_MCSPI5_IO_CLKSPII_CLK_PARENT_SPI_MAIN_5_IO_CLKSPIO_CLK                        | CLK_STATE_NOT_READY | 0               |
    |   345     |     0    | DEV_MCSPI6_IO_CLKSPIO_CLK                                                         | CLK_STATE_READY     | 0               |
    |   345     |     1    | DEV_MCSPI6_VBUSP_CLK                                                              | CLK_STATE_READY     | 125000000       |
    |   345     |     2    | DEV_MCSPI6_CLKSPIREF_CLK                                                          | CLK_STATE_READY     | 50000000        |
    |   345     |     3    | DEV_MCSPI6_IO_CLKSPII_CLK                                                         | CLK_STATE_READY     | 0               |
    |   345     |     4    | DEV_MCSPI6_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI6_CLK_OUT                             | CLK_STATE_READY     | 0               |
    |   345     |     5    | DEV_MCSPI6_IO_CLKSPII_CLK_PARENT_SPI_MAIN_6_IO_CLKSPIO_CLK                        | CLK_STATE_NOT_READY | 0               |
    |   346     |     0    | DEV_MCSPI7_IO_CLKSPIO_CLK                                                         | CLK_STATE_READY     | 0               |
    |   346     |     1    | DEV_MCSPI7_VBUSP_CLK                                                              | CLK_STATE_READY     | 125000000       |
    |   346     |     2    | DEV_MCSPI7_CLKSPIREF_CLK                                                          | CLK_STATE_READY     | 50000000        |
    |   346     |     3    | DEV_MCSPI7_IO_CLKSPII_CLK                                                         | CLK_STATE_READY     | 0               |
    |   346     |     4    | DEV_MCSPI7_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI7_CLK_OUT                             | CLK_STATE_READY     | 0               |
    |   346     |     5    | DEV_MCSPI7_IO_CLKSPII_CLK_PARENT_SPI_MAIN_7_IO_CLKSPIO_CLK                        | CLK_STATE_NOT_READY | 0               |
    |     0     |     0    | DEV_MCU_ADC12FC_16FFC0_ADC_CLK                                                    | CLK_STATE_READY     | 19200000        |
    |     0     |     1    | DEV_MCU_ADC12FC_16FFC0_ADC_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                     | CLK_STATE_READY     | 19200000        |
    |     0     |     2    | DEV_MCU_ADC12FC_16FFC0_ADC_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT1_CLK            | CLK_STATE_READY     | 60000000        |
    |     0     |     3    | DEV_MCU_ADC12FC_16FFC0_ADC_CLK_PARENT_HSDIV1_16FFT_MCU_0_HSDIVOUT1_CLK            | CLK_STATE_READY     | 58823529        |
    |     0     |     4    | DEV_MCU_ADC12FC_16FFC0_ADC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                 | CLK_STATE_READY     | 0               |
    |     0     |     5    | DEV_MCU_ADC12FC_16FFC0_VBUS_CLK                                                   | CLK_STATE_READY     | 333333333       |
    |     0     |     6    | DEV_MCU_ADC12FC_16FFC0_SYS_CLK                                                    | CLK_STATE_READY     | 500000000       |
    |     1     |     0    | DEV_MCU_ADC12FC_16FFC1_ADC_CLK                                                    | CLK_STATE_READY     | 19200000        |
    |     1     |     1    | DEV_MCU_ADC12FC_16FFC1_ADC_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                     | CLK_STATE_READY     | 19200000        |
    |     1     |     2    | DEV_MCU_ADC12FC_16FFC1_ADC_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT1_CLK            | CLK_STATE_READY     | 60000000        |
    |     1     |     3    | DEV_MCU_ADC12FC_16FFC1_ADC_CLK_PARENT_HSDIV1_16FFT_MCU_0_HSDIVOUT1_CLK            | CLK_STATE_READY     | 58823529        |
    |     1     |     4    | DEV_MCU_ADC12FC_16FFC1_ADC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                 | CLK_STATE_READY     | 0               |
    |     1     |     5    | DEV_MCU_ADC12FC_16FFC1_VBUS_CLK                                                   | CLK_STATE_READY     | 333333333       |
    |     1     |     6    | DEV_MCU_ADC12FC_16FFC1_SYS_CLK                                                    | CLK_STATE_READY     | 500000000       |
    |    29     |     0    | DEV_MCU_CPSW0_MDIO_MDCLK_O                                                        | CLK_STATE_READY     | 0               |
    |    29     |     1    | DEV_MCU_CPSW0_CPTS_GENF0                                                          | CLK_STATE_READY     | 0               |
    |    29     |     3    | DEV_MCU_CPSW0_CPTS_RFT_CLK                                                        | CLK_STATE_READY     | 500000000       |
    |    29     |     4    | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK               | CLK_STATE_READY     | 250000000       |
    |    29     |     5    | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK             | CLK_STATE_READY     | 200000000       |
    |    29     |     6    | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT                   | CLK_STATE_READY     | 0               |
    |    29     |     7    | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT                       | CLK_STATE_READY     | 0               |
    |    29     |     8    | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                     | CLK_STATE_READY     | 0               |
    |    29     |     9    | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT                         | CLK_STATE_READY     | 0               |
    |    29     |    10    | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN0_TXMCLK              | CLK_STATE_READY     | 0               |
    |    29     |    11    | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN1_TXMCLK              | CLK_STATE_READY     | 0               |
    |    29     |    12    | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN2_TXMCLK              | CLK_STATE_READY     | 0               |
    |    29     |    13    | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN3_TXMCLK              | CLK_STATE_READY     | 0               |
    |    29     |    18    | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK                | CLK_STATE_READY     | 500000000       |
    |    29     |    19    | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK2      | CLK_STATE_READY     | 500000000       |
    |    29     |    20    | DEV_MCU_CPSW0_GMII1_MR_CLK                                                        | CLK_STATE_READY     | 25000000        |
    |    29     |    21    | DEV_MCU_CPSW0_GMII_RFT_CLK                                                        | CLK_STATE_READY     | 125000000       |
    |    29     |    22    | DEV_MCU_CPSW0_RGMII1_RXC_I                                                        | CLK_STATE_READY     | 0               |
    |    29     |    26    | DEV_MCU_CPSW0_RMII_MHZ_50_CLK                                                     | CLK_STATE_READY     | 0               |
    |    29     |    27    | DEV_MCU_CPSW0_RGMII1_TXC_O                                                        | CLK_STATE_READY     | 0               |
    |    29     |    28    | DEV_MCU_CPSW0_CPPI_CLK_CLK                                                        | CLK_STATE_READY     | 333333333       |
    |    29     |    29    | DEV_MCU_CPSW0_RGMII_MHZ_5_CLK                                                     | CLK_STATE_READY     | 5000000         |
    |    29     |    30    | DEV_MCU_CPSW0_GMII1_MT_CLK                                                        | CLK_STATE_READY     | 25000000        |
    |    29     |    32    | DEV_MCU_CPSW0_RGMII_MHZ_50_CLK                                                    | CLK_STATE_READY     | 50000000        |
    |    29     |    33    | DEV_MCU_CPSW0_RGMII_MHZ_250_CLK                                                   | CLK_STATE_READY     | 250000000       |
    |    37     |     0    | DEV_MCU_CPT2_AGGR0_VCLK_CLK                                                       | CLK_STATE_READY     | 333333333       |
    |    53     |     0    | DEV_MCU_DCC0_DCC_CLKSRC0_CLK                                                      | CLK_STATE_READY     | 200000000       |
    |    53     |     1    | DEV_MCU_DCC0_DCC_CLKSRC1_CLK                                                      | CLK_STATE_READY     | 60000000        |
    |    53     |     2    | DEV_MCU_DCC0_DCC_CLKSRC2_CLK                                                      | CLK_STATE_READY     | 80000000        |
    |    53     |     3    | DEV_MCU_DCC0_DCC_CLKSRC3_CLK                                                      | CLK_STATE_READY     | 96000000        |
    |    53     |     4    | DEV_MCU_DCC0_DCC_CLKSRC4_CLK                                                      | CLK_STATE_READY     | 133333333       |
    |    53     |     5    | DEV_MCU_DCC0_DCC_CLKSRC5_CLK                                                      | CLK_STATE_READY     | 32000           |
    |    53     |     6    | DEV_MCU_DCC0_DCC_CLKSRC6_CLK                                                      | CLK_STATE_READY     | 32768           |
    |    53     |     7    | DEV_MCU_DCC0_DCC_CLKSRC7_CLK                                                      | CLK_STATE_READY     | 0               |
    |    53     |     8    | DEV_MCU_DCC0_DCC_INPUT00_CLK                                                      | CLK_STATE_READY     | 19200000        |
    |    53     |     9    | DEV_MCU_DCC0_DCC_INPUT01_CLK                                                      | CLK_STATE_READY     | 32000           |
    |    53     |    10    | DEV_MCU_DCC0_DCC_INPUT02_CLK                                                      | CLK_STATE_READY     | 12500000        |
    |    53     |    11    | DEV_MCU_DCC0_DCC_INPUT10_CLK                                                      | CLK_STATE_READY     | 333333333       |
    |    53     |    12    | DEV_MCU_DCC0_VBUS_CLK                                                             | CLK_STATE_READY     | 166666666       |
    |    54     |     0    | DEV_MCU_DCC1_DCC_CLKSRC0_CLK                                                      | CLK_STATE_READY     | 250000000       |
    |    54     |     1    | DEV_MCU_DCC1_DCC_CLKSRC1_CLK                                                      | CLK_STATE_READY     | 200000000       |
    |    54     |     2    | DEV_MCU_DCC1_DCC_CLKSRC2_CLK                                                      | CLK_STATE_READY     | 80000000        |
    |    54     |     3    | DEV_MCU_DCC1_DCC_CLKSRC3_CLK                                                      | CLK_STATE_READY     | 166666666       |
    |    54     |     4    | DEV_MCU_DCC1_DCC_CLKSRC4_CLK                                                      | CLK_STATE_READY     | 250000000       |
    |    54     |     5    | DEV_MCU_DCC1_DCC_CLKSRC5_CLK                                                      | CLK_STATE_READY     | 58823529        |
    |    54     |     6    | DEV_MCU_DCC1_DCC_CLKSRC6_CLK                                                      | CLK_STATE_READY     | 0               |
    |    54     |     7    | DEV_MCU_DCC1_DCC_CLKSRC7_CLK                                                      | CLK_STATE_READY     | 500000000       |
    |    54     |     8    | DEV_MCU_DCC1_DCC_INPUT00_CLK                                                      | CLK_STATE_READY     | 19200000        |
    |    54     |     9    | DEV_MCU_DCC1_DCC_INPUT01_CLK                                                      | CLK_STATE_READY     | 32768           |
    |    54     |    10    | DEV_MCU_DCC1_DCC_INPUT02_CLK                                                      | CLK_STATE_READY     | 12500000        |
    |    54     |    11    | DEV_MCU_DCC1_DCC_INPUT10_CLK                                                      | CLK_STATE_READY     | 250000000       |
    |    54     |    12    | DEV_MCU_DCC1_VBUS_CLK                                                             | CLK_STATE_READY     | 166666666       |
    |    55     |     0    | DEV_MCU_DCC2_DCC_CLKSRC0_CLK                                                      | CLK_STATE_READY     | 0               |
    |    55     |     1    | DEV_MCU_DCC2_DCC_CLKSRC1_CLK                                                      | CLK_STATE_READY     | 0               |
    |    55     |     2    | DEV_MCU_DCC2_DCC_CLKSRC2_CLK                                                      | CLK_STATE_READY     | 0               |
    |    55     |     3    | DEV_MCU_DCC2_DCC_CLKSRC3_CLK                                                      | CLK_STATE_READY     | 192000000       |
    |    55     |     4    | DEV_MCU_DCC2_DCC_CLKSRC4_CLK                                                      | CLK_STATE_READY     | 0               |
    |    55     |     6    | DEV_MCU_DCC2_DCC_CLKSRC6_CLK                                                      | CLK_STATE_READY     | 12500000        |
    |    55     |     7    | DEV_MCU_DCC2_DCC_CLKSRC7_CLK                                                      | CLK_STATE_READY     | 19200000        |
    |    55     |     8    | DEV_MCU_DCC2_DCC_INPUT00_CLK                                                      | CLK_STATE_READY     | 19200000        |
    |    55     |     9    | DEV_MCU_DCC2_DCC_INPUT01_CLK                                                      | CLK_STATE_READY     | 0               |
    |    55     |    10    | DEV_MCU_DCC2_DCC_INPUT02_CLK                                                      | CLK_STATE_READY     | 12500000        |
    |    55     |    11    | DEV_MCU_DCC2_DCC_INPUT10_CLK                                                      | CLK_STATE_READY     | 333333333       |
    |    55     |    12    | DEV_MCU_DCC2_VBUS_CLK                                                             | CLK_STATE_READY     | 166666666       |
    |   105     |     0    | DEV_MCU_ESM0_CLK                                                                  | CLK_STATE_READY     | 166666666       |
    |   107     |     0    | DEV_MCU_FSS0_FSAS_0_GCLK                                                          | CLK_STATE_READY     | 1000000000      |
    |   108     |     1    | DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_CLKX2_INV_CLK                                      | CLK_STATE_READY     | 166666666       |
    |   108     |     2    | DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_CLKX1_INV_CLK                                      | CLK_STATE_READY     | 83333333        |
    |   108     |     3    | DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_CLKX1_CLK                                          | CLK_STATE_READY     | 83333333        |
    |   108     |     6    | DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_CLKX2_CLK                                          | CLK_STATE_READY     | 166666666       |
    |   108     |     7    | DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_OUT_CLK_N                                          | CLK_STATE_READY     | 0               |
    |   108     |     8    | DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_OUT_CLK_P                                          | CLK_STATE_READY     | 0               |
    |   108     |    11    | DEV_MCU_FSS0_HYPERBUS1P0_0_CBA_CLK                                                | CLK_STATE_READY     | 1000000000      |
    |   109     |     0    | DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK                                                 | CLK_STATE_READY     | 0               |
    |   109     |     1    | DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK_PARENT_BOARD_0_MCU_OSPI0_DQS_OUT                | CLK_STATE_READY     | 0               |
    |   109     |     2    | DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK_PARENT_FSS_MCU_0_OSPI_0_OSPI_OCLK_CLK           | CLK_STATE_READY     | 0               |
    |   109     |     3    | DEV_MCU_FSS0_OSPI_0_OSPI_HCLK_CLK                                                 | CLK_STATE_READY     | 1000000000      |
    |   109     |     4    | DEV_MCU_FSS0_OSPI_0_OSPI_OCLK_CLK                                                 | CLK_STATE_READY     | 0               |
    |   109     |     5    | DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK                                                 | CLK_STATE_READY     | 133333333       |
    |   109     |     6    | DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT4_CLK         | CLK_STATE_READY     | 133333333       |
    |   109     |     7    | DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT4_CLK         | CLK_STATE_READY     | 166666666       |
    |   109     |     8    | DEV_MCU_FSS0_OSPI_0_OSPI_DQS_CLK                                                  | CLK_STATE_READY     | 0               |
    |   109     |     9    | DEV_MCU_FSS0_OSPI_0_OSPI_PCLK_CLK                                                 | CLK_STATE_READY     | 1000000000      |
    |   110     |     0    | DEV_MCU_FSS0_OSPI_1_OSPI_ICLK_CLK                                                 | CLK_STATE_READY     | 0               |
    |   110     |     1    | DEV_MCU_FSS0_OSPI_1_OSPI_ICLK_CLK_PARENT_BOARD_0_MCU_OSPI1_DQS_OUT                | CLK_STATE_READY     | 0               |
    |   110     |     2    | DEV_MCU_FSS0_OSPI_1_OSPI_ICLK_CLK_PARENT_FSS_MCU_0_OSPI_1_OSPI_OCLK_CLK           | CLK_STATE_READY     | 0               |
    |   110     |     3    | DEV_MCU_FSS0_OSPI_1_OSPI_HCLK_CLK                                                 | CLK_STATE_READY     | 1000000000      |
    |   110     |     4    | DEV_MCU_FSS0_OSPI_1_OSPI_OCLK_CLK                                                 | CLK_STATE_READY     | 0               |
    |   110     |     5    | DEV_MCU_FSS0_OSPI_1_OSPI_RCLK_CLK                                                 | CLK_STATE_READY     | 133333333       |
    |   110     |     6    | DEV_MCU_FSS0_OSPI_1_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT4_CLK         | CLK_STATE_READY     | 133333333       |
    |   110     |     7    | DEV_MCU_FSS0_OSPI_1_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT4_CLK         | CLK_STATE_READY     | 166666666       |
    |   110     |     8    | DEV_MCU_FSS0_OSPI_1_OSPI_DQS_CLK                                                  | CLK_STATE_READY     | 0               |
    |   110     |     9    | DEV_MCU_FSS0_OSPI_1_OSPI_PCLK_CLK                                                 | CLK_STATE_READY     | 1000000000      |
    |   221     |     0    | DEV_MCU_I2C0_PORSCL                                                               | CLK_STATE_READY     | 0               |
    |   221     |     1    | DEV_MCU_I2C0_PISYS_CLK                                                            | CLK_STATE_READY     | 96000000        |
    |   221     |     2    | DEV_MCU_I2C0_CLK                                                                  | CLK_STATE_READY     | 166666666       |
    |   221     |     3    | DEV_MCU_I2C0_PISCL                                                                | CLK_STATE_READY     | 0               |
    |   222     |     0    | DEV_MCU_I2C1_PORSCL                                                               | CLK_STATE_READY     | 0               |
    |   222     |     1    | DEV_MCU_I2C1_PISYS_CLK                                                            | CLK_STATE_READY     | 96000000        |
    |   222     |     2    | DEV_MCU_I2C1_CLK                                                                  | CLK_STATE_READY     | 166666666       |
    |   222     |     3    | DEV_MCU_I2C1_PISCL                                                                | CLK_STATE_READY     | 0               |
    |   118     |     0    | DEV_MCU_I3C0_I3C_SCL_DI                                                           | CLK_STATE_READY     | 0               |
    |   118     |     1    | DEV_MCU_I3C0_I3C_SCL_DO                                                           | CLK_STATE_READY     | 0               |
    |   118     |     2    | DEV_MCU_I3C0_I3C_SCLK_CLK                                                         | CLK_STATE_READY     | 166666666       |
    |   118     |     3    | DEV_MCU_I3C0_I3C_PCLK_CLK                                                         | CLK_STATE_READY     | 166666666       |
    |   118     |     4    | DEV_MCU_I3C0_I3C_SDA_DI                                                           | CLK_STATE_READY     | 0               |
    |   119     |     2    | DEV_MCU_I3C1_I3C_SCLK_CLK                                                         | CLK_STATE_READY     | 166666666       |
    |   119     |     3    | DEV_MCU_I3C1_I3C_PCLK_CLK                                                         | CLK_STATE_READY     | 166666666       |
    |   207     |     0    | DEV_MCU_MCAN0_MCANSS_HCLK_CLK                                                     | CLK_STATE_READY     | 166666666       |
    |   207     |     1    | DEV_MCU_MCAN0_MCANSS_CCLK_CLK                                                     | CLK_STATE_READY     | 80000000        |
    |   207     |     2    | DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT3_CLK             | CLK_STATE_READY     | 80000000        |
    |   207     |     3    | DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                  | CLK_STATE_READY     | 0               |
    |   207     |     4    | DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT2_CLK             | CLK_STATE_READY     | 80000000        |
    |   207     |     5    | DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                      | CLK_STATE_READY     | 19200000        |
    |   207     |     6    | DEV_MCU_MCAN0_MCANSS_CAN_RXD                                                      | CLK_STATE_READY     | 0               |
    |   208     |     0    | DEV_MCU_MCAN1_MCANSS_HCLK_CLK                                                     | CLK_STATE_READY     | 166666666       |
    |   208     |     1    | DEV_MCU_MCAN1_MCANSS_CCLK_CLK                                                     | CLK_STATE_READY     | 80000000        |
    |   208     |     2    | DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT3_CLK             | CLK_STATE_READY     | 80000000        |
    |   208     |     3    | DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                  | CLK_STATE_READY     | 0               |
    |   208     |     4    | DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT2_CLK             | CLK_STATE_READY     | 80000000        |
    |   208     |     5    | DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                      | CLK_STATE_READY     | 19200000        |
    |   208     |     6    | DEV_MCU_MCAN1_MCANSS_CAN_RXD                                                      | CLK_STATE_READY     | 0               |
    |   347     |     0    | DEV_MCU_MCSPI0_IO_CLKSPIO_CLK                                                     | CLK_STATE_READY     | 0               |
    |   347     |     1    | DEV_MCU_MCSPI0_VBUSP_CLK                                                          | CLK_STATE_READY     | 166666666       |
    |   347     |     2    | DEV_MCU_MCSPI0_CLKSPIREF_CLK                                                      | CLK_STATE_READY     | 50000000        |
    |   347     |     3    | DEV_MCU_MCSPI0_IO_CLKSPII_CLK                                                     | CLK_STATE_READY     | 0               |
    |   347     |     4    | DEV_MCU_MCSPI0_IO_CLKSPII_CLK_PARENT_BOARD_0_MCU_SPI0_CLK_OUT                     | CLK_STATE_READY     | 0               |
    |   347     |     5    | DEV_MCU_MCSPI0_IO_CLKSPII_CLK_PARENT_SPI_MCU_0_IO_CLKSPIO_CLK                     | CLK_STATE_READY     | 0               |
    |   348     |     0    | DEV_MCU_MCSPI1_IO_CLKSPIO_CLK                                                     | CLK_STATE_READY     | 0               |
    |   348     |     1    | DEV_MCU_MCSPI1_VBUSP_CLK                                                          | CLK_STATE_READY     | 166666666       |
    |   348     |     2    | DEV_MCU_MCSPI1_CLKSPIREF_CLK                                                      | CLK_STATE_READY     | 50000000        |
    |   348     |     3    | DEV_MCU_MCSPI1_IO_CLKSPII_CLK                                                     | CLK_STATE_NOT_READY | 0               |
    |   348     |     4    | DEV_MCU_MCSPI1_IO_CLKSPII_CLK_PARENT_SPI_MAIN_3_IO_CLKSPIO_CLK                    | CLK_STATE_NOT_READY | 0               |
    |   348     |     5    | DEV_MCU_MCSPI1_IO_CLKSPII_CLK_PARENT_MCU_SPI1_CLK_LPBK_MUX_OUT0                   | CLK_STATE_READY     | 0               |
    |   349     |     0    | DEV_MCU_MCSPI2_IO_CLKSPIO_CLK                                                     | CLK_STATE_READY     | 0               |
    |   349     |     1    | DEV_MCU_MCSPI2_VBUSP_CLK                                                          | CLK_STATE_READY     | 166666666       |
    |   349     |     2    | DEV_MCU_MCSPI2_CLKSPIREF_CLK                                                      | CLK_STATE_READY     | 50000000        |
    |   349     |     3    | DEV_MCU_MCSPI2_IO_CLKSPII_CLK                                                     | CLK_STATE_READY     | 0               |
    |   268     |     0    | DEV_MCU_NAVSS0_INTR_ROUTER_0_INTR_CLK                                             | CLK_STATE_READY     | 1000000000      |
    |   269     |     0    | DEV_MCU_NAVSS0_MCRC_0_CLK                                                         | CLK_STATE_READY     | 1000000000      |
    |   270     |     0    | DEV_MCU_NAVSS0_MODSS_VD2CLK                                                       | CLK_STATE_READY     | 1000000000      |
    |   271     |     0    | DEV_MCU_NAVSS0_PROXY0_CLK_CLK                                                     | CLK_STATE_READY     | 1000000000      |
    |   272     |     0    | DEV_MCU_NAVSS0_RINGACC0_SYS_CLK                                                   | CLK_STATE_READY     | 1000000000      |
    |   273     |     0    | DEV_MCU_NAVSS0_UDMAP_0_SYS_CLK                                                    | CLK_STATE_READY     | 1000000000      |
    |   274     |     0    | DEV_MCU_NAVSS0_UDMASS_VD2CLK                                                      | CLK_STATE_READY     | 1000000000      |
    |   275     |     0    | DEV_MCU_NAVSS0_UDMASS_INTA_0_SYS_CLK                                              | CLK_STATE_READY     | 1000000000      |
    |   176     |     0    | DEV_MCU_PBIST0_CLK6_CLK                                                           | CLK_STATE_READY     | 83333333        |
    |   176     |     1    | DEV_MCU_PBIST0_CLK8_CLK                                                           | CLK_STATE_READY     | 83333333        |
    |   176     |     3    | DEV_MCU_PBIST0_CLK3_CLK                                                           | CLK_STATE_READY     | 166666666       |
    |   176     |     4    | DEV_MCU_PBIST0_CLK7_CLK                                                           | CLK_STATE_READY     | 83333333        |
    |   176     |     6    | DEV_MCU_PBIST0_CLK4_CLK                                                           | CLK_STATE_READY     | 83333333        |
    |   176     |     7    | DEV_MCU_PBIST0_CLK5_CLK                                                           | CLK_STATE_READY     | 83333333        |
    |   176     |     8    | DEV_MCU_PBIST0_CLK1_CLK                                                           | CLK_STATE_READY     | 500000000       |
    |   176     |     9    | DEV_MCU_PBIST0_CLK2_CLK                                                           | CLK_STATE_READY     | 333333333       |
    |   177     |     0    | DEV_MCU_PBIST1_CLK6_CLK                                                           | CLK_STATE_READY     | 83333333        |
    |   177     |     1    | DEV_MCU_PBIST1_CLK8_CLK                                                           | CLK_STATE_READY     | 83333333        |
    |   177     |     3    | DEV_MCU_PBIST1_CLK3_CLK                                                           | CLK_STATE_READY     | 333333333       |
    |   177     |     4    | DEV_MCU_PBIST1_CLK7_CLK                                                           | CLK_STATE_READY     | 83333333        |
    |   177     |     6    | DEV_MCU_PBIST1_CLK4_CLK                                                           | CLK_STATE_READY     | 83333333        |
    |   177     |     7    | DEV_MCU_PBIST1_CLK5_CLK                                                           | CLK_STATE_READY     | 166666666       |
    |   177     |     8    | DEV_MCU_PBIST1_CLK1_CLK                                                           | CLK_STATE_READY     | 500000000       |
    |   177     |     9    | DEV_MCU_PBIST1_CLK2_CLK                                                           | CLK_STATE_READY     | 400000000       |
    |   178     |     1    | DEV_MCU_PBIST2_CLK8_CLK                                                           | CLK_STATE_READY     | 83333333        |
    |   284     |     0    | DEV_MCU_R5FSS0_CORE0_CPU_CLK                                                      | CLK_STATE_READY     | 1000000000      |
    |   284     |     1    | DEV_MCU_R5FSS0_CORE0_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK     | CLK_STATE_READY     | 1000000000      |
    |   284     |     2    | DEV_MCU_R5FSS0_CORE0_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK3    | CLK_STATE_READY     | 333333333       |
    |   284     |     3    | DEV_MCU_R5FSS0_CORE0_INTERFACE_CLK                                                | CLK_STATE_READY     | 1000000000      |
    |   284     |     4    | DEV_MCU_R5FSS0_CORE0_INTERFACE_PHASE                                              | CLK_STATE_READY     | 333333333       |
    |   285     |     0    | DEV_MCU_R5FSS0_CORE1_CPU_CLK                                                      | CLK_STATE_READY     | 1000000000      |
    |   285     |     1    | DEV_MCU_R5FSS0_CORE1_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK     | CLK_STATE_READY     | 1000000000      |
    |   285     |     2    | DEV_MCU_R5FSS0_CORE1_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK3    | CLK_STATE_READY     | 333333333       |
    |   285     |     3    | DEV_MCU_R5FSS0_CORE1_INTERFACE_CLK                                                | CLK_STATE_READY     | 1000000000      |
    |   285     |     4    | DEV_MCU_R5FSS0_CORE1_INTERFACE_PHASE                                              | CLK_STATE_READY     | 333333333       |
    |   295     |     0    | DEV_MCU_RTI0_VBUSP_CLK                                                            | CLK_STATE_READY     | 166666666       |
    |   295     |     1    | DEV_MCU_RTI0_RTI_CLK                                                              | CLK_STATE_READY     | 19200000        |
    |   295     |     2    | DEV_MCU_RTI0_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                               | CLK_STATE_READY     | 19200000        |
    |   295     |     3    | DEV_MCU_RTI0_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                               | CLK_STATE_READY     | 32768           |
    |   295     |     4    | DEV_MCU_RTI0_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK          | CLK_STATE_READY     | 12500000        |
    |   295     |     5    | DEV_MCU_RTI0_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK            | CLK_STATE_READY     | 32000           |
    |   296     |     0    | DEV_MCU_RTI1_VBUSP_CLK                                                            | CLK_STATE_READY     | 166666666       |
    |   296     |     1    | DEV_MCU_RTI1_RTI_CLK                                                              | CLK_STATE_READY     | 19200000        |
    |   296     |     2    | DEV_MCU_RTI1_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                               | CLK_STATE_READY     | 19200000        |
    |   296     |     3    | DEV_MCU_RTI1_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                               | CLK_STATE_READY     | 32768           |
    |   296     |     4    | DEV_MCU_RTI1_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK          | CLK_STATE_READY     | 12500000        |
    |   296     |     5    | DEV_MCU_RTI1_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK            | CLK_STATE_READY     | 32000           |
    |    35     |     0    | DEV_MCU_TIMER0_TIMER_PWM                                                          | CLK_STATE_READY     | 0               |
    |    35     |     1    | DEV_MCU_TIMER0_TIMER_TCLK_CLK                                                     | CLK_STATE_READY     | 62500000        |
    |    35     |     2    | DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                      | CLK_STATE_READY     | 19200000        |
    |    35     |     3    | DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK16  | CLK_STATE_READY     | 62500000        |
    |    35     |     4    | DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY     | 12500000        |
    |    35     |     5    | DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK             | CLK_STATE_READY     | 200000000       |
    |    35     |     6    | DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                  | CLK_STATE_READY     | 0               |
    |    35     |     7    | DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                      | CLK_STATE_READY     | 32768           |
    |    35     |     8    | DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0                  | CLK_STATE_READY     | 0               |
    |    35     |     9    | DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK   | CLK_STATE_READY     | 32000           |
    |    35     |    10    | DEV_MCU_TIMER0_TIMER_HCLK_CLK                                                     | CLK_STATE_READY     | 166666666       |
    |    83     |     1    | DEV_MCU_TIMER1_TIMER_TCLK_CLK                                                     | CLK_STATE_READY     | 19200000        |
    |    83     |     2    | DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT1                        | CLK_STATE_READY     | 19200000        |
    |    83     |     3    | DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_0_TIMER_PWM               | CLK_STATE_READY     | 0               |
    |    83     |    10    | DEV_MCU_TIMER1_TIMER_HCLK_CLK                                                     | CLK_STATE_READY     | 166666666       |
    |    84     |     0    | DEV_MCU_TIMER2_TIMER_PWM                                                          | CLK_STATE_READY     | 0               |
    |    84     |     1    | DEV_MCU_TIMER2_TIMER_TCLK_CLK                                                     | CLK_STATE_READY     | 19200000        |
    |    84     |     2    | DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                      | CLK_STATE_READY     | 19200000        |
    |    84     |     3    | DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK16  | CLK_STATE_READY     | 62500000        |
    |    84     |     4    | DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY     | 12500000        |
    |    84     |     5    | DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK             | CLK_STATE_READY     | 200000000       |
    |    84     |     6    | DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                  | CLK_STATE_READY     | 0               |
    |    84     |     7    | DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                      | CLK_STATE_READY     | 32768           |
    |    84     |     8    | DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0                  | CLK_STATE_READY     | 0               |
    |    84     |     9    | DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK   | CLK_STATE_READY     | 32000           |
    |    84     |    10    | DEV_MCU_TIMER2_TIMER_HCLK_CLK                                                     | CLK_STATE_READY     | 166666666       |
    |    85     |     1    | DEV_MCU_TIMER3_TIMER_TCLK_CLK                                                     | CLK_STATE_READY     | 19200000        |
    |    85     |     2    | DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT3                        | CLK_STATE_READY     | 19200000        |
    |    85     |     3    | DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_2_TIMER_PWM               | CLK_STATE_READY     | 0               |
    |    85     |    10    | DEV_MCU_TIMER3_TIMER_HCLK_CLK                                                     | CLK_STATE_READY     | 166666666       |
    |    86     |     0    | DEV_MCU_TIMER4_TIMER_PWM                                                          | CLK_STATE_READY     | 0               |
    |    86     |     1    | DEV_MCU_TIMER4_TIMER_TCLK_CLK                                                     | CLK_STATE_READY     | 19200000        |
    |    86     |     2    | DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                      | CLK_STATE_READY     | 19200000        |
    |    86     |     3    | DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK16  | CLK_STATE_READY     | 62500000        |
    |    86     |     4    | DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY     | 12500000        |
    |    86     |     5    | DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK             | CLK_STATE_READY     | 200000000       |
    |    86     |     6    | DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                  | CLK_STATE_READY     | 0               |
    |    86     |     7    | DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                      | CLK_STATE_READY     | 32768           |
    |    86     |     8    | DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0                  | CLK_STATE_READY     | 0               |
    |    86     |     9    | DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK   | CLK_STATE_READY     | 32000           |
    |    86     |    10    | DEV_MCU_TIMER4_TIMER_HCLK_CLK                                                     | CLK_STATE_READY     | 166666666       |
    |    87     |     1    | DEV_MCU_TIMER5_TIMER_TCLK_CLK                                                     | CLK_STATE_READY     | 19200000        |
    |    87     |     2    | DEV_MCU_TIMER5_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT5                        | CLK_STATE_READY     | 19200000        |
    |    87     |     3    | DEV_MCU_TIMER5_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_4_TIMER_PWM               | CLK_STATE_READY     | 0               |
    |    87     |    10    | DEV_MCU_TIMER5_TIMER_HCLK_CLK                                                     | CLK_STATE_READY     | 166666666       |
    |    88     |     0    | DEV_MCU_TIMER6_TIMER_PWM                                                          | CLK_STATE_READY     | 0               |
    |    88     |     1    | DEV_MCU_TIMER6_TIMER_TCLK_CLK                                                     | CLK_STATE_READY     | 19200000        |
    |    88     |     2    | DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                      | CLK_STATE_READY     | 19200000        |
    |    88     |     3    | DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK16  | CLK_STATE_READY     | 62500000        |
    |    88     |     4    | DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY     | 12500000        |
    |    88     |     5    | DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK             | CLK_STATE_READY     | 200000000       |
    |    88     |     6    | DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                  | CLK_STATE_READY     | 0               |
    |    88     |     7    | DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                      | CLK_STATE_READY     | 32768           |
    |    88     |     8    | DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0                  | CLK_STATE_READY     | 0               |
    |    88     |     9    | DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK   | CLK_STATE_READY     | 32000           |
    |    88     |    10    | DEV_MCU_TIMER6_TIMER_HCLK_CLK                                                     | CLK_STATE_READY     | 166666666       |
    |    89     |     1    | DEV_MCU_TIMER7_TIMER_TCLK_CLK                                                     | CLK_STATE_READY     | 19200000        |
    |    89     |     2    | DEV_MCU_TIMER7_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT7                        | CLK_STATE_READY     | 19200000        |
    |    89     |     3    | DEV_MCU_TIMER7_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_6_TIMER_PWM               | CLK_STATE_READY     | 0               |
    |    89     |    10    | DEV_MCU_TIMER7_TIMER_HCLK_CLK                                                     | CLK_STATE_READY     | 166666666       |
    |    90     |     0    | DEV_MCU_TIMER8_TIMER_PWM                                                          | CLK_STATE_READY     | 0               |
    |    90     |     1    | DEV_MCU_TIMER8_TIMER_TCLK_CLK                                                     | CLK_STATE_READY     | 19200000        |
    |    90     |     2    | DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                      | CLK_STATE_READY     | 19200000        |
    |    90     |     3    | DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK16  | CLK_STATE_READY     | 62500000        |
    |    90     |     4    | DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY     | 12500000        |
    |    90     |     5    | DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK             | CLK_STATE_READY     | 200000000       |
    |    90     |     6    | DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                  | CLK_STATE_READY     | 0               |
    |    90     |     7    | DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                      | CLK_STATE_READY     | 32768           |
    |    90     |     8    | DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0                  | CLK_STATE_READY     | 0               |
    |    90     |     9    | DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK   | CLK_STATE_READY     | 32000           |
    |    90     |    10    | DEV_MCU_TIMER8_TIMER_HCLK_CLK                                                     | CLK_STATE_READY     | 166666666       |
    |    91     |     1    | DEV_MCU_TIMER9_TIMER_TCLK_CLK                                                     | CLK_STATE_READY     | 62500000        |
    |    91     |     2    | DEV_MCU_TIMER9_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT9                        | CLK_STATE_READY     | 62500000        |
    |    91     |     3    | DEV_MCU_TIMER9_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_8_TIMER_PWM               | CLK_STATE_READY     | 0               |
    |    91     |    10    | DEV_MCU_TIMER9_TIMER_HCLK_CLK                                                     | CLK_STATE_READY     | 166666666       |
    |   149     |     2    | DEV_MCU_UART0_VBUSP_CLK                                                           | CLK_STATE_READY     | 166666666       |
    |   149     |     3    | DEV_MCU_UART0_FCLK_CLK                                                            | CLK_STATE_READY     | 96000000        |
    |   149     |     4    | DEV_MCU_UART0_FCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT3_CLK                    | CLK_STATE_READY     | 96000000        |
    |   149     |     5    | DEV_MCU_UART0_FCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_1_HSDIVOUT5_CLK                 | CLK_STATE_READY     | 192000000       |
    |    98     |     1    | DEV_MMCSD0_EMMCSS_XIN_CLK                                                         | CLK_STATE_READY     | 200000000       |
    |    98     |     2    | DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT2_CLK                | CLK_STATE_READY     | 200000000       |
    |    98     |     3    | DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT2_CLK                | CLK_STATE_READY     | 192000000       |
    |    98     |     4    | DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK                | CLK_STATE_READY     | 200000000       |
    |    98     |     5    | DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT2_CLK                | CLK_STATE_READY     | 200000000       |
    |    98     |     7    | DEV_MMCSD0_EMMCSS_VBUS_CLK                                                        | CLK_STATE_READY     | 250000000       |
    |    99     |     1    | DEV_MMCSD1_EMMCSDSS_XIN_CLK                                                       | CLK_STATE_READY     | 200000000       |
    |    99     |     2    | DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT2_CLK              | CLK_STATE_READY     | 200000000       |
    |    99     |     3    | DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT2_CLK              | CLK_STATE_READY     | 192000000       |
    |    99     |     4    | DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK              | CLK_STATE_READY     | 200000000       |
    |    99     |     5    | DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT2_CLK              | CLK_STATE_READY     | 200000000       |
    |    99     |     6    | DEV_MMCSD1_EMMCSDSS_IO_CLK_O                                                      | CLK_STATE_READY     | 0               |
    |    99     |     7    | DEV_MMCSD1_EMMCSDSS_IO_CLK_I                                                      | CLK_STATE_READY     | 0               |
    |    99     |     8    | DEV_MMCSD1_EMMCSDSS_VBUS_CLK                                                      | CLK_STATE_READY     | 250000000       |
    |   224     |     0    | DEV_NAVSS0_CPTS0_GENF2                                                            | CLK_STATE_READY     | 0               |
    |   224     |     1    | DEV_NAVSS0_CPTS0_GENF3                                                            | CLK_STATE_READY     | 0               |
    |   225     |     0    | DEV_NAVSS0_BCDMA_0_CLK                                                            | CLK_STATE_READY     | 500000000       |
    |   226     |     0    | DEV_NAVSS0_CPTS_0_TS_GENF0                                                        | CLK_STATE_READY     | 0               |
    |   226     |     2    | DEV_NAVSS0_CPTS_0_TS_GENF1                                                        | CLK_STATE_READY     | 0               |
    |   226     |     4    | DEV_NAVSS0_CPTS_0_VBUSP_GCLK                                                      | CLK_STATE_READY     | 500000000       |
    |   226     |     5    | DEV_NAVSS0_CPTS_0_RCLK                                                            | CLK_STATE_READY     | 200000000       |
    |   226     |     6    | DEV_NAVSS0_CPTS_0_RCLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK                   | CLK_STATE_READY     | 250000000       |
    |   226     |     7    | DEV_NAVSS0_CPTS_0_RCLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK                 | CLK_STATE_READY     | 200000000       |
    |   226     |     8    | DEV_NAVSS0_CPTS_0_RCLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT                       | CLK_STATE_READY     | 0               |
    |   226     |     9    | DEV_NAVSS0_CPTS_0_RCLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT                           | CLK_STATE_READY     | 0               |
    |   226     |    10    | DEV_NAVSS0_CPTS_0_RCLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                         | CLK_STATE_READY     | 0               |
    |   226     |    11    | DEV_NAVSS0_CPTS_0_RCLK_PARENT_BOARD_0_EXT_REFCLK1_OUT                             | CLK_STATE_READY     | 0               |
    |   226     |    12    | DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN0_TXMCLK                  | CLK_STATE_READY     | 0               |
    |   226     |    13    | DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN1_TXMCLK                  | CLK_STATE_READY     | 0               |
    |   226     |    14    | DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN2_TXMCLK                  | CLK_STATE_READY     | 0               |
    |   226     |    15    | DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN3_TXMCLK                  | CLK_STATE_READY     | 0               |
    |   226     |    20    | DEV_NAVSS0_CPTS_0_RCLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK                    | CLK_STATE_READY     | 500000000       |
    |   226     |    21    | DEV_NAVSS0_CPTS_0_RCLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK           | CLK_STATE_READY     | 500000000       |
    |   227     |     0    | DEV_NAVSS0_INTR_0_INTR_CLK                                                        | CLK_STATE_READY     | 500000000       |
    |   228     |     0    | DEV_NAVSS0_MAILBOX1_0_VCLK_CLK                                                    | CLK_STATE_READY     | 500000000       |
    |   229     |     0    | DEV_NAVSS0_MAILBOX1_1_VCLK_CLK                                                    | CLK_STATE_READY     | 500000000       |
    |   238     |     0    | DEV_NAVSS0_MAILBOX1_10_VCLK_CLK                                                   | CLK_STATE_READY     | 500000000       |
    |   239     |     0    | DEV_NAVSS0_MAILBOX1_11_VCLK_CLK                                                   | CLK_STATE_READY     | 500000000       |
    |   230     |     0    | DEV_NAVSS0_MAILBOX1_2_VCLK_CLK                                                    | CLK_STATE_READY     | 500000000       |
    |   231     |     0    | DEV_NAVSS0_MAILBOX1_3_VCLK_CLK                                                    | CLK_STATE_READY     | 500000000       |
    |   232     |     0    | DEV_NAVSS0_MAILBOX1_4_VCLK_CLK                                                    | CLK_STATE_READY     | 500000000       |
    |   233     |     0    | DEV_NAVSS0_MAILBOX1_5_VCLK_CLK                                                    | CLK_STATE_READY     | 500000000       |
    |   234     |     0    | DEV_NAVSS0_MAILBOX1_6_VCLK_CLK                                                    | CLK_STATE_READY     | 500000000       |
    |   235     |     0    | DEV_NAVSS0_MAILBOX1_7_VCLK_CLK                                                    | CLK_STATE_READY     | 500000000       |
    |   236     |     0    | DEV_NAVSS0_MAILBOX1_8_VCLK_CLK                                                    | CLK_STATE_READY     | 500000000       |
    |   237     |     0    | DEV_NAVSS0_MAILBOX1_9_VCLK_CLK                                                    | CLK_STATE_READY     | 500000000       |
    |   240     |     0    | DEV_NAVSS0_MAILBOX_0_VCLK_CLK                                                     | CLK_STATE_READY     | 500000000       |
    |   241     |     0    | DEV_NAVSS0_MAILBOX_1_VCLK_CLK                                                     | CLK_STATE_READY     | 500000000       |
    |   250     |     0    | DEV_NAVSS0_MAILBOX_10_VCLK_CLK                                                    | CLK_STATE_READY     | 500000000       |
    |   251     |     0    | DEV_NAVSS0_MAILBOX_11_VCLK_CLK                                                    | CLK_STATE_READY     | 500000000       |
    |   242     |     0    | DEV_NAVSS0_MAILBOX_2_VCLK_CLK                                                     | CLK_STATE_READY     | 500000000       |
    |   243     |     0    | DEV_NAVSS0_MAILBOX_3_VCLK_CLK                                                     | CLK_STATE_READY     | 500000000       |
    |   244     |     0    | DEV_NAVSS0_MAILBOX_4_VCLK_CLK                                                     | CLK_STATE_READY     | 500000000       |
    |   245     |     0    | DEV_NAVSS0_MAILBOX_5_VCLK_CLK                                                     | CLK_STATE_READY     | 500000000       |
    |   246     |     0    | DEV_NAVSS0_MAILBOX_6_VCLK_CLK                                                     | CLK_STATE_READY     | 500000000       |
    |   247     |     0    | DEV_NAVSS0_MAILBOX_7_VCLK_CLK                                                     | CLK_STATE_READY     | 500000000       |
    |   248     |     0    | DEV_NAVSS0_MAILBOX_8_VCLK_CLK                                                     | CLK_STATE_READY     | 500000000       |
    |   249     |     0    | DEV_NAVSS0_MAILBOX_9_VCLK_CLK                                                     | CLK_STATE_READY     | 500000000       |
    |   252     |     0    | DEV_NAVSS0_MCRC_0_CLK                                                             | CLK_STATE_READY     | 500000000       |
    |   253     |     0    | DEV_NAVSS0_MODSS_VD2CLK                                                           | CLK_STATE_READY     | 500000000       |
    |   254     |     0    | DEV_NAVSS0_MODSS_INTA_0_SYS_CLK                                                   | CLK_STATE_READY     | 500000000       |
    |   255     |     0    | DEV_NAVSS0_MODSS_INTA_1_SYS_CLK                                                   | CLK_STATE_READY     | 500000000       |
    |   256     |     0    | DEV_NAVSS0_PROXY_0_CLK_CLK                                                        | CLK_STATE_READY     | 500000000       |
    |   257     |     0    | DEV_NAVSS0_PVU_0_CLK_CLK                                                          | CLK_STATE_READY     | 500000000       |
    |   258     |     0    | DEV_NAVSS0_PVU_1_CLK_CLK                                                          | CLK_STATE_READY     | 500000000       |
    |   259     |     0    | DEV_NAVSS0_RINGACC_0_SYS_CLK                                                      | CLK_STATE_READY     | 500000000       |
    |   260     |     0    | DEV_NAVSS0_SPINLOCK_0_CLK                                                         | CLK_STATE_READY     | 500000000       |
    |   261     |     0    | DEV_NAVSS0_TIMERMGR_0_EON_TICK_EVT                                                | CLK_STATE_READY     | 0               |
    |   261     |     1    | DEV_NAVSS0_TIMERMGR_0_VCLK_CLK                                                    | CLK_STATE_READY     | 500000000       |
    |   262     |     0    | DEV_NAVSS0_TIMERMGR_1_EON_TICK_EVT                                                | CLK_STATE_READY     | 0               |
    |   262     |     1    | DEV_NAVSS0_TIMERMGR_1_VCLK_CLK                                                    | CLK_STATE_READY     | 500000000       |
    |   263     |     0    | DEV_NAVSS0_UDMAP_0_SYS_CLK                                                        | CLK_STATE_READY     | 500000000       |
    |   264     |     0    | DEV_NAVSS0_UDMASS_VD2CLK                                                          | CLK_STATE_READY     | 500000000       |
    |   265     |     0    | DEV_NAVSS0_UDMASS_INTA_0_SYS_CLK                                                  | CLK_STATE_READY     | 500000000       |
    |   266     |     0    | DEV_NAVSS0_VIRTSS_VD2CLK                                                          | CLK_STATE_READY     | 500000000       |
    |   171     |     1    | DEV_PBIST0_CLK8_CLK                                                               | CLK_STATE_READY     | 125000000       |
    |   172     |     1    | DEV_PBIST1_CLK8_CLK                                                               | CLK_STATE_READY     | 125000000       |
    |   175     |     1    | DEV_PBIST10_CLK8_CLK                                                              | CLK_STATE_READY     | 125000000       |
    |   168     |     4    | DEV_PBIST11_CLK7_CLK                                                              | CLK_STATE_READY     | 125000000       |
    |   174     |     1    | DEV_PBIST2_CLK8_CLK                                                               | CLK_STATE_READY     | 125000000       |
    |   170     |     1    | DEV_PBIST3_CLK8_CLK                                                               | CLK_STATE_READY     | 125000000       |
    |   173     |     1    | DEV_PBIST4_CLK8_CLK                                                               | CLK_STATE_READY     | 125000000       |
    |   167     |     1    | DEV_PBIST5_CLK8_CLK                                                               | CLK_STATE_READY     | 125000000       |
    |   276     |     0    | DEV_PCIE1_PCIE_LANE0_TXMCLK                                                       | CLK_STATE_READY     | 0               |
    |   276     |     1    | DEV_PCIE1_PCIE_LANE0_TXFCLK                                                       | CLK_STATE_READY     | 0               |
    |   276     |     2    | DEV_PCIE1_PCIE_LANE0_RXFCLK                                                       | CLK_STATE_READY     | 0               |
    |   276     |     3    | DEV_PCIE1_PCIE_LANE0_TXCLK                                                        | CLK_STATE_READY     | 0               |
    |   276     |     4    | DEV_PCIE1_PCIE_LANE3_RXFCLK                                                       | CLK_STATE_READY     | 0               |
    |   276     |     5    | DEV_PCIE1_PCIE_LANE3_RXCLK                                                        | CLK_STATE_READY     | 0               |
    |   276     |     6    | DEV_PCIE1_PCIE_LANE2_RXFCLK                                                       | CLK_STATE_READY     | 0               |
    |   276     |     7    | DEV_PCIE1_PCIE_LANE1_TXCLK                                                        | CLK_STATE_READY     | 0               |
    |   276     |     8    | DEV_PCIE1_PCIE_CPTS_RCLK_CLK                                                      | CLK_STATE_READY     | 250000000       |
    |   276     |     9    | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK             | CLK_STATE_READY     | 250000000       |
    |   276     |    10    | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK           | CLK_STATE_READY     | 200000000       |
    |   276     |    11    | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT                 | CLK_STATE_READY     | 0               |
    |   276     |    12    | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT                     | CLK_STATE_READY     | 0               |
    |   276     |    13    | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                   | CLK_STATE_READY     | 0               |
    |   276     |    14    | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT                       | CLK_STATE_READY     | 0               |
    |   276     |    15    | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN0_TXMCLK            | CLK_STATE_READY     | 0               |
    |   276     |    16    | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN1_TXMCLK            | CLK_STATE_READY     | 0               |
    |   276     |    17    | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN2_TXMCLK            | CLK_STATE_READY     | 0               |
    |   276     |    18    | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN3_TXMCLK            | CLK_STATE_READY     | 0               |
    |   276     |    23    | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK              | CLK_STATE_READY     | 500000000       |
    |   276     |    24    | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK     | CLK_STATE_READY     | 500000000       |
    |   276     |    26    | DEV_PCIE1_PCIE_LANE3_TXMCLK                                                       | CLK_STATE_READY     | 0               |
    |   276     |    27    | DEV_PCIE1_PCIE_LANE2_RXCLK                                                        | CLK_STATE_READY     | 0               |
    |   276     |    28    | DEV_PCIE1_PCIE_LANE1_RXFCLK                                                       | CLK_STATE_READY     | 0               |
    |   276     |    29    | DEV_PCIE1_PCIE_LANE0_RXCLK                                                        | CLK_STATE_READY     | 0               |
    |   276     |    30    | DEV_PCIE1_PCIE_LANE2_REFCLK                                                       | CLK_STATE_READY     | 0               |
    |   276     |    31    | DEV_PCIE1_PCIE_LANE3_REFCLK                                                       | CLK_STATE_READY     | 0               |
    |   276     |    32    | DEV_PCIE1_PCIE_LANE2_TXMCLK                                                       | CLK_STATE_READY     | 0               |
    |   276     |    33    | DEV_PCIE1_PCIE_LANE1_REFCLK                                                       | CLK_STATE_READY     | 0               |
    |   276     |    34    | DEV_PCIE1_PCIE_LANE2_TXFCLK                                                       | CLK_STATE_READY     | 0               |
    |   276     |    35    | DEV_PCIE1_PCIE_PM_CLK                                                             | CLK_STATE_READY     | 12500000        |
    |   276     |    36    | DEV_PCIE1_PCIE_LANE1_TXFCLK                                                       | CLK_STATE_READY     | 0               |
    |   276     |    37    | DEV_PCIE1_PCIE_LANE1_TXMCLK                                                       | CLK_STATE_READY     | 0               |
    |   276     |    38    | DEV_PCIE1_PCIE_LANE0_REFCLK                                                       | CLK_STATE_READY     | 0               |
    |   276     |    39    | DEV_PCIE1_PCIE_LANE1_RXCLK                                                        | CLK_STATE_READY     | 0               |
    |   276     |    40    | DEV_PCIE1_PCIE_LANE3_TXFCLK                                                       | CLK_STATE_READY     | 0               |
    |   276     |    41    | DEV_PCIE1_PCIE_CBA_CLK                                                            | CLK_STATE_READY     | 250000000       |
    |   276     |    42    | DEV_PCIE1_PCIE_LANE2_TXCLK                                                        | CLK_STATE_READY     | 0               |
    |   276     |    43    | DEV_PCIE1_PCIE_LANE3_TXCLK                                                        | CLK_STATE_READY     | 0               |
    |   143     |     0    | DEV_PSC0_SLOW_CLK                                                                 | CLK_STATE_READY     | 20833333        |
    |   143     |     1    | DEV_PSC0_CLK                                                                      | CLK_STATE_READY     | 125000000       |
    |   279     |     0    | DEV_R5FSS0_CORE0_CPU_CLK                                                          | CLK_STATE_READY     | 1000000000      |
    |   279     |     1    | DEV_R5FSS0_CORE0_INTERFACE_CLK                                                    | CLK_STATE_READY     | 1000000000      |
    |   280     |     0    | DEV_R5FSS0_CORE1_CPU_CLK                                                          | CLK_STATE_READY     | 1000000000      |
    |   280     |     1    | DEV_R5FSS0_CORE1_INTERFACE_CLK                                                    | CLK_STATE_READY     | 1000000000      |
    |   281     |     0    | DEV_R5FSS1_CORE0_CPU_CLK                                                          | CLK_STATE_READY     | 1000000000      |
    |   281     |     1    | DEV_R5FSS1_CORE0_INTERFACE_CLK                                                    | CLK_STATE_READY     | 1000000000      |
    |   282     |     0    | DEV_R5FSS1_CORE1_CPU_CLK                                                          | CLK_STATE_READY     | 1000000000      |
    |   282     |     1    | DEV_R5FSS1_CORE1_INTERFACE_CLK                                                    | CLK_STATE_READY     | 1000000000      |
    |   286     |     0    | DEV_RTI0_VBUSP_CLK                                                                | CLK_STATE_READY     | 125000000       |
    |   286     |     1    | DEV_RTI0_RTI_CLK                                                                  | CLK_STATE_READY     | 32000           |
    |   286     |     2    | DEV_RTI0_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                                   | CLK_STATE_READY     | 19200000        |
    |   286     |     3    | DEV_RTI0_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                                   | CLK_STATE_READY     | 32768           |
    |   286     |     4    | DEV_RTI0_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK              | CLK_STATE_READY     | 12500000        |
    |   286     |     5    | DEV_RTI0_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK                | CLK_STATE_READY     | 32000           |
    |   286     |     6    | DEV_RTI0_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                                    | CLK_STATE_READY     | 0               |
    |   286     |     7    | DEV_RTI0_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0                               | CLK_STATE_READY     | 0               |
    |   286     |     8    | DEV_RTI0_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1                               | CLK_STATE_READY     | 0               |
    |   286     |     9    | DEV_RTI0_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2                               | CLK_STATE_READY     | 0               |
    |   287     |     0    | DEV_RTI1_VBUSP_CLK                                                                | CLK_STATE_READY     | 125000000       |
    |   287     |     1    | DEV_RTI1_RTI_CLK                                                                  | CLK_STATE_READY     | 32000           |
    |   287     |     2    | DEV_RTI1_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                                   | CLK_STATE_READY     | 19200000        |
    |   287     |     3    | DEV_RTI1_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                                   | CLK_STATE_READY     | 32768           |
    |   287     |     4    | DEV_RTI1_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK              | CLK_STATE_READY     | 12500000        |
    |   287     |     5    | DEV_RTI1_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK                | CLK_STATE_READY     | 32000           |
    |   287     |     6    | DEV_RTI1_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                                    | CLK_STATE_READY     | 0               |
    |   287     |     7    | DEV_RTI1_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0                               | CLK_STATE_READY     | 0               |
    |   287     |     8    | DEV_RTI1_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1                               | CLK_STATE_READY     | 0               |
    |   287     |     9    | DEV_RTI1_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2                               | CLK_STATE_READY     | 0               |
    |   290     |     0    | DEV_RTI15_VBUSP_CLK                                                               | CLK_STATE_READY     | 125000000       |
    |   290     |     1    | DEV_RTI15_RTI_CLK                                                                 | CLK_STATE_READY     | 19200000        |
    |   290     |     2    | DEV_RTI15_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                                  | CLK_STATE_READY     | 19200000        |
    |   290     |     3    | DEV_RTI15_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                                  | CLK_STATE_READY     | 32768           |
    |   290     |     4    | DEV_RTI15_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK             | CLK_STATE_READY     | 12500000        |
    |   290     |     5    | DEV_RTI15_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK               | CLK_STATE_READY     | 32000           |
    |   290     |     6    | DEV_RTI15_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                                   | CLK_STATE_READY     | 0               |
    |   290     |     7    | DEV_RTI15_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0                              | CLK_STATE_READY     | 0               |
    |   290     |     8    | DEV_RTI15_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1                              | CLK_STATE_READY     | 0               |
    |   290     |     9    | DEV_RTI15_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2                              | CLK_STATE_READY     | 0               |
    |   288     |     0    | DEV_RTI16_VBUSP_CLK                                                               | CLK_STATE_READY     | 125000000       |
    |   288     |     1    | DEV_RTI16_RTI_CLK                                                                 | CLK_STATE_READY     | 19200000        |
    |   288     |     2    | DEV_RTI16_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                                  | CLK_STATE_READY     | 19200000        |
    |   288     |     3    | DEV_RTI16_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                                  | CLK_STATE_READY     | 32768           |
    |   288     |     4    | DEV_RTI16_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK             | CLK_STATE_READY     | 12500000        |
    |   288     |     5    | DEV_RTI16_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK               | CLK_STATE_READY     | 32000           |
    |   288     |     6    | DEV_RTI16_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                                   | CLK_STATE_READY     | 0               |
    |   288     |     7    | DEV_RTI16_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0                              | CLK_STATE_READY     | 0               |
    |   288     |     8    | DEV_RTI16_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1                              | CLK_STATE_READY     | 0               |
    |   288     |     9    | DEV_RTI16_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2                              | CLK_STATE_READY     | 0               |
    |   289     |     0    | DEV_RTI17_VBUSP_CLK                                                               | CLK_STATE_READY     | 125000000       |
    |   289     |     1    | DEV_RTI17_RTI_CLK                                                                 | CLK_STATE_READY     | 19200000        |
    |   289     |     2    | DEV_RTI17_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                                  | CLK_STATE_READY     | 19200000        |
    |   289     |     3    | DEV_RTI17_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                                  | CLK_STATE_READY     | 32768           |
    |   289     |     4    | DEV_RTI17_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK             | CLK_STATE_READY     | 12500000        |
    |   289     |     5    | DEV_RTI17_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK               | CLK_STATE_READY     | 32000           |
    |   289     |     6    | DEV_RTI17_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                                   | CLK_STATE_READY     | 0               |
    |   289     |     7    | DEV_RTI17_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0                              | CLK_STATE_READY     | 0               |
    |   289     |     8    | DEV_RTI17_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1                              | CLK_STATE_READY     | 0               |
    |   289     |     9    | DEV_RTI17_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2                              | CLK_STATE_READY     | 0               |
    |   291     |     0    | DEV_RTI28_VBUSP_CLK                                                               | CLK_STATE_READY     | 125000000       |
    |   291     |     1    | DEV_RTI28_RTI_CLK                                                                 | CLK_STATE_READY     | 19200000        |
    |   291     |     2    | DEV_RTI28_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                                  | CLK_STATE_READY     | 19200000        |
    |   291     |     3    | DEV_RTI28_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                                  | CLK_STATE_READY     | 32768           |
    |   291     |     4    | DEV_RTI28_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK             | CLK_STATE_READY     | 12500000        |
    |   291     |     5    | DEV_RTI28_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK               | CLK_STATE_READY     | 32000           |
    |   291     |     6    | DEV_RTI28_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                                   | CLK_STATE_READY     | 0               |
    |   291     |     7    | DEV_RTI28_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0                              | CLK_STATE_READY     | 0               |
    |   291     |     8    | DEV_RTI28_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1                              | CLK_STATE_READY     | 0               |
    |   291     |     9    | DEV_RTI28_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2                              | CLK_STATE_READY     | 0               |
    |   292     |     0    | DEV_RTI29_VBUSP_CLK                                                               | CLK_STATE_READY     | 125000000       |
    |   292     |     1    | DEV_RTI29_RTI_CLK                                                                 | CLK_STATE_READY     | 19200000        |
    |   292     |     2    | DEV_RTI29_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                                  | CLK_STATE_READY     | 19200000        |
    |   292     |     3    | DEV_RTI29_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                                  | CLK_STATE_READY     | 32768           |
    |   292     |     4    | DEV_RTI29_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK             | CLK_STATE_READY     | 12500000        |
    |   292     |     5    | DEV_RTI29_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK               | CLK_STATE_READY     | 32000           |
    |   292     |     6    | DEV_RTI29_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                                   | CLK_STATE_READY     | 0               |
    |   292     |     7    | DEV_RTI29_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0                              | CLK_STATE_READY     | 0               |
    |   292     |     8    | DEV_RTI29_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1                              | CLK_STATE_READY     | 0               |
    |   292     |     9    | DEV_RTI29_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2                              | CLK_STATE_READY     | 0               |
    |   293     |     0    | DEV_RTI30_VBUSP_CLK                                                               | CLK_STATE_READY     | 125000000       |
    |   293     |     1    | DEV_RTI30_RTI_CLK                                                                 | CLK_STATE_READY     | 19200000        |
    |   293     |     2    | DEV_RTI30_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                                  | CLK_STATE_READY     | 19200000        |
    |   293     |     3    | DEV_RTI30_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                                  | CLK_STATE_READY     | 32768           |
    |   293     |     4    | DEV_RTI30_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK             | CLK_STATE_READY     | 12500000        |
    |   293     |     5    | DEV_RTI30_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK               | CLK_STATE_READY     | 32000           |
    |   293     |     6    | DEV_RTI30_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                                   | CLK_STATE_READY     | 0               |
    |   293     |     7    | DEV_RTI30_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0                              | CLK_STATE_READY     | 0               |
    |   293     |     8    | DEV_RTI30_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1                              | CLK_STATE_READY     | 0               |
    |   293     |     9    | DEV_RTI30_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2                              | CLK_STATE_READY     | 0               |
    |   294     |     0    | DEV_RTI31_VBUSP_CLK                                                               | CLK_STATE_READY     | 125000000       |
    |   294     |     1    | DEV_RTI31_RTI_CLK                                                                 | CLK_STATE_READY     | 19200000        |
    |   294     |     2    | DEV_RTI31_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                                  | CLK_STATE_READY     | 19200000        |
    |   294     |     3    | DEV_RTI31_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                                  | CLK_STATE_READY     | 32768           |
    |   294     |     4    | DEV_RTI31_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK             | CLK_STATE_READY     | 12500000        |
    |   294     |     5    | DEV_RTI31_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK               | CLK_STATE_READY     | 32000           |
    |   294     |     6    | DEV_RTI31_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                                   | CLK_STATE_READY     | 0               |
    |   294     |     7    | DEV_RTI31_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0                              | CLK_STATE_READY     | 0               |
    |   294     |     8    | DEV_RTI31_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1                              | CLK_STATE_READY     | 0               |
    |   294     |     9    | DEV_RTI31_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2                              | CLK_STATE_READY     | 0               |
    |   145     |     0    | DEV_SA2_CPSW_PSILSS0_MAIN_CLK                                                     | CLK_STATE_READY     | 500000000       |
    |   145     |     1    | DEV_SA2_CPSW_PSILSS0_MAIN_2_CLK                                                   | CLK_STATE_READY     | 250000000       |
    |   297     |     0    | DEV_SA2_UL0_PKA_IN_CLK                                                            | CLK_STATE_READY     | 400000000       |
    |   297     |     1    | DEV_SA2_UL0_X1_CLK                                                                | CLK_STATE_READY     | 125000000       |
    |   297     |     2    | DEV_SA2_UL0_X2_CLK                                                                | CLK_STATE_READY     | 250000000       |
    |   365     |     0    | DEV_SERDES_10G0_CLK                                                               | CLK_STATE_READY     | 125000000       |
    |   365     |     1    | DEV_SERDES_10G0_CMN_REFCLK_M                                                      | CLK_STATE_READY     | 0               |
    |   365     |     1    | DEV_SERDES_10G0_CMN_REFCLK_M                                                      | CLK_STATE_READY     | 0               |
    |   365     |     2    | DEV_SERDES_10G0_CMN_REFCLK_P                                                      | CLK_STATE_READY     | 0               |
    |   365     |     2    | DEV_SERDES_10G0_CMN_REFCLK_P                                                      | CLK_STATE_READY     | 0               |
    |   365     |     3    | DEV_SERDES_10G0_CORE_REF_CLK                                                      | CLK_STATE_READY     | 100000000       |
    |   365     |     4    | DEV_SERDES_10G0_CORE_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                       | CLK_STATE_READY     | 19200000        |
    |   365     |     5    | DEV_SERDES_10G0_CORE_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                        | CLK_STATE_READY     | 0               |
    |   365     |     6    | DEV_SERDES_10G0_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK             | CLK_STATE_READY     | 125000000       |
    |   365     |     7    | DEV_SERDES_10G0_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK             | CLK_STATE_READY     | 100000000       |
    |   365     |     9    | DEV_SERDES_10G0_IP1_LN0_REFCLK                                                    | CLK_STATE_READY     | 0               |
    |   365     |    10    | DEV_SERDES_10G0_IP1_LN0_RXCLK                                                     | CLK_STATE_READY     | 0               |
    |   365     |    11    | DEV_SERDES_10G0_IP1_LN0_RXFCLK                                                    | CLK_STATE_READY     | 0               |
    |   365     |    12    | DEV_SERDES_10G0_IP1_LN0_TXCLK                                                     | CLK_STATE_NOT_READY | 0               |
    |   365     |    13    | DEV_SERDES_10G0_IP1_LN0_TXFCLK                                                    | CLK_STATE_READY     | 0               |
    |   365     |    14    | DEV_SERDES_10G0_IP1_LN0_TXMCLK                                                    | CLK_STATE_READY     | 0               |
    |   365     |    15    | DEV_SERDES_10G0_IP1_LN1_REFCLK                                                    | CLK_STATE_READY     | 0               |
    |   365     |    16    | DEV_SERDES_10G0_IP1_LN1_RXCLK                                                     | CLK_STATE_READY     | 0               |
    |   365     |    17    | DEV_SERDES_10G0_IP1_LN1_RXFCLK                                                    | CLK_STATE_READY     | 0               |
    |   365     |    18    | DEV_SERDES_10G0_IP1_LN1_TXCLK                                                     | CLK_STATE_NOT_READY | 0               |
    |   365     |    19    | DEV_SERDES_10G0_IP1_LN1_TXFCLK                                                    | CLK_STATE_READY     | 0               |
    |   365     |    20    | DEV_SERDES_10G0_IP1_LN1_TXMCLK                                                    | CLK_STATE_READY     | 0               |
    |   365     |    21    | DEV_SERDES_10G0_IP1_LN2_REFCLK                                                    | CLK_STATE_READY     | 0               |
    |   365     |    22    | DEV_SERDES_10G0_IP1_LN2_RXCLK                                                     | CLK_STATE_READY     | 0               |
    |   365     |    23    | DEV_SERDES_10G0_IP1_LN2_RXFCLK                                                    | CLK_STATE_READY     | 0               |
    |   365     |    24    | DEV_SERDES_10G0_IP1_LN2_TXCLK                                                     | CLK_STATE_NOT_READY | 0               |
    |   365     |    25    | DEV_SERDES_10G0_IP1_LN2_TXCLK_PARENT_K3_DSS_EDP_MAIN_0_PHY_LN2_TXCLK              | CLK_STATE_NOT_READY | 0               |
    |   365     |    26    | DEV_SERDES_10G0_IP1_LN2_TXCLK_PARENT_K3_DSS_EDP_MAIN_0_PHY_LN0_TXCLK              | CLK_STATE_NOT_READY | 0               |
    |   365     |    27    | DEV_SERDES_10G0_IP1_LN2_TXFCLK                                                    | CLK_STATE_READY     | 0               |
    |   365     |    28    | DEV_SERDES_10G0_IP1_LN2_TXMCLK                                                    | CLK_STATE_READY     | 0               |
    |   365     |    29    | DEV_SERDES_10G0_IP1_LN3_REFCLK                                                    | CLK_STATE_READY     | 0               |
    |   365     |    30    | DEV_SERDES_10G0_IP1_LN3_RXCLK                                                     | CLK_STATE_READY     | 0               |
    |   365     |    31    | DEV_SERDES_10G0_IP1_LN3_RXFCLK                                                    | CLK_STATE_READY     | 0               |
    |   365     |    32    | DEV_SERDES_10G0_IP1_LN3_TXCLK                                                     | CLK_STATE_NOT_READY | 0               |
    |   365     |    33    | DEV_SERDES_10G0_IP1_LN3_TXCLK_PARENT_K3_DSS_EDP_MAIN_0_PHY_LN3_TXCLK              | CLK_STATE_NOT_READY | 0               |
    |   365     |    34    | DEV_SERDES_10G0_IP1_LN3_TXCLK_PARENT_K3_DSS_EDP_MAIN_0_PHY_LN1_TXCLK              | CLK_STATE_NOT_READY | 0               |
    |   365     |    35    | DEV_SERDES_10G0_IP1_LN3_TXFCLK                                                    | CLK_STATE_READY     | 0               |
    |   365     |    36    | DEV_SERDES_10G0_IP1_LN3_TXMCLK                                                    | CLK_STATE_READY     | 0               |
    |   365     |    37    | DEV_SERDES_10G0_IP2_LN0_REFCLK                                                    | CLK_STATE_READY     | 0               |
    |   365     |    38    | DEV_SERDES_10G0_IP2_LN0_RXCLK                                                     | CLK_STATE_READY     | 0               |
    |   365     |    39    | DEV_SERDES_10G0_IP2_LN0_RXFCLK                                                    | CLK_STATE_READY     | 0               |
    |   365     |    40    | DEV_SERDES_10G0_IP2_LN0_TXCLK                                                     | CLK_STATE_NOT_READY | 0               |
    |   365     |    41    | DEV_SERDES_10G0_IP2_LN0_TXFCLK                                                    | CLK_STATE_READY     | 0               |
    |   365     |    42    | DEV_SERDES_10G0_IP2_LN0_TXMCLK                                                    | CLK_STATE_READY     | 0               |
    |   365     |    43    | DEV_SERDES_10G0_IP2_LN1_REFCLK                                                    | CLK_STATE_READY     | 0               |
    |   365     |    44    | DEV_SERDES_10G0_IP2_LN1_RXCLK                                                     | CLK_STATE_READY     | 0               |
    |   365     |    45    | DEV_SERDES_10G0_IP2_LN1_RXFCLK                                                    | CLK_STATE_READY     | 0               |
    |   365     |    46    | DEV_SERDES_10G0_IP2_LN1_TXCLK                                                     | CLK_STATE_NOT_READY | 0               |
    |   365     |    47    | DEV_SERDES_10G0_IP2_LN1_TXFCLK                                                    | CLK_STATE_READY     | 0               |
    |   365     |    48    | DEV_SERDES_10G0_IP2_LN1_TXMCLK                                                    | CLK_STATE_READY     | 0               |
    |   365     |    49    | DEV_SERDES_10G0_IP2_LN2_REFCLK                                                    | CLK_STATE_READY     | 0               |
    |   365     |    50    | DEV_SERDES_10G0_IP2_LN2_RXCLK                                                     | CLK_STATE_READY     | 0               |
    |   365     |    51    | DEV_SERDES_10G0_IP2_LN2_RXFCLK                                                    | CLK_STATE_READY     | 0               |
    |   365     |    52    | DEV_SERDES_10G0_IP2_LN2_TXCLK                                                     | CLK_STATE_NOT_READY | 0               |
    |   365     |    53    | DEV_SERDES_10G0_IP2_LN2_TXFCLK                                                    | CLK_STATE_READY     | 0               |
    |   365     |    54    | DEV_SERDES_10G0_IP2_LN2_TXMCLK                                                    | CLK_STATE_READY     | 0               |
    |   365     |    55    | DEV_SERDES_10G0_IP2_LN3_REFCLK                                                    | CLK_STATE_READY     | 0               |
    |   365     |    56    | DEV_SERDES_10G0_IP2_LN3_RXCLK                                                     | CLK_STATE_READY     | 0               |
    |   365     |    57    | DEV_SERDES_10G0_IP2_LN3_RXFCLK                                                    | CLK_STATE_READY     | 0               |
    |   365     |    58    | DEV_SERDES_10G0_IP2_LN3_TXCLK                                                     | CLK_STATE_NOT_READY | 0               |
    |   365     |    59    | DEV_SERDES_10G0_IP2_LN3_TXFCLK                                                    | CLK_STATE_READY     | 0               |
    |   365     |    60    | DEV_SERDES_10G0_IP2_LN3_TXMCLK                                                    | CLK_STATE_READY     | 0               |
    |   365     |    67    | DEV_SERDES_10G0_IP3_LN1_REFCLK                                                    | CLK_STATE_READY     | 0               |
    |   365     |    68    | DEV_SERDES_10G0_IP3_LN1_RXCLK                                                     | CLK_STATE_READY     | 0               |
    |   365     |    69    | DEV_SERDES_10G0_IP3_LN1_RXFCLK                                                    | CLK_STATE_READY     | 0               |
    |   365     |    70    | DEV_SERDES_10G0_IP3_LN1_TXCLK                                                     | CLK_STATE_READY     | 0               |
    |   365     |    71    | DEV_SERDES_10G0_IP3_LN1_TXFCLK                                                    | CLK_STATE_READY     | 0               |
    |   365     |    72    | DEV_SERDES_10G0_IP3_LN1_TXMCLK                                                    | CLK_STATE_READY     | 0               |
    |   365     |    79    | DEV_SERDES_10G0_IP3_LN3_REFCLK                                                    | CLK_STATE_READY     | 0               |
    |   365     |    80    | DEV_SERDES_10G0_IP3_LN3_RXCLK                                                     | CLK_STATE_READY     | 0               |
    |   365     |    81    | DEV_SERDES_10G0_IP3_LN3_RXFCLK                                                    | CLK_STATE_READY     | 0               |
    |   365     |    82    | DEV_SERDES_10G0_IP3_LN3_TXCLK                                                     | CLK_STATE_READY     | 0               |
    |   365     |    83    | DEV_SERDES_10G0_IP3_LN3_TXFCLK                                                    | CLK_STATE_READY     | 0               |
    |   365     |    84    | DEV_SERDES_10G0_IP3_LN3_TXMCLK                                                    | CLK_STATE_READY     | 0               |
    |   365     |    85    | DEV_SERDES_10G0_IP4_LN0_REFCLK                                                    | CLK_STATE_READY     | 0               |
    |   365     |    86    | DEV_SERDES_10G0_IP4_LN0_RXCLK                                                     | CLK_STATE_READY     | 0               |
    |   365     |    87    | DEV_SERDES_10G0_IP4_LN0_RXFCLK                                                    | CLK_STATE_READY     | 0               |
    |   365     |    88    | DEV_SERDES_10G0_IP4_LN0_TXCLK                                                     | CLK_STATE_NOT_READY | 0               |
    |   365     |    89    | DEV_SERDES_10G0_IP4_LN0_TXFCLK                                                    | CLK_STATE_READY     | 0               |
    |   365     |    90    | DEV_SERDES_10G0_IP4_LN0_TXMCLK                                                    | CLK_STATE_READY     | 0               |
    |   365     |    91    | DEV_SERDES_10G0_IP4_LN1_REFCLK                                                    | CLK_STATE_READY     | 0               |
    |   365     |    92    | DEV_SERDES_10G0_IP4_LN1_RXCLK                                                     | CLK_STATE_READY     | 0               |
    |   365     |    93    | DEV_SERDES_10G0_IP4_LN1_RXFCLK                                                    | CLK_STATE_READY     | 0               |
    |   365     |    94    | DEV_SERDES_10G0_IP4_LN1_TXCLK                                                     | CLK_STATE_NOT_READY | 0               |
    |   365     |    95    | DEV_SERDES_10G0_IP4_LN1_TXFCLK                                                    | CLK_STATE_READY     | 0               |
    |   365     |    96    | DEV_SERDES_10G0_IP4_LN1_TXMCLK                                                    | CLK_STATE_READY     | 0               |
    |   365     |    97    | DEV_SERDES_10G0_IP4_LN2_REFCLK                                                    | CLK_STATE_READY     | 0               |
    |   365     |    98    | DEV_SERDES_10G0_IP4_LN2_RXCLK                                                     | CLK_STATE_READY     | 0               |
    |   365     |    99    | DEV_SERDES_10G0_IP4_LN2_RXFCLK                                                    | CLK_STATE_READY     | 0               |
    |   365     |   100    | DEV_SERDES_10G0_IP4_LN2_TXCLK                                                     | CLK_STATE_NOT_READY | 0               |
    |   365     |   101    | DEV_SERDES_10G0_IP4_LN2_TXFCLK                                                    | CLK_STATE_READY     | 0               |
    |   365     |   102    | DEV_SERDES_10G0_IP4_LN2_TXMCLK                                                    | CLK_STATE_READY     | 0               |
    |   365     |   103    | DEV_SERDES_10G0_IP4_LN3_REFCLK                                                    | CLK_STATE_READY     | 0               |
    |   365     |   104    | DEV_SERDES_10G0_IP4_LN3_RXCLK                                                     | CLK_STATE_READY     | 0               |
    |   365     |   105    | DEV_SERDES_10G0_IP4_LN3_RXFCLK                                                    | CLK_STATE_READY     | 0               |
    |   365     |   106    | DEV_SERDES_10G0_IP4_LN3_TXCLK                                                     | CLK_STATE_NOT_READY | 0               |
    |   365     |   107    | DEV_SERDES_10G0_IP4_LN3_TXFCLK                                                    | CLK_STATE_READY     | 0               |
    |   365     |   108    | DEV_SERDES_10G0_IP4_LN3_TXMCLK                                                    | CLK_STATE_READY     | 0               |
    |   365     |   130    | DEV_SERDES_10G0_TAP_TCK                                                           | CLK_STATE_READY     | 0               |
    |    42     |     0    | DEV_STM0_CORE_CLK                                                                 | CLK_STATE_READY     | 250000000       |
    |    42     |     1    | DEV_STM0_VBUSP_CLK                                                                | CLK_STATE_READY     | 125000000       |
    |    42     |     2    | DEV_STM0_ATB_CLK                                                                  | CLK_STATE_READY     | 250000000       |
    |    63     |     0    | DEV_TIMER0_TIMER_PWM                                                              | CLK_STATE_READY     | 0               |
    |    63     |     1    | DEV_TIMER0_TIMER_TCLK_CLK                                                         | CLK_STATE_READY     | 19200000        |
    |    63     |     2    | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                          | CLK_STATE_READY     | 19200000        |
    |    63     |     3    | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                           | CLK_STATE_READY     | 0               |
    |    63     |     4    | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT8_CLK              | CLK_STATE_READY     | 250000000       |
    |    63     |     5    | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK     | CLK_STATE_READY     | 12500000        |
    |    63     |     6    | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK                | CLK_STATE_READY     | 250000000       |
    |    63     |     7    | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                      | CLK_STATE_READY     | 0               |
    |    63     |     8    | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT                          | CLK_STATE_READY     | 0               |
    |    63     |     9    | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                          | CLK_STATE_READY     | 32768           |
    |    63     |    10    | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT                        | CLK_STATE_READY     | 0               |
    |    63     |    11    | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK                | CLK_STATE_READY     | 192000000       |
    |    63     |    12    | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK              | CLK_STATE_READY     | 225000000       |
    |    63     |    13    | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK                | CLK_STATE_READY     | 196608000       |
    |    63     |    14    | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF2                  | CLK_STATE_READY     | 0               |
    |    63     |    15    | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF3                  | CLK_STATE_READY     | 0               |
    |    63     |    16    | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MAIN_0_CPTS_GENF0                     | CLK_STATE_NOT_READY | 0               |
    |    63     |    18    | DEV_TIMER0_TIMER_HCLK_CLK                                                         | CLK_STATE_READY     | 125000000       |
    |    64     |     1    | DEV_TIMER1_TIMER_TCLK_CLK                                                         | CLK_STATE_READY     | 19200000        |
    |    64     |     2    | DEV_TIMER1_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT1                           | CLK_STATE_READY     | 19200000        |
    |    64     |     3    | DEV_TIMER1_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_0_TIMER_PWM                  | CLK_STATE_READY     | 0               |
    |    64     |    18    | DEV_TIMER1_TIMER_HCLK_CLK                                                         | CLK_STATE_READY     | 125000000       |
    |    73     |     0    | DEV_TIMER10_TIMER_PWM                                                             | CLK_STATE_READY     | 0               |
    |    73     |     1    | DEV_TIMER10_TIMER_TCLK_CLK                                                        | CLK_STATE_READY     | 19200000        |
    |    73     |     2    | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                         | CLK_STATE_READY     | 19200000        |
    |    73     |     3    | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                          | CLK_STATE_READY     | 0               |
    |    73     |     4    | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT8_CLK             | CLK_STATE_READY     | 250000000       |
    |    73     |     5    | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK    | CLK_STATE_READY     | 12500000        |
    |    73     |     6    | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK               | CLK_STATE_READY     | 250000000       |
    |    73     |     7    | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                     | CLK_STATE_READY     | 0               |
    |    73     |     8    | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT                         | CLK_STATE_READY     | 0               |
    |    73     |     9    | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                         | CLK_STATE_READY     | 32768           |
    |    73     |    10    | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT                       | CLK_STATE_READY     | 0               |
    |    73     |    11    | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK               | CLK_STATE_READY     | 192000000       |
    |    73     |    12    | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK             | CLK_STATE_READY     | 225000000       |
    |    73     |    13    | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK               | CLK_STATE_READY     | 196608000       |
    |    73     |    14    | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF2                 | CLK_STATE_READY     | 0               |
    |    73     |    15    | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF3                 | CLK_STATE_READY     | 0               |
    |    73     |    16    | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MAIN_0_CPTS_GENF0                    | CLK_STATE_NOT_READY | 0               |
    |    73     |    18    | DEV_TIMER10_TIMER_HCLK_CLK                                                        | CLK_STATE_READY     | 125000000       |
    |    74     |     1    | DEV_TIMER11_TIMER_TCLK_CLK                                                        | CLK_STATE_READY     | 19200000        |
    |    74     |     2    | DEV_TIMER11_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT11                         | CLK_STATE_READY     | 19200000        |
    |    74     |     3    | DEV_TIMER11_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_10_TIMER_PWM                | CLK_STATE_NOT_READY | 0               |
    |    74     |    18    | DEV_TIMER11_TIMER_HCLK_CLK                                                        | CLK_STATE_READY     | 125000000       |
    |    75     |     0    | DEV_TIMER12_TIMER_PWM                                                             | CLK_STATE_READY     | 0               |
    |    75     |     1    | DEV_TIMER12_TIMER_TCLK_CLK                                                        | CLK_STATE_READY     | 19200000        |
    |    75     |     2    | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                         | CLK_STATE_READY     | 19200000        |
    |    75     |     3    | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                          | CLK_STATE_READY     | 0               |
    |    75     |     4    | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT8_CLK             | CLK_STATE_READY     | 250000000       |
    |    75     |     5    | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK    | CLK_STATE_READY     | 12500000        |
    |    75     |     6    | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK               | CLK_STATE_READY     | 250000000       |
    |    75     |     7    | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                     | CLK_STATE_READY     | 0               |
    |    75     |     8    | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT                         | CLK_STATE_READY     | 0               |
    |    75     |     9    | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                         | CLK_STATE_READY     | 32768           |
    |    75     |    10    | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT                       | CLK_STATE_READY     | 0               |
    |    75     |    11    | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK               | CLK_STATE_READY     | 192000000       |
    |    75     |    12    | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK             | CLK_STATE_READY     | 225000000       |
    |    75     |    13    | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK               | CLK_STATE_READY     | 196608000       |
    |    75     |    14    | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF2                 | CLK_STATE_READY     | 0               |
    |    75     |    15    | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF3                 | CLK_STATE_READY     | 0               |
    |    75     |    16    | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MAIN_0_CPTS_GENF0                    | CLK_STATE_NOT_READY | 0               |
    |    75     |    18    | DEV_TIMER12_TIMER_HCLK_CLK                                                        | CLK_STATE_READY     | 125000000       |
    |    76     |     1    | DEV_TIMER13_TIMER_TCLK_CLK                                                        | CLK_STATE_READY     | 19200000        |
    |    76     |     2    | DEV_TIMER13_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT13                         | CLK_STATE_READY     | 19200000        |
    |    76     |     3    | DEV_TIMER13_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_12_TIMER_PWM                | CLK_STATE_NOT_READY | 0               |
    |    76     |    18    | DEV_TIMER13_TIMER_HCLK_CLK                                                        | CLK_STATE_READY     | 125000000       |
    |    77     |     0    | DEV_TIMER14_TIMER_PWM                                                             | CLK_STATE_READY     | 0               |
    |    77     |     1    | DEV_TIMER14_TIMER_TCLK_CLK                                                        | CLK_STATE_READY     | 19200000        |
    |    77     |     2    | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                         | CLK_STATE_READY     | 19200000        |
    |    77     |     3    | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                          | CLK_STATE_READY     | 0               |
    |    77     |     4    | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT8_CLK             | CLK_STATE_READY     | 250000000       |
    |    77     |     5    | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK    | CLK_STATE_READY     | 12500000        |
    |    77     |     6    | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK               | CLK_STATE_READY     | 250000000       |
    |    77     |     7    | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                     | CLK_STATE_READY     | 0               |
    |    77     |     8    | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT                         | CLK_STATE_READY     | 0               |
    |    77     |     9    | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                         | CLK_STATE_READY     | 32768           |
    |    77     |    10    | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT                       | CLK_STATE_READY     | 0               |
    |    77     |    11    | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK               | CLK_STATE_READY     | 192000000       |
    |    77     |    12    | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK             | CLK_STATE_READY     | 225000000       |
    |    77     |    13    | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK               | CLK_STATE_READY     | 196608000       |
    |    77     |    14    | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF2                 | CLK_STATE_READY     | 0               |
    |    77     |    15    | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF3                 | CLK_STATE_READY     | 0               |
    |    77     |    16    | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MAIN_0_CPTS_GENF0                    | CLK_STATE_NOT_READY | 0               |
    |    77     |    18    | DEV_TIMER14_TIMER_HCLK_CLK                                                        | CLK_STATE_READY     | 125000000       |
    |    78     |     1    | DEV_TIMER15_TIMER_TCLK_CLK                                                        | CLK_STATE_READY     | 19200000        |
    |    78     |     2    | DEV_TIMER15_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT15                         | CLK_STATE_READY     | 19200000        |
    |    78     |     3    | DEV_TIMER15_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_14_TIMER_PWM                | CLK_STATE_NOT_READY | 0               |
    |    78     |    18    | DEV_TIMER15_TIMER_HCLK_CLK                                                        | CLK_STATE_READY     | 125000000       |
    |    79     |     0    | DEV_TIMER16_TIMER_PWM                                                             | CLK_STATE_READY     | 0               |
    |    79     |     1    | DEV_TIMER16_TIMER_TCLK_CLK                                                        | CLK_STATE_READY     | 19200000        |
    |    79     |     2    | DEV_TIMER16_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT16                         | CLK_STATE_READY     | 19200000        |
    |    79     |     3    | DEV_TIMER16_TIMER_TCLK_CLK_PARENT_MAIN_TIMER16_AFS_SEL_OUT0                       | CLK_STATE_READY     | 0               |
    |    79     |    34    | DEV_TIMER16_TIMER_HCLK_CLK                                                        | CLK_STATE_READY     | 125000000       |
    |    80     |     1    | DEV_TIMER17_TIMER_TCLK_CLK                                                        | CLK_STATE_READY     | 19200000        |
    |    80     |     2    | DEV_TIMER17_TIMER_TCLK_CLK_PARENT_MAIN_TIMER17_AFS_EN_OUT0                        | CLK_STATE_READY     | 19200000        |
    |    80     |     3    | DEV_TIMER17_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_16_TIMER_PWM                | CLK_STATE_NOT_READY | 0               |
    |    80     |    34    | DEV_TIMER17_TIMER_HCLK_CLK                                                        | CLK_STATE_READY     | 125000000       |
    |    81     |     0    | DEV_TIMER18_TIMER_PWM                                                             | CLK_STATE_READY     | 0               |
    |    81     |     1    | DEV_TIMER18_TIMER_TCLK_CLK                                                        | CLK_STATE_READY     | 19200000        |
    |    81     |     2    | DEV_TIMER18_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT18                         | CLK_STATE_READY     | 19200000        |
    |    81     |     3    | DEV_TIMER18_TIMER_TCLK_CLK_PARENT_MAIN_TIMER18_AFS_SEL_OUT0                       | CLK_STATE_READY     | 0               |
    |    81     |    34    | DEV_TIMER18_TIMER_HCLK_CLK                                                        | CLK_STATE_READY     | 125000000       |
    |    82     |     1    | DEV_TIMER19_TIMER_TCLK_CLK                                                        | CLK_STATE_READY     | 19200000        |
    |    82     |     2    | DEV_TIMER19_TIMER_TCLK_CLK_PARENT_MAIN_TIMER19_AFS_EN_OUT0                        | CLK_STATE_READY     | 19200000        |
    |    82     |     3    | DEV_TIMER19_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_18_TIMER_PWM                | CLK_STATE_NOT_READY | 0               |
    |    82     |    34    | DEV_TIMER19_TIMER_HCLK_CLK                                                        | CLK_STATE_READY     | 125000000       |
    |    65     |     0    | DEV_TIMER2_TIMER_PWM                                                              | CLK_STATE_READY     | 0               |
    |    65     |     1    | DEV_TIMER2_TIMER_TCLK_CLK                                                         | CLK_STATE_READY     | 19200000        |
    |    65     |     2    | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                          | CLK_STATE_READY     | 19200000        |
    |    65     |     3    | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                           | CLK_STATE_READY     | 0               |
    |    65     |     4    | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT8_CLK              | CLK_STATE_READY     | 250000000       |
    |    65     |     5    | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK     | CLK_STATE_READY     | 12500000        |
    |    65     |     6    | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK                | CLK_STATE_READY     | 250000000       |
    |    65     |     7    | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                      | CLK_STATE_READY     | 0               |
    |    65     |     8    | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT                          | CLK_STATE_READY     | 0               |
    |    65     |     9    | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                          | CLK_STATE_READY     | 32768           |
    |    65     |    10    | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT                        | CLK_STATE_READY     | 0               |
    |    65     |    11    | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK                | CLK_STATE_READY     | 192000000       |
    |    65     |    12    | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK              | CLK_STATE_READY     | 225000000       |
    |    65     |    13    | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK                | CLK_STATE_READY     | 196608000       |
    |    65     |    14    | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF2                  | CLK_STATE_READY     | 0               |
    |    65     |    15    | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF3                  | CLK_STATE_READY     | 0               |
    |    65     |    16    | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MAIN_0_CPTS_GENF0                     | CLK_STATE_NOT_READY | 0               |
    |    65     |    18    | DEV_TIMER2_TIMER_HCLK_CLK                                                         | CLK_STATE_READY     | 125000000       |
    |    66     |     1    | DEV_TIMER3_TIMER_TCLK_CLK                                                         | CLK_STATE_READY     | 19200000        |
    |    66     |     2    | DEV_TIMER3_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT3                           | CLK_STATE_READY     | 19200000        |
    |    66     |     3    | DEV_TIMER3_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_2_TIMER_PWM                  | CLK_STATE_READY     | 0               |
    |    66     |    18    | DEV_TIMER3_TIMER_HCLK_CLK                                                         | CLK_STATE_READY     | 125000000       |
    |    67     |     0    | DEV_TIMER4_TIMER_PWM                                                              | CLK_STATE_READY     | 0               |
    |    67     |     1    | DEV_TIMER4_TIMER_TCLK_CLK                                                         | CLK_STATE_READY     | 19200000        |
    |    67     |     2    | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                          | CLK_STATE_READY     | 19200000        |
    |    67     |     3    | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                           | CLK_STATE_READY     | 0               |
    |    67     |     4    | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT8_CLK              | CLK_STATE_READY     | 250000000       |
    |    67     |     5    | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK     | CLK_STATE_READY     | 12500000        |
    |    67     |     6    | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK                | CLK_STATE_READY     | 250000000       |
    |    67     |     7    | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                      | CLK_STATE_READY     | 0               |
    |    67     |     8    | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT                          | CLK_STATE_READY     | 0               |
    |    67     |     9    | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                          | CLK_STATE_READY     | 32768           |
    |    67     |    10    | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT                        | CLK_STATE_READY     | 0               |
    |    67     |    11    | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK                | CLK_STATE_READY     | 192000000       |
    |    67     |    12    | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK              | CLK_STATE_READY     | 225000000       |
    |    67     |    13    | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK                | CLK_STATE_READY     | 196608000       |
    |    67     |    14    | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF2                  | CLK_STATE_READY     | 0               |
    |    67     |    15    | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF3                  | CLK_STATE_READY     | 0               |
    |    67     |    16    | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MAIN_0_CPTS_GENF0                     | CLK_STATE_NOT_READY | 0               |
    |    67     |    18    | DEV_TIMER4_TIMER_HCLK_CLK                                                         | CLK_STATE_READY     | 125000000       |
    |    68     |     1    | DEV_TIMER5_TIMER_TCLK_CLK                                                         | CLK_STATE_READY     | 19200000        |
    |    68     |     2    | DEV_TIMER5_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT5                           | CLK_STATE_READY     | 19200000        |
    |    68     |     3    | DEV_TIMER5_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_4_TIMER_PWM                  | CLK_STATE_READY     | 0               |
    |    68     |    18    | DEV_TIMER5_TIMER_HCLK_CLK                                                         | CLK_STATE_READY     | 125000000       |
    |    69     |     0    | DEV_TIMER6_TIMER_PWM                                                              | CLK_STATE_READY     | 0               |
    |    69     |     1    | DEV_TIMER6_TIMER_TCLK_CLK                                                         | CLK_STATE_READY     | 19200000        |
    |    69     |     2    | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                          | CLK_STATE_READY     | 19200000        |
    |    69     |     3    | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                           | CLK_STATE_READY     | 0               |
    |    69     |     4    | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT8_CLK              | CLK_STATE_READY     | 250000000       |
    |    69     |     5    | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK     | CLK_STATE_READY     | 12500000        |
    |    69     |     6    | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK                | CLK_STATE_READY     | 250000000       |
    |    69     |     7    | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                      | CLK_STATE_READY     | 0               |
    |    69     |     8    | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT                          | CLK_STATE_READY     | 0               |
    |    69     |     9    | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                          | CLK_STATE_READY     | 32768           |
    |    69     |    10    | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT                        | CLK_STATE_READY     | 0               |
    |    69     |    11    | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK                | CLK_STATE_READY     | 192000000       |
    |    69     |    12    | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK              | CLK_STATE_READY     | 225000000       |
    |    69     |    13    | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK                | CLK_STATE_READY     | 196608000       |
    |    69     |    14    | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF2                  | CLK_STATE_READY     | 0               |
    |    69     |    15    | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF3                  | CLK_STATE_READY     | 0               |
    |    69     |    16    | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MAIN_0_CPTS_GENF0                     | CLK_STATE_NOT_READY | 0               |
    |    69     |    18    | DEV_TIMER6_TIMER_HCLK_CLK                                                         | CLK_STATE_READY     | 125000000       |
    |    70     |     1    | DEV_TIMER7_TIMER_TCLK_CLK                                                         | CLK_STATE_READY     | 19200000        |
    |    70     |     2    | DEV_TIMER7_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT7                           | CLK_STATE_READY     | 19200000        |
    |    70     |     3    | DEV_TIMER7_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_6_TIMER_PWM                  | CLK_STATE_READY     | 0               |
    |    70     |    18    | DEV_TIMER7_TIMER_HCLK_CLK                                                         | CLK_STATE_READY     | 125000000       |
    |    71     |     0    | DEV_TIMER8_TIMER_PWM                                                              | CLK_STATE_READY     | 0               |
    |    71     |     1    | DEV_TIMER8_TIMER_TCLK_CLK                                                         | CLK_STATE_READY     | 19200000        |
    |    71     |     2    | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                          | CLK_STATE_READY     | 19200000        |
    |    71     |     3    | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                           | CLK_STATE_READY     | 0               |
    |    71     |     4    | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT8_CLK              | CLK_STATE_READY     | 250000000       |
    |    71     |     5    | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK     | CLK_STATE_READY     | 12500000        |
    |    71     |     6    | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK                | CLK_STATE_READY     | 250000000       |
    |    71     |     7    | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                      | CLK_STATE_READY     | 0               |
    |    71     |     8    | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT                          | CLK_STATE_READY     | 0               |
    |    71     |     9    | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                          | CLK_STATE_READY     | 32768           |
    |    71     |    10    | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT                        | CLK_STATE_READY     | 0               |
    |    71     |    11    | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK                | CLK_STATE_READY     | 192000000       |
    |    71     |    12    | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK              | CLK_STATE_READY     | 225000000       |
    |    71     |    13    | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK                | CLK_STATE_READY     | 196608000       |
    |    71     |    14    | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF2                  | CLK_STATE_READY     | 0               |
    |    71     |    15    | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF3                  | CLK_STATE_READY     | 0               |
    |    71     |    16    | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MAIN_0_CPTS_GENF0                     | CLK_STATE_NOT_READY | 0               |
    |    71     |    18    | DEV_TIMER8_TIMER_HCLK_CLK                                                         | CLK_STATE_READY     | 125000000       |
    |    72     |     1    | DEV_TIMER9_TIMER_TCLK_CLK                                                         | CLK_STATE_READY     | 19200000        |
    |    72     |     2    | DEV_TIMER9_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT9                           | CLK_STATE_READY     | 19200000        |
    |    72     |     3    | DEV_TIMER9_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_8_TIMER_PWM                  | CLK_STATE_NOT_READY | 0               |
    |    72     |    18    | DEV_TIMER9_TIMER_HCLK_CLK                                                         | CLK_STATE_READY     | 125000000       |
    |   124     |     0    | DEV_TIMESYNC_INTRTR0_INTR_CLK                                                     | CLK_STATE_READY     | 125000000       |
    |   146     |     2    | DEV_UART0_VBUSP_CLK                                                               | CLK_STATE_READY     | 125000000       |
    |   146     |     3    | DEV_UART0_FCLK_CLK                                                                | CLK_STATE_READY     | 48000000        |
    |   350     |     2    | DEV_UART1_VBUSP_CLK                                                               | CLK_STATE_READY     | 125000000       |
    |   350     |     3    | DEV_UART1_FCLK_CLK                                                                | CLK_STATE_READY     | 48000000        |
    |   351     |     2    | DEV_UART2_VBUSP_CLK                                                               | CLK_STATE_READY     | 125000000       |
    |   351     |     3    | DEV_UART2_FCLK_CLK                                                                | CLK_STATE_READY     | 48000000        |
    |   352     |     2    | DEV_UART3_VBUSP_CLK                                                               | CLK_STATE_READY     | 125000000       |
    |   352     |     3    | DEV_UART3_FCLK_CLK                                                                | CLK_STATE_READY     | 48000000        |
    |   353     |     2    | DEV_UART4_VBUSP_CLK                                                               | CLK_STATE_READY     | 125000000       |
    |   353     |     3    | DEV_UART4_FCLK_CLK                                                                | CLK_STATE_READY     | 48000000        |
    |   354     |     2    | DEV_UART5_VBUSP_CLK                                                               | CLK_STATE_READY     | 125000000       |
    |   354     |     3    | DEV_UART5_FCLK_CLK                                                                | CLK_STATE_READY     | 48000000        |
    |   355     |     2    | DEV_UART6_VBUSP_CLK                                                               | CLK_STATE_READY     | 125000000       |
    |   355     |     3    | DEV_UART6_FCLK_CLK                                                                | CLK_STATE_READY     | 48000000        |
    |   356     |     2    | DEV_UART7_VBUSP_CLK                                                               | CLK_STATE_READY     | 125000000       |
    |   356     |     3    | DEV_UART7_FCLK_CLK                                                                | CLK_STATE_READY     | 48000000        |
    |   357     |     2    | DEV_UART8_VBUSP_CLK                                                               | CLK_STATE_READY     | 125000000       |
    |   357     |     3    | DEV_UART8_FCLK_CLK                                                                | CLK_STATE_READY     | 48000000        |
    |   358     |     2    | DEV_UART9_VBUSP_CLK                                                               | CLK_STATE_READY     | 125000000       |
    |   358     |     3    | DEV_UART9_FCLK_CLK                                                                | CLK_STATE_READY     | 48000000        |
    |   360     |     1    | DEV_USB0_PIPE_RXFCLK                                                              | CLK_STATE_READY     | 0               |
    |   360     |     2    | DEV_USB0_PIPE_RXFCLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP3_LN3_RXFCLK                    | CLK_STATE_READY     | 0               |
    |   360     |     3    | DEV_USB0_PIPE_RXFCLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP3_LN1_RXFCLK                    | CLK_STATE_READY     | 0               |
    |   360     |     4    | DEV_USB0_USB2_APB_PCLK_CLK                                                        | CLK_STATE_READY     | 125000000       |
    |   360     |     5    | DEV_USB0_PIPE_TXCLK                                                               | CLK_STATE_READY     | 0               |
    |   360     |     7    | DEV_USB0_PIPE_TXFCLK                                                              | CLK_STATE_READY     | 0               |
    |   360     |     8    | DEV_USB0_PIPE_TXFCLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP3_LN3_TXFCLK                    | CLK_STATE_READY     | 0               |
    |   360     |     9    | DEV_USB0_PIPE_TXFCLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP3_LN1_TXFCLK                    | CLK_STATE_READY     | 0               |
    |   360     |    10    | DEV_USB0_PIPE_REFCLK                                                              | CLK_STATE_READY     | 0               |
    |   360     |    11    | DEV_USB0_PIPE_REFCLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP3_LN3_REFCLK                    | CLK_STATE_READY     | 0               |
    |   360     |    12    | DEV_USB0_PIPE_REFCLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP3_LN1_REFCLK                    | CLK_STATE_READY     | 0               |
    |   360     |    13    | DEV_USB0_PCLK_CLK                                                                 | CLK_STATE_READY     | 125000000       |
    |   360     |    15    | DEV_USB0_CLK_LPM_CLK                                                              | CLK_STATE_READY     | 24000000        |
    |   360     |    16    | DEV_USB0_USB2_REFCLOCK_CLK                                                        | CLK_STATE_READY     | 19200000        |
    |   360     |    17    | DEV_USB0_USB2_REFCLOCK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                         | CLK_STATE_READY     | 19200000        |
    |   360     |    18    | DEV_USB0_USB2_REFCLOCK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                          | CLK_STATE_READY     | 0               |
    |   360     |    19    | DEV_USB0_PIPE_RXCLK                                                               | CLK_STATE_READY     | 0               |
    |   360     |    20    | DEV_USB0_PIPE_RXCLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP3_LN3_RXCLK                      | CLK_STATE_READY     | 0               |
    |   360     |    21    | DEV_USB0_PIPE_RXCLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP3_LN1_RXCLK                      | CLK_STATE_READY     | 0               |
    |   360     |    22    | DEV_USB0_ACLK_CLK                                                                 | CLK_STATE_READY     | 500000000       |
    |   360     |    23    | DEV_USB0_BUF_CLK                                                                  | CLK_STATE_READY     | 250000000       |
    |   360     |    25    | DEV_USB0_USB2_TAP_TCK                                                             | CLK_STATE_READY     | 0               |
    |   360     |    26    | DEV_USB0_PIPE_TXMCLK                                                              | CLK_STATE_READY     | 0               |
    |   360     |    27    | DEV_USB0_PIPE_TXMCLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP3_LN3_TXMCLK                    | CLK_STATE_READY     | 0               |
    |   360     |    28    | DEV_USB0_PIPE_TXMCLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP3_LN1_TXMCLK                    | CLK_STATE_READY     | 0               |
    |   361     |     0    | DEV_VPAC0_LDC0_CLK_CLK                                                            | CLK_STATE_READY     | 720000000       |
    |   361     |     1    | DEV_VPAC0_NF_CLK_CLK                                                              | CLK_STATE_READY     | 720000000       |
    |   361     |     2    | DEV_VPAC0_MAIN_CLK                                                                | CLK_STATE_READY     | 720000000       |
    |   361     |     3    | DEV_VPAC0_MAIN_CLK_PARENT_HSDIV1_16FFT_MAIN_25_HSDIVOUT1_CLK                      | CLK_STATE_READY     | 720000000       |
    |   361     |     4    | DEV_VPAC0_MAIN_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK                       | CLK_STATE_READY     | 600000000       |
    |   361     |     5    | DEV_VPAC0_VISS0_CLK_CLK                                                           | CLK_STATE_READY     | 720000000       |
    |   361     |     6    | DEV_VPAC0_PSIL_LEAF_CLK                                                           | CLK_STATE_READY     | 500000000       |
    |   361     |     7    | DEV_VPAC0_MSC_CLK                                                                 | CLK_STATE_READY     | 720000000       |
    |   362     |     0    | DEV_VUSR_DUAL0_V0_RXFL_CLK                                                        | CLK_STATE_READY     | 0               |
    |   362     |     1    | DEV_VUSR_DUAL0_VUSRX_LN0_TXFCLK                                                   | CLK_STATE_READY     | 0               |
    |   362     |     2    | DEV_VUSR_DUAL0_V0_CLK                                                             | CLK_STATE_READY     | 500000000       |
    |   362     |     3    | DEV_VUSR_DUAL0_V1_TXPM_CLK                                                        | CLK_STATE_READY     | 0               |
    |   362     |     4    | DEV_VUSR_DUAL0_VUSRX_LN1_TXMCLK                                                   | CLK_STATE_READY     | 0               |
    |   362     |     5    | DEV_VUSR_DUAL0_V1_TXFL_CLK                                                        | CLK_STATE_READY     | 0               |
    |   362     |     6    | DEV_VUSR_DUAL0_VUSRX_LN0_RXCLK                                                    | CLK_STATE_READY     | 0               |
    |   362     |     7    | DEV_VUSR_DUAL0_VUSRX_LN2_RXFCLK                                                   | CLK_STATE_READY     | 0               |
    |   362     |     8    | DEV_VUSR_DUAL0_VUSRX_LN2_REFCLK                                                   | CLK_STATE_READY     | 0               |
    |   362     |     9    | DEV_VUSR_DUAL0_VUSRX_LN3_RXCLK                                                    | CLK_STATE_READY     | 0               |
    |   362     |    10    | DEV_VUSR_DUAL0_VUSRX_LN1_RXFCLK                                                   | CLK_STATE_READY     | 0               |
    |   362     |    11    | DEV_VUSR_DUAL0_VUSRX_LN0_REFCLK                                                   | CLK_STATE_READY     | 0               |
    |   362     |    12    | DEV_VUSR_DUAL0_VUSRX_LN1_TXCLK                                                    | CLK_STATE_READY     | 0               |
    |   362     |    13    | DEV_VUSR_DUAL0_VUSRX_LN3_RXFCLK                                                   | CLK_STATE_READY     | 0               |
    |   362     |    14    | DEV_VUSR_DUAL0_VUSRX_LN3_TXCLK                                                    | CLK_STATE_READY     | 0               |
    |   362     |    15    | DEV_VUSR_DUAL0_VUSRX_LN3_TXMCLK                                                   | CLK_STATE_READY     | 0               |
    |   362     |    16    | DEV_VUSR_DUAL0_VUSRX_LN3_TXFCLK                                                   | CLK_STATE_READY     | 0               |
    |   362     |    17    | DEV_VUSR_DUAL0_VUSRX_LN0_TXCLK                                                    | CLK_STATE_READY     | 0               |
    |   362     |    18    | DEV_VUSR_DUAL0_V1_CLK                                                             | CLK_STATE_READY     | 500000000       |
    |   362     |    19    | DEV_VUSR_DUAL0_V0_TXFL_CLK                                                        | CLK_STATE_READY     | 0               |
    |   362     |    20    | DEV_VUSR_DUAL0_VUSRX_LN0_RXFCLK                                                   | CLK_STATE_READY     | 0               |
    |   362     |    21    | DEV_VUSR_DUAL0_VUSRX_LN2_RXCLK                                                    | CLK_STATE_READY     | 0               |
    |   362     |    22    | DEV_VUSR_DUAL0_V0_TXPM_CLK                                                        | CLK_STATE_READY     | 0               |
    |   362     |    23    | DEV_VUSR_DUAL0_V0_RXPM_CLK                                                        | CLK_STATE_READY     | 0               |
    |   362     |    24    | DEV_VUSR_DUAL0_VUSRX_LN1_REFCLK                                                   | CLK_STATE_READY     | 0               |
    |   362     |    25    | DEV_VUSR_DUAL0_V1_RXPM_CLK                                                        | CLK_STATE_READY     | 0               |
    |   362     |    26    | DEV_VUSR_DUAL0_V1_RXFL_CLK                                                        | CLK_STATE_READY     | 0               |
    |   362     |    27    | DEV_VUSR_DUAL0_VUSRX_LN2_TXCLK                                                    | CLK_STATE_READY     | 0               |
    |   362     |    28    | DEV_VUSR_DUAL0_VUSRX_LN2_TXFCLK                                                   | CLK_STATE_READY     | 0               |
    |   362     |    29    | DEV_VUSR_DUAL0_VUSRX_LN0_TXMCLK                                                   | CLK_STATE_READY     | 0               |
    |   362     |    30    | DEV_VUSR_DUAL0_VUSRX_LN2_TXMCLK                                                   | CLK_STATE_READY     | 0               |
    |   362     |    31    | DEV_VUSR_DUAL0_VUSRX_LN1_TXFCLK                                                   | CLK_STATE_READY     | 0               |
    |   362     |    32    | DEV_VUSR_DUAL0_VUSRX_LN3_REFCLK                                                   | CLK_STATE_READY     | 0               |
    |   362     |    33    | DEV_VUSR_DUAL0_VUSRX_LN1_RXCLK                                                    | CLK_STATE_READY     | 0               |
    |   151     |     0    | DEV_WKUP_DDPA0_DDPA_CLK                                                           | CLK_STATE_READY     | 166666666       |
    |   104     |     0    | DEV_WKUP_ESM0_CLK                                                                 | CLK_STATE_READY     | 166666666       |
    |   115     |     0    | DEV_WKUP_GPIO0_MMR_CLK                                                            | CLK_STATE_READY     | 27777777        |
    |   116     |     0    | DEV_WKUP_GPIO1_MMR_CLK                                                            | CLK_STATE_READY     | 27777777        |
    |   125     |     0    | DEV_WKUP_GPIOMUX_INTRTR0_INTR_CLK                                                 | CLK_STATE_READY     | 166666666       |
    |   304     |     0    | DEV_WKUP_HSM0_DAP_CLK                                                             | CLK_STATE_READY     | 1000000000      |
    |   223     |     0    | DEV_WKUP_I2C0_PORSCL                                                              | CLK_STATE_READY     | 0               |
    |   223     |     1    | DEV_WKUP_I2C0_PISYS_CLK                                                           | CLK_STATE_READY     | 96000000        |
    |   223     |     2    | DEV_WKUP_I2C0_PISYS_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT3_CLK                   | CLK_STATE_READY     | 96000000        |
    |   223     |     3    | DEV_WKUP_I2C0_PISYS_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                            | CLK_STATE_READY     | 19200000        |
    |   223     |     4    | DEV_WKUP_I2C0_CLK                                                                 | CLK_STATE_READY     | 166666666       |
    |   223     |     5    | DEV_WKUP_I2C0_PISCL                                                               | CLK_STATE_READY     | 0               |
    |   147     |     0    | DEV_WKUP_J7AM_WAKEUP_16FF0_PLL_CTRL_WKUP_CLK24_CLK                                | CLK_STATE_READY     | 1000000000      |
    |   147     |     1    | DEV_WKUP_J7AM_WAKEUP_16FF0_WKUP_RCOSC_12P5M_CLK                                   | CLK_STATE_READY     | 12500000        |
    |   147     |     2    | DEV_WKUP_J7AM_WAKEUP_16FF0_WKUP_RCOSC_32K_CLK                                     | CLK_STATE_READY     | 32000           |
    |   123     |     0    | DEV_WKUP_PORZ_SYNC0_CLK_12M_RC_CLK                                                | CLK_STATE_READY     | 12500000        |
    |   126     |     0    | DEV_WKUP_PSC0_SLOW_CLK                                                            | CLK_STATE_READY     | 41666666        |
    |   126     |     1    | DEV_WKUP_PSC0_CLK                                                                 | CLK_STATE_READY     | 166666666       |
    |   359     |     2    | DEV_WKUP_UART0_VBUSP_CLK                                                          | CLK_STATE_READY     | 166666666       |
    |   359     |     3    | DEV_WKUP_UART0_FCLK_CLK                                                           | CLK_STATE_READY     | 96000000        |
    |   359     |     4    | DEV_WKUP_UART0_FCLK_CLK_PARENT_WKUP_USART_CLKSEL_OUT0                             | CLK_STATE_READY     | 96000000        |
    |   359     |     5    | DEV_WKUP_UART0_FCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                            | CLK_STATE_READY     | 19200000        |
    |   180     |     0    | DEV_WKUP_VTM0_FIX_REF_CLK                                                         | CLK_STATE_READY     | 19200000        |
    |   180     |     1    | DEV_WKUP_VTM0_FIX_REF2_CLK                                                        | CLK_STATE_READY     | 12500000        |
    |   180     |     2    | DEV_WKUP_VTM0_VBUSP_CLK                                                           | CLK_STATE_READY     | 166666666       |
    |--------------------------------------------------------------------------------------------------------------------------------------------------|
    
    

    As for clock assignments, each video port can be routed to 1 or 2 different interfaces, so there is some flexibility. Default devicetree assumes the connections used in SK board. 

    Can you elaborate on this a little more? We just copied this from the SK-am68 evm device tree and not sure if it's correct for us. I've taken it out and put it back in and haven't noticed a difference. In our case, MIPI is directly connected to the panel. There is no bridge or anything in between.

    Thank you!

  • Hi Amandio,

    In TRM section 5.5.10.3, each VP can go to two different interfaces as shown below:

    However, DSI0 can only be reached through the third VP, so what is in the default TI devicetree should work for your custom board as well.

    As for timing, I get 1364*635*60/1000=51968.4 (kHz) instead of 51206 (kHz). Could you try adjusting the pixel clock?

    Regards,

    Takuma

  • Hi Takuma,

    Thanks for your help. I had a typo in the timings in my previous post. The clock should be 51206, I entered the wrong timing values which caused that arithmetic error on my part.

    We got the display working now. The final issue was a hardware problem on our LCD board which was causing the LCD supply rails to come up at the wrong time according to the power on sequence in the datasheet. Once we modified the board to fix this, the panel started working perfectly.

    I still have some questions about how the clocking works and the device tree relating to DSI, but I'll post those in their own threads.

    Thank you for your help and time!

  • Hi Amandio,

    Awesome to hear that the LCD is working!

    Regards,

    Takuma