DRA821U: How to use CPSWng with u-boot

Tool/software:

Hi Team,

We have designed a custom board based on the J7200XSOMXEVM reference design.

We are developing the software for the custom board with PROCESSOR-SDK-LINUX-RT-J7200 (10.00.07.03).

The custom board uses three Ethernet ports: CPSW2g (MCU-RMII1) and CPSWng (RGMII2, RGMII3).

We want to use RGMII2 in u-boot to boot via NFS via TFTP, but RGMII2 is not recognized.

The CPSWng related settings in the device tree are written below.

	ethernet1_pins_default: ethernet1-default-pins {
		pinctrl-single,pins = <
			J721E_IOPAD(0x4c, PIN_INPUT, 4) /* (V19) MCAN5_RX.RGMII3_RD0 */
			J721E_IOPAD(0x50, PIN_INPUT, 4) /* (T13) MCAN6_TX.RGMII3_RD1 */
			J721E_IOPAD(0x54, PIN_INPUT, 4) /* (U14) MCAN6_RX.RGMII3_RD2 */
			J721E_IOPAD(0x58, PIN_INPUT, 4) /* (U16) MCAN7_TX.RGMII3_RD3 */
			J721E_IOPAD(0x48, PIN_INPUT, 4) /* (V21) MCAN5_TX.RGMII3_RXC */
			J721E_IOPAD(0x5c, PIN_INPUT, 4) /* (U15) MCAN7_RX.RGMII3_RX_CTL */
			J721E_IOPAD(0x60, PIN_OUTPUT, 4) /* (T15) MCAN8_TX.RGMII3_TD0 */
			J721E_IOPAD(0x64, PIN_OUTPUT, 4) /* (U19) MCAN8_RX.RGMII3_TD1 */
			J721E_IOPAD(0x68, PIN_OUTPUT, 4) /* (T14) MCAN9_TX.RGMII3_TD2 */
			J721E_IOPAD(0x6c, PIN_OUTPUT, 4) /* (U18) MCAN9_RX.RGMII3_TD3 */
			J721E_IOPAD(0x74, PIN_OUTPUT, 4) /* (U20) MCAN10_RX.RGMII3_TXC */
			J721E_IOPAD(0x70, PIN_OUTPUT, 4) /* (U17) MCAN10_TX.RGMII3_TX_CTL */
		>;
	};

	ethernet0_pins_default: ethernet0-default-pins {
		pinctrl-single,pins = <
			J721E_IOPAD(0x7c, PIN_INPUT, 4) /* (Y13) MCAN11_RX.RGMII2_RD0 */
			J721E_IOPAD(0x80, PIN_INPUT, 4) /* (AA15) MCAN12_TX.RGMII2_RD1 */
			J721E_IOPAD(0x84, PIN_INPUT, 4) /* (AA14) MCAN12_RX.RGMII2_RD2 */
			J721E_IOPAD(0x88, PIN_INPUT, 4) /* (AA18) MCAN13_TX.RGMII2_RD3 */
			J721E_IOPAD(0x78, PIN_INPUT, 4) /* (Y14) MCAN11_TX.RGMII2_RXC */
			J721E_IOPAD(0x8c, PIN_INPUT, 4) /* (AA16) MCAN13_RX.RGMII2_RX_CTL */
			J721E_IOPAD(0x90, PIN_OUTPUT, 4) /* (W17) MCAN15_TX.RGMII2_TD0 */
			J721E_IOPAD(0x94, PIN_OUTPUT, 4) /* (W20) MCAN15_RX.RGMII2_TD1 */
			J721E_IOPAD(0x98, PIN_OUTPUT, 4) /* (V14) UART2_RXD.RGMII2_TD2 */
			J721E_IOPAD(0x9c, PIN_OUTPUT, 4) /* (V13) UART2_TXD.RGMII2_TD3 */
			J721E_IOPAD(0x28, PIN_OUTPUT, 4) /* (W21) MCAN1_TX.RGMII2_TXC */
			J721E_IOPAD(0xa0, PIN_OUTPUT, 4) /* (U12) GPIO0_41.RGMII2_TX_CTL */
		>;
	};

	dp83867_mdio_pins_default: dp83867-mdio-default-pins {
		pinctrl-single,pins = <
			J721E_IOPAD(0xa8, PIN_OUTPUT, 5) /* (W19) UART8_TXD.MDIO0_MDC */
			J721E_IOPAD(0xa4, PIN_INPUT, 5) /* (W14) UART8_RXD.MDIO0_MDIO */
		>;
	};

	&cpsw0 {
		status = "okay";
		pinctrl-names = "default";
		pinctrl-0 = <&ethernet0_pins_default>, <&ethernet1_pins_default>;
	};

	&cpsw0_port2 {
		status = "okay";
		phy-mode = "rgmii-rxid";
		phy-handle = <&cpsw5g_phy0>;
	};

	&cpsw0_port3 {
		status = "okay";
		phy-mode = "rgmii-rxid";
	};

	&cpsw5g_mdio {
		status = "okay";
		pinctrl-names = "default";
		pinctrl-0 = <&dp83867_mdio_pins_default>;

		cpsw5g_phy0: ethernet0-phy@0 {
			reg = <0>;
			ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
			ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
			ti,min-output-impedance;
		};
	};

The cpsw driver included in u-boot (ti-u-boot-2024.04+git/drivers/net/ti/am65-cpsw-nuss.c) does not contain any description of "ti,j721e-cpswxg-nuss", but is it possible to use CPSWng with u-boot?

If possible, could you tell me how to set it up?

Regards,

mizutani