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AM6442: USB 3.0 Differential Impedance and Polarity Reversal

TK0312
Prodigy 40 points
Part Number: AM6442
Other Parts Discussed in Thread: AM6412, AM6422, AM2434, HD3SS3220

Tool/software:

Hello,

I am designing a board using the AM6442 to support USB 3.0 with a USB Type-C connector.

For many devices, it is appropriate to set the differential impedance for SSTX and SSRX to 90Ω. However, the "High-Speed Interface Layout Guidelines" specify 95Ω for the AM6442, while some other devices specify 90Ω. Does this mean that a board designed with 90Ω impedance will not work? What is the reason for specifying 95Ω instead of 90Ω?

Additionally, the following document specifies checking the polarity of USB 3.0 signals: "AM6442, AM6422, AM6412 and AM2434 Processor Schematic Design Guidelines and Schematic Review Checklist."

Various guides and the HD3SS3220 datasheet indicate that reversing the polarity of SSTX and SSRX is acceptable. Does this mean that while many devices allow polarity reversal, the AM6442 requires correct polarity connections?

Example:
Connecting the SSRXP pin of the USB Type-C connector to the SSRXN signal and the SSRXN pin to the SSRXP signal.
Is this acceptable?

Thank you for your assistance.

Best regards,
TK0312

  • +1
    TI__Guru**** 197579 points

    Hello TK0312

    Please refer to the TRM.

    The SERDES0 seems to support polarity reversal. 

    12.2.3.1.1 SerDes Features
    The SERDES module features include:
    • Single lane PHY containing:
    – Transmit and Receive I/Os

    Serializer
    – Deserializer
    – Clock and data recovery (CDR) unit
    • Common Module (CMN)
    – PLLs
    – Controller bias
    – Automatic calibration of pin termination resistors
    – Reference clock input buffers
    – Reset and startup management
    • Physical Coding Sub-block (PCS)
    – USB3.1 Gen 1 (5 Gbps)
    •
    – PCIe Gen 1 (2.5 Gbps), Gen 2 (5 Gbps)
    – QSGMII Specification revision 1.2
    – Symbol alignment
    – Selectable serial pin polarity reversal for both transmit and receive paths
    – Bit stream reordering
    • Physical Media Attachment (PMA) layer
    – Transmit equalization
    – Receive equalization
    – Supports on-the-fly eye and bathtub curve diagramming with 8-bit voltage amplitude resolution and up to
    1/64 UI time resolution
    – Data path BIST with programmable pattern generation and error detection
    – Serial bit stream and parallel word loopback for both line and parallel side
    – 8-bit ADC provides digitized ATB measurement results
    – Supports DC and AC JTAG (boundary scan) per IEEE 1149.6

    I am checking with the team internally and will update you.

    Regards,

    Sreenivasa

  • 0 in reply to Kallikuppa Sreenivasa
    Prodigy 40 points

    Hello Sreenivasa,

    Thank you for your response. I understand now that the checklist's instruction means to "verify the polarity reversal as well."

    Schematic Review
    Follow the below list for the custom schematic design:
    1. Connection of the USB3.0 interface signals including polarity
    2. Connection of the USB2.0 interface signals
    3. Connection of SERDES0_REXT resistor including value and tolerance
    4. Connection of the required filters and decoupling capacitors (Follow the EVM implementation)
    5. Clock termination and connections
    6. Provision for AC coupling capacitors as per recommendation

    Additionally, I noticed that my previous question regarding the difference between 95Ω and 90Ω differential impedance was not addressed. Could you please provide more information on this?

    Thank you for your assistance.

    Best regards,

    TK0312

  • 0 in reply to TK0312
    TI__Guru**** 197579 points

    Hello TK0312

    Thank you. 

    Please refer below:

    We recommended 95 +/-5% because it was a common value that could be used for PCIe, SSUSB, and other interfaces (SGMII) since this limit falls within the limits of all three.

     Sitara High speed

    https://www.ti.com/lit/an/spraar7j/spraar7j.pdf

    Table A-6. AM64x

    TK0312 said:
    For many devices, it is appropriate to set the differential impedance for SSTX and SSRX to 90Ω. However, the "High-Speed Interface Layout Guidelines" specify 95Ω for the AM6442, while some other devices specify 90Ω. Does this mean that a board designed with 90Ω impedance will not work? What is the reason for specifying 95Ω instead of 90Ω?

    The below could help.

     Jacinto

    https://www.ti.com/lit/an/spracp4a/spracp4a.pdf

    Table 3-3. USB3.1 (Super Speed) Routing Specifications

    Regards,

    Sreenivasa

  • 0 in reply to Kallikuppa Sreenivasa
    Prodigy 40 points

    Hello Sreenivasa,

    Thank you for your response.

    I understand that the 95Ω +/-5% specification for the AM6442 is to support PCIe, SSUSB, and SGMII interfaces, as this value falls within the limits for all three. I assume this is because the SERDES PHY is designed for 95Ω.

    Does this mean that designing the board with 95Ω is the correct approach when using the AM6442? Will there be any issues arising from the difference with the USB 3.0 Specification of 90Ω?

    Thank you for your assistance.

    Best regards,

    TK0312

  • +1 in reply to TK0312
    TI__Guru**** 197579 points

    Hello TK0312

    Thank you. 

    TK0312 said:
    Does this mean that designing the board with 95Ω is the correct approach when using the AM6442?

    I would recommend following the sitara high speed design since the implementation would have gone through all the tests.

    TK0312 said:
    Will there be any issues arising from the difference with the USB 3.0 Specification of 90Ω?

    As mentioned above,  the implementation would have gone through all the tests. This should not be a concern.

    Additionally please read the below note in the SOC data sheet. The USB3 interface is compliant to standards.

    7.7.9 SerDes PHY Electrical Characteristics
    Note
    The PCIe interface is compliant with the electrical parameters specified in PCI Express® Base
    Specification Revision 4.0, February 19, 2014.
    Note
    USB0 instance is compliant with the USB3.1 SuperSpeed Transmitter and Receiver Normative
    Electrical Parameters as defined in the Universal Serial Bus 3.1 Specification, Revision 1.0 , July
    26, 2013.

    Regards,

    Sreenivasa

  • 0 in reply to Kallikuppa Sreenivasa
    Prodigy 40 points

    Hello Sreenivasa,

    Thank you very much for your detailed response. All my questions have been fully answered, and I now have a clear understanding of the design requirements.

    I appreciate your assistance and the valuable information you provided.

    Best regards,

    TK0312

  • +1 in reply to TK0312
    TI__Guru**** 197579 points

    Hello TK0312

    Thank you for the note. Appreciated.

    Regards,

    Sreenivasa