DRA829V: PCIe BAR Aperture of Register PCIE_CORE_RP_I_RC_BAR_CONFIG_REG for inbound transactions

Jakob Bleickert

Part Number: DRA829V

Tool/software:

Dear TI team,

Referring to register field RCBAR0A the Root Complex BAR aperture can be configured with a size of 4 bytes and 8 bytes (DRA829TDA4VM_Registers_Part4).
The configured aperture represents the corresponding mask that is applied to PCIE_CORE_RP_I_RC_BAR_0 register, where bits 3-0 are always not writable.

Consequently, I would expect 32-bit BARs to have apertures between 2 GB (2^31 bytes) and 16 B (2^4 bytes) with 31 and 4 not writable bits respectively.
How are apertures of 4 bytes and 8 bytes possible?

Thanks a lot for your help.

Best regards,
Jakob

1 month ago

0 Takuma Fujiwara 1 month ago

TI__Mastermind 40073 points

Hi Jakob,

I will need to check on this one as I do not have the answer off the top of my head and I am currently on travel. However, is there a usecase for RC BAR aperture of size 4 and 8 bytes? If I remember, our Linux driver sets BAR aperture mask to 0xF.

Regards,

Takuma

0 Jakob Bleickert 1 month ago in reply to Takuma Fujiwara

Prodigy 80 points

Hi Takuma,

Thank you for the answer. A BAR aperture of 0xF would correspond to my understanding that a minimum 16-byte alignment must be preserved.
This use case of smaller BAR apertures is not yet relevant for me, I just want to make sure that I understand and use these registers correctly.

Best regards,
Jakob

+1 Takuma Fujiwara 1 month ago in reply to Jakob Bleickert

TI__Mastermind 40073 points

Hi Jakob,

At least for EP, there is a minimum aperture of 128 bytes set in software in the Linux driver from Cadence, the IP provider: https://git.ti.com/cgit/ti-linux-kernel/ti-linux-kernel/tree/drivers/pci/controller/cadence/pcie-cadence-ep.c?h=ti-linux-6.1.y#n16. I would recommend the same to be done if you are not using the Cadence driver.

For RC, the register that I think you are referring to is set in cdns_pcie_host_bar_ib_config: https://git.ti.com/cgit/ti-linux-kernel/ti-linux-kernel/tree/drivers/pci/controller/cadence/pcie-cadence-host.c?h=ti-linux-6.1.y#n229. For RC, we do not have any soft minimum value set, only maximum.

The 4~8 bytes is most likely for legacy devices that use I/O BARs as they need only the two LSBs for type indication, unlike memory space that require 4 bits. As such, for legacy devices using I/O BARs the smallest aperture would be 4 bytes instead of 16 bytes.

Regards,

Takuma

Processors

Processors forum

DRA829V: PCIe BAR Aperture of Register PCIE_CORE_RP_I_RC_BAR_CONFIG_REG for inbound transactions