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Cache Registers Access Problem

Hello All

I am using the  TMS320C6413-500 DSP and I am unable to read the contens of address 0x01840000 correctly.

In my system, I have the DSP configured as slave, and I can check the contents of the cache registers in a terminal window that comunicates with my main processor that is connected to the DSP using the HPI interface.

When I try to read any address inside the L2 Registers memory zone, I am always reading random values, and not the contents of the registers.

I use all the other registers with no problems, but for the cache registers I am missing something and I am unable to access them.

Probably I am missing some initialization?

My system only use L2 SRAM and I do not have external ROM or RAM.

My main problem is not the cache configuration itself, it is related with the SRAM memory contents after warm reseting.

After warm reset, some zones of my memory are cleared and I believe this could be related with L1D chache since the system only have L2 SRAM and no L2 Cache.

The idea is to maintain the contents of the memory, after warm reset, the simply way possible.

The code execute a sync loop of 2uS, but the code itself does not take more than 1.6uS to execute, so I have same time to writeback L1D cache if necessary.

If I read one selected zone of memory before warm reset, after reset the contents are ok, but if I do not refresh the reading of this zone of memory, I have some areas filled with 0x00

Any help will be very appreciated

best regards

Nuno Pereira