Other Parts Discussed in Thread: INA209, ADC084S021, TPS65090, DP83869, TPS65912, TPS65910, ADS7950, LM95241, AFE4404, LM95245, ADC108S102, INA238, TMP006, LM63, LMP91000, AMC6821, TLC4541, LMK04832, ADS8688, DAC5571, HDC2010, TMP401, TMP464, CDCE925, TPS65218, DAC7612, TPS65217, ADS131E08, DRV2665, DRV2667, TMP513, DAC082S085, ADS7828, TPS65010, LP3972, LP3971, TMP117, ADC128S052, TPS23861, ADS1015, INA3221, LM83, TPS62360, LM80, LM87, TPS65219, TPS65086, DP83TC811, TPS65023, LP3943, LM95234, DAC7311, CDCE706, OPT3001, LM77, LM70, LM73, ADS8344, PCF8574, ADS7871, TSC2046, LM3533, TMP108, TWL6040, AFE4403, TMP102, TMP103, ADC128D818, ADS124S08, TMP421, TMP007, ADC161S626, TPIC2810, TPS51632, TPS65132, LM92, LM93, LM90
Tool/software:
Hello,
I am trying to boot Linux Kernel 6.1.y on 66AK2G12 device but it crashes on rootfs mounting.
I use Uboot to load FIT image (kernel, initramfs, DTB) from flash and to boot it.
When kernel boots, I get kernel panic:
Kernel panic - not syncing: VFS: Unable to mount root fs on unknown-block(0,0)
At the beginning of kernel log there is this message:
INITRD: 0x8eb7a000+0x01486000 is not a memory region - disabling initrd
Uboot loads ramdisk to 0x8eb7a000 - 0x8ffff2b8 and passes ramdisk location and its size to kernel via DTB in chosen node.
I don't understand why kernel complains. I used to use kernel 4.19.y (git.ti.com/.../ and I did not experience any issues. However when I migrated to 6.1.y version it started failing to boot even though I did not make any changes in Uboot.
Is the issue somehow related to 32-bit/36-bit addressing on K2G device?
Is K2G really supported in Linux 6.1.y?
Regarding the Uboot, there is initrd fixup logic. Can you explain how this supposed to work? The fixup logic was disabled when I used to use kernel 4.19.y and it booted fine. When I turn it on when using 6.1.y, Uboot hangs on "Starting kernel ...".
Boot log:
U-Boot 2019.01-gb9a02a7d56-dirty (Nov 28 2022 - 07:45:43 -0500)
CPU: 66AK2Gx-100 SR1.0
DRAM:
Clear entire DDR3 memory to enable ECC
Memory Test. Start addr 0x80000000 size 512 MiB
512 MiB
POST mem_regions PASSED
Flash: 128 MiB
Loading Environment from norflash... OK
Net: eth0: netcp@4000000
Hit any key to stop autoboot: 0
=> printenv
OPIMAGEVALID1=TRUE
OPIMAGEVALID2=TRUE
arch=arm
args_all=setenv bootargs console=ttyS0,115200n8
baudrate=115200
board=tma
board_name=tma
boot_fdt=try
boot_monitor_fit_entry=mon-0
boot_monitor_loadadd=0x80000000
bootargs=console=ttyS0,115200n8
bootcmd=run dual_boot_cmd
bootcmd_fit=run set_ubootFlag; run args_all; saveenv; run install_boot_monitor;run install_power_mgnt;bootm ${fit_loadaddr}
bootdelay=2
bootm_size=0x10000000
checkPrimaryImage=if iminfo ${fitA}; then setenv OPIMAGEVALID1 TRUE; else setenv OPIMAGEVALID1 FALSE; fi
checkSecondaryImage=if iminfo ${fitB}; then setenv OPIMAGEVALID2 TRUE; else setenv OPIMAGEVALID2 FALSE; fi
cpu=armv7
dual_boot_cmd=get_post_test_status; run checkPrimaryImage; run checkSecondaryImage; if test "$OPIMAGEVALID1" = "TRUE"; then echo "Loading Primary FIT" ; setenv imageFlag primary; setenv fit_loadaddr ${fitA}; run bootcmd_fit; elif test "$OPIMAGEVALID2" = "TRUE"; then echo "Loading Secondary FIT" ; setenv imageFlag secondary; setenv fit_loadaddr ${fitB}; run bootcmd_fit; else echo "Primary and Secondary FIT both invalid for use. Halt!!"; fi;
ethaddr=e0:62:34:6a:0b:fc
fdt_addr_r=0x88000000
fdtaddr=0x88000000
fdtcontroladdr=9df1f800
fitA=0x30700000
fitB=0x34300000
fit_loadaddr=0x30700000
gatewayip=192.168.1.1
imageFlag=primary
install_boot_monitor=imxtract ${fit_loadaddr} ${boot_monitor_fit_entry} ${boot_monitor_loadadd};mon_install ${boot_monitor_loadadd};
install_power_mgnt=imxtract ${fit_loadaddr} ${power_mgnt_fit_entry} ${power_mgnt_loadadd};rproc init; rproc load 0 ${power_mgnt_loadadd} 0x8354; rproc start 0;
ipaddr=192.168.1.3
kernel_addr_r=0x82000000
loadaddr=0x82000000
mem_lpae=1
mem_post_status=Passed
mtdids=nand0=davinci_nand.0
mtdparts=mtdparts=davinci_nand.0:1024k(bootloader)ro,512k(params)ro,-(ubifs)
netmask=255.255.255.0
operationalFlag=NoResult
power_mgnt_fit_entry=pmmc-0
power_mgnt_loadadd=0x80010000
pxefile_addr_r=0x80100000
ramdisk_addr_r=0x88080000
rdaddr=0x88080000
scriptaddr=0x80000000
serverip=192.168.1.4
set_ubootFlag=if itest *0x0C01FFFC -eq 0x31; then setenv uBootFlag primary; elif itest *0x0C01FFFC -eq 0x32; then setenv uBootFlag secondary; else setenv uBootFlag na; fi;
soc=keystone
stderr=serial@02530c00
stdin=serial@02530c00
stdout=serial@02530c00
uBootFlag=primary
ver=U-Boot 2019.01-gb9a02a7d56-dirty (Nov 28 2022 - 07:45:43 -0500)
Environment size: 2351/262140 bytes
=> run bootcmd
Saving Environment to norflash... From 0x9dedf580 to 0x30600000 Bytes 262144)
Erasing from sector #48 to #49
2/2
Sector(s) erased. Writing to FLASH
131072/131072
Write completed. Last addr written (0x30640000)
OK
## Copying 'mon-0' subimage from FIT image at 34300000 ...
sha1+ Loading part 0 ... OK
K2_BM_15.07-54-gd57d5c1d8f0b SoC:k2g built:08:48:33, Oct 22 2020
## installed monitor @ 0xc0f7000, freq [24000000], status 202338304
## Copying 'pmmc-0' subimage from FIT image at 34300000 ...
sha1+ Loading part 0 ... OK
Load Remote Processor 0 with data@addr=0x80010000 33620 bytes: Success!
## Loading kernel from FIT Image at 34300000 ...
Using 'conf-1' configuration
Trying 'kernel-0' kernel subimage
Description: Linux Kernel
Created: 2025-02-05 9:26:59 UTC
Type: Kernel Image
Compression: uncompressed
Data Start: 0x343000c4
Data Size: 4713312 Bytes = 4.5 MiB
Architecture: ARM
OS: Linux
Load Address: 0x80030000
Entry Point: 0x80030000
Hash algo: sha1
Hash value: 31d8d4a139568afb196d96488a18a1347c5889b9
Verifying Hash Integrity ... sha1+ OK
## Loading ramdisk from FIT Image at 34300000 ...
Using 'conf-1' configuration
Trying 'ramdisk-0' ramdisk subimage
Description: ramdisk
Created: 2025-02-05 9:26:59 UTC
Type: RAMDisk Image
Compression: uncompressed
Data Start: 0x34794e24
Data Size: 21516984 Bytes = 20.5 MiB
Architecture: ARM
OS: Linux
Load Address: 0x81500000
Entry Point: unavailable
Hash algo: sha1
Hash value: f96026afd9d9ccb273987839c1f156f700f1dcd9
Verifying Hash Integrity ... sha1+ OK
Loading ramdisk from 0x34794e24 to 0x81500000
## Loading fdt from FIT Image at 34300000 ...
Using 'conf-1' configuration
Trying 'fdt-0' fdt subimage
Description: Flattened Device Tree blob
Created: 2025-02-05 9:26:59 UTC
Type: Flat Device Tree
Compression: uncompressed
Data Start: 0x3477ed18
Data Size: 23322 Bytes = 22.8 KiB
Architecture: ARM
Load Address: 0x80020000
Hash algo: sha1
Hash value: 7744f57256cc17a615a0731f913f8b108eff8853
Verifying Hash Integrity ... sha1+ OK
Loading fdt from 0x3477ed18 to 0x80020000
Booting using the fdt blob at 0x80020000
Loading Kernel Image ... OK
Loading Ramdisk to 8eb7a000, end 8ffff2b8 ... OK
Loading Device Tree to 8eb71000, end 8eb79b19 ... OK
Starting kernel ...
[ 0.000000] Booting Linux on physical CPU 0x0
[ 0.000000] Linux version 6.1.112-ti-g4ef41ca7ad95 (oe-user@oe-host) (arm-oe-linux-gnueabi-gcc (GCC) 13.3.0, GNU ld (GNU Binutils) 2.42.0.20240723) #1 SMP PREEMPT Wed Nov 13 13:49:51 UTC 2024
[ 0.000000] CPU: ARMv7 Processor [412fc0f4] revision 4 (ARMv7), cr=30c5387d
[ 0.000000] CPU: div instructions available: patching division code
[ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, PIPT instruction cache
[ 0.000000] OF: fdt: Machine model: TMA
[ 0.000000] Memory policy: Data cache writealloc
[ 0.000000] Switching physical address space to 0x800000000
[ 0.000000] INITRD: 0x8eb7a000+0x01486000 is not a memory region - disabling initrd
[ 0.000000] Reserved memory: created CMA memory pool at 0x000000081f800000, size 8 MiB
[ 0.000000] OF: reserved mem: initialized node dsp-common-memory@81f800000, compatible id shared-dma-pool
[ 0.000000] cma: Reserved 48 MiB at 0x0000000801400000
[ 0.000000] Zone ranges:
[ 0.000000] DMA [mem 0x0000000800000000-0x000000081fffffff]
[ 0.000000] Normal empty
[ 0.000000] HighMem empty
[ 0.000000] Movable zone start for each node
[ 0.000000] Early memory node ranges
[ 0.000000] node 0: [mem 0x0000000800000000-0x000000081fffffff]
[ 0.000000] Initmem setup node 0 [mem 0x0000000800000000-0x000000081fffffff]
[ 0.000000] percpu: Embedded 12 pages/cpu s16468 r8192 d24492 u49152
[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 129920
[ 0.000000] Kernel command line: console=ttyS0,115200n8
[ 0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
[ 0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes, linear)
[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
[ 0.000000] Memory: 425480K/524288K available (8192K kernel code, 613K rwdata, 2008K rodata, 2048K init, 242K bss, 41464K reserved, 57344K cma-reserved, 0K highmem)
[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=1.
[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
[ 0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
[ 0.000000] GIC: Using split EOI/Deactivate mode
[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
[ 0.000000] arch_timer: cp15 timer(s) running at 24.00MHz (phys).
[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x588fe9dc0, max_idle_ns: 440795202592 ns
[ 0.000001] sched_clock: 56 bits at 24MHz, resolution 41ns, wraps every 4398046511097ns
[ 0.000013] Switching to timer-based delay loop, resolution 41ns
[ 0.000244] Console: colour dummy device 80x30
[ 0.000289] Calibrating delay loop (skipped), value calculated using timer frequency.. 48.00 BogoMIPS (lpj=240000)
[ 0.000302] CPU: Testing write buffer coherency: ok
[ 0.000338] CPU0: Spectre v2: using ICIALLU workaround
[ 0.000346] CPU0: Spectre BHB: enabling loop workaround for all CPUs
[ 0.000352] pid_max: default: 32768 minimum: 301
[ 0.000478] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
[ 0.000489] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
[ 0.001282] /cpus/cpu@0 missing clock-frequency property
[ 0.001306] CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
[ 0.001977] Setting up static identity map for 0x80200000 - 0x80200138
[ 0.002087] rcu: Hierarchical SRCU implementation.
[ 0.002093] rcu: Max phase no-delay instances is 1000.
[ 0.002412] smp: Bringing up secondary CPUs ...
[ 0.002419] smp: Brought up 1 node, 1 CPU
[ 0.002426] SMP: Total of 1 processors activated (48.00 BogoMIPS).
[ 0.002434] CPU: All CPU(s) started in HYP mode.
[ 0.002438] CPU: Virtualization extensions available.
[ 0.002817] devtmpfs: initialized
[ 0.006465] VFP support v0.3: implementor 41 architecture 4 part 30 variant f rev 0
[ 0.006602] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
[ 0.006618] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
[ 0.007850] pinctrl core: initialized pinctrl subsystem
[ 0.008807] NET: Registered PF_NETLINK/PF_ROUTE protocol family
[ 0.009914] DMA: preallocated 256 KiB pool for atomic coherent allocations
[ 0.010774] thermal_sys: Registered thermal governor 'fair_share'
[ 0.010781] thermal_sys: Registered thermal governor 'bang_bang'
[ 0.010786] thermal_sys: Registered thermal governor 'step_wise'
[ 0.010790] thermal_sys: Registered thermal governor 'user_space'
[ 0.010852] cpuidle: using governor ladder
[ 0.010878] cpuidle: using governor menu
[ 0.011105] hw-breakpoint: found 5 (+1 reserved) breakpoint and 4 watchpoint registers.
[ 0.011115] hw-breakpoint: maximum watchpoint size is 8 bytes.
[ 0.025604] pps_core: LinuxPPS API ver. 1 registered
[ 0.025613] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
[ 0.025629] EDAC MC: Ver: 3.0.0
[ 0.026838] clocksource: Switched to clocksource arch_sys_counter
[ 0.033608] NET: Registered PF_INET protocol family
[ 0.033783] IP idents hash table entries: 8192 (order: 4, 65536 bytes, linear)
[ 0.034707] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes, linear)
[ 0.034735] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
[ 0.034748] TCP established hash table entries: 4096 (order: 2, 16384 bytes, linear)
[ 0.034783] TCP bind hash table entries: 4096 (order: 4, 65536 bytes, linear)
[ 0.034901] TCP: Hash tables configured (established 4096 bind 4096)
[ 0.034960] UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
[ 0.034984] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
[ 0.035102] NET: Registered PF_UNIX/PF_LOCAL protocol family
[ 0.035516] hw perfevents: enabled with armv7_cortex_a15 PMU driver, 7 counters available
[ 0.036302] Initialise system trusted keyrings
[ 0.036785] workingset: timestamp_bits=14 max_order=17 bucket_order=3
[ 0.042004] Key type asymmetric registered
[ 0.042015] Asymmetric key parser 'x509' registered
[ 0.042123] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 249)
[ 0.042132] io scheduler mq-deadline registered
[ 0.042138] io scheduler kyber registered
[ 0.042508] keystone_irq 26202a0.keystone_irq: irqchip registered, nr_irqs 28
[ 0.043090] pinctrl-single 2621000.pinmux: please update dts to use #pinctrl-cells = <1>
[ 0.043456] pinctrl-single 2621000.pinmux: 260 pins, size 1040
[ 0.084257] Serial: 8250/16550 driver, 10 ports, IRQ sharing enabled
[ 0.084322] platform serial8250: set dma_offset780000000
[ 0.093411] brd: module loaded
[ 0.098056] loop: module loaded
[ 0.100327] physmap-flash 30000000.gpmc_nor: physmap platform flash device: [mem 0x30000000-0x3fffffff]
[ 0.100391] 30000000.gpmc_nor: Found 1 x16 devices at 0x0 in 16-bit bank. Manufacturer ID 0x000001 Chip ID 0x002801
[ 0.100407] 30000000.gpmc_nor: Found 1 x16 devices at 0x8000000 in 16-bit bank
[ 0.100421] Amd/Fujitsu Extended Query Table at 0x0040
[ 0.100435] Amd/Fujitsu Extended Query version 1.5.
[ 0.100445] number of CFI chips: 2
[ 0.100954] 6 fixed-partitions partitions found on MTD device 30000000.gpmc_nor
[ 0.100966] Creating 6 MTD partitions on "30000000.gpmc_nor":
[ 0.100973] 0x000000200000-0x000000400000 : "uboot_1"
[ 0.102184] 0x000000400000-0x000000600000 : "uboot_2"
[ 0.103221] 0x000000600000-0x000000700000 : "uboot_env"
[ 0.104258] 0x000000700000-0x000004300000 : "itb_1"
[ 0.105266] 0x000004300000-0x000007f00000 : "itb_2"
[ 0.106296] 0x000008000000-0x00000ffe0000 : "gpmc_partition"
[ 0.107960] platform Fixed MDIO bus.0: set dma_offset780000000
[ 0.108556] i2c_dev: i2c /dev entries driver
[ 0.110077] NET: Registered PF_PACKET protocol family
[ 0.110148] Key type dns_resolver registered
[ 0.110185] Registering SWP/SWPB emulation handler
[ 0.110560] Loading compiled-in X.509 certificates
[ 0.115451] ti-sci 2921c00.system-controller: ABI: 2.4 (firmware rev 0x0011 '0.1.1-50-g129ef (Eagle)')
[ 0.123716] keystone-rproc 10800000.dsp: assigned reserved memory node dsp-common-memory@81f800000
[ 0.123912] remoteproc remoteproc0: 10800000.dsp is available
[ 0.124062] remoteproc remoteproc0: Direct firmware load for keystone-dsp0-fw failed with error -2
[ 0.124075] remoteproc remoteproc0: powering up 10800000.dsp
[ 0.124127] remoteproc remoteproc0: Direct firmware load for keystone-dsp0-fw failed with error -2
[ 0.124138] remoteproc remoteproc0: request_firmware failed: -2
[ 0.134442] debugfs: Directory '2700000.edma' with parent 'dmaengine' already present!
[ 0.134460] edma 2700000.edma: TI EDMA DMA engine driver
[ 0.134914] edma 2728000.edma: memcpy is disabled
[ 0.137987] edma 2728000.edma: TI EDMA DMA engine driver
[ 0.138872] lm75 0-0048: supply vs not found, using dummy regulator
[ 0.139362] hwmon hwmon0: temp1_input not attached to any thermal zone
[ 0.139373] lm75 0-0048: hwmon0: sensor 'lm75'
[ 0.140458] keystone-navigator-qmss soc@0:qmss@4020000: qmgr start queue 0, number of queues 128
[ 0.140560] keystone-navigator-qmss soc@0:qmss@4020000: added qmgr start queue 0, num of queues 128, reg_peek (ptrval), reg_status 00000000, reg_config (ptrval), reg_region (ptrval), reg_push (ptrval), reg_pop (ptrval)
[ 0.141411] keystone-navigator-dma soc@0:knav_dmas@0: DMA dma_gbe registered 53 logical channels, flows 32, tx chans: 21, rx chans: 32
[ 0.142374] printk: console [ttyS0] disabled
[ 0.142506] 2530c00.serial: ttyS0 at MMIO 0x2530c00 (irq = 274, base_baud = 12000000) is a TI DA8xx/66AK2x
[ 1.029737] printk: console [ttyS0] enabled
[ 1.035267] 2531000.serial: ttyS1 at MMIO 0x2531000 (irq = 275, base_baud = 12000000) is a TI DA8xx/66AK2x
[ 1.046277] 2531400.serial: ttyS2 at MMIO 0x2531400 (irq = 276, base_baud = 12000000) is a TI DA8xx/66AK2x
[ 1.057985] spi_davinci 21805400.spi: DMA is not supported (-19)
[ 1.064341] spi_davinci 21805400.spi: Controller at 0x(ptrval)
[ 1.070807] spi_davinci 21805800.spi: DMA is not supported (-19)
[ 1.077153] spi_davinci 21805800.spi: Controller at 0x(ptrval)
[ 1.083521] spi_davinci 21805c00.spi: DMA is not supported (-19)
[ 1.089867] spi_davinci 21805c00.spi: Controller at 0x(ptrval)
[ 1.096214] spi_davinci 21806000.spi: DMA is not supported (-19)
[ 1.102566] spi_davinci 21806000.spi: Controller at 0x(ptrval)
[ 1.167020] davinci_mdio 4200f00.mdio: davinci mdio revision 1.7, bus freq 2500000
[ 1.176526] davinci_mdio 4200f00.mdio: phy[1]: device 4200f00.mdio:01, driver NS DP83848C 10/100 Mbps PHY
[ 1.186508] netcp-1.0 2620110.netcp: ALE enabled
[ 1.191259] netcp-1.0 2620110.netcp: initialized cpsw ale version 1.4
[ 1.197725] netcp-1.0 2620110.netcp: ALE Table size 64
[ 1.203268] netcp-1.0 2620110.netcp: module(netcp-xgbe) not used for device
[ 1.211870] clk: Disabling unused clocks
[ 1.227477] /dev/root: Can't open blockdev
[ 1.231897] Kernel panic - not syncing: VFS: Unable to mount root fs on unknown-block(0,0)
[ 1.240143] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 6.1.112-ti-g4ef41ca7ad95 #1
[ 1.247613] Hardware name: Keystone
[ 1.251096] [<c020dc4c>] (unwind_backtrace) from [<c0209c84>] (show_stack+0x10/0x14)
[ 1.258843] [<c0209c84>] (show_stack) from [<c0862850>] (dump_stack_lvl+0x40/0x4c)
[ 1.266410] [<c0862850>] (dump_stack_lvl) from [<c085820c>] (panic+0x114/0x314)
[ 1.273721] [<c085820c>] (panic) from [<c0e017a0>] (mount_block_root+0x174/0x20c)
[ 1.281205] [<c0e017a0>] (mount_block_root) from [<c0e01b2c>] (prepare_namespace+0x150/0x18c)
[ 1.289722] [<c0e01b2c>] (prepare_namespace) from [<c0862e44>] (kernel_init+0x18/0x12c)
[ 1.297721] [<c0862e44>] (kernel_init) from [<c020021c>] (ret_from_fork+0x14/0x38)
[ 1.305284] Exception stack(0xe0811fb0 to 0xe0811ff8)
[ 1.310324] 1fa0: 00000000 00000000 00000000 00000000
[ 1.318485] 1fc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
[ 1.326644] 1fe0: 00000000 00000000 00000000 00000000 00000013 00000000
[ 1.333250] ---[ end Kernel panic - not syncing: VFS: Unable to mount root fs on unknown-block(0,0) ]---
Linux Kernel source: https://git.ti.com/cgit/ti-linux-kernel/ti-linux-kernel/tree/?h=ti-linux-6.1.y&id=4ef41ca7ad952c7b13b7e40808ab1025796f9a6c
Kernel config:
# # Automatically generated file; DO NOT EDIT. # Linux/arm 6.1.112 Kernel Configuration # CONFIG_CC_VERSION_TEXT="arm-oe-linux-gnueabi-gcc (GCC) 13.3.0" CONFIG_CC_IS_GCC=y CONFIG_GCC_VERSION=130300 CONFIG_CLANG_VERSION=0 CONFIG_AS_IS_GNU=y CONFIG_AS_VERSION=24200 CONFIG_LD_IS_BFD=y CONFIG_LD_VERSION=24200 CONFIG_LLD_VERSION=0 CONFIG_CC_HAS_ASM_GOTO_OUTPUT=y CONFIG_CC_HAS_ASM_GOTO_TIED_OUTPUT=y CONFIG_CC_HAS_ASM_INLINE=y CONFIG_CC_HAS_NO_PROFILE_FN_ATTR=y CONFIG_PAHOLE_VERSION=0 CONFIG_IRQ_WORK=y CONFIG_BUILDTIME_TABLE_SORT=y CONFIG_THREAD_INFO_IN_TASK=y # # General setup # CONFIG_INIT_ENV_ARG_LIMIT=32 # CONFIG_COMPILE_TEST is not set CONFIG_WERROR=y CONFIG_LOCALVERSION="" CONFIG_LOCALVERSION_AUTO=y CONFIG_BUILD_SALT="" CONFIG_HAVE_KERNEL_GZIP=y CONFIG_HAVE_KERNEL_LZMA=y CONFIG_HAVE_KERNEL_XZ=y CONFIG_HAVE_KERNEL_LZO=y CONFIG_HAVE_KERNEL_LZ4=y CONFIG_KERNEL_GZIP=y # CONFIG_KERNEL_LZMA is not set # CONFIG_KERNEL_XZ is not set # CONFIG_KERNEL_LZO is not set # CONFIG_KERNEL_LZ4 is not set CONFIG_DEFAULT_INIT="" CONFIG_DEFAULT_HOSTNAME="(none)" CONFIG_SYSVIPC=y CONFIG_SYSVIPC_SYSCTL=y CONFIG_POSIX_MQUEUE=y CONFIG_POSIX_MQUEUE_SYSCTL=y # CONFIG_WATCH_QUEUE is not set CONFIG_CROSS_MEMORY_ATTACH=y # CONFIG_USELIB is not set # CONFIG_AUDIT is not set CONFIG_HAVE_ARCH_AUDITSYSCALL=y # # IRQ subsystem # CONFIG_GENERIC_IRQ_PROBE=y CONFIG_GENERIC_IRQ_SHOW=y CONFIG_GENERIC_IRQ_SHOW_LEVEL=y CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y CONFIG_GENERIC_IRQ_MIGRATION=y CONFIG_HARDIRQS_SW_RESEND=y CONFIG_IRQ_DOMAIN=y CONFIG_IRQ_DOMAIN_HIERARCHY=y CONFIG_GENERIC_IRQ_IPI=y CONFIG_IRQ_FORCED_THREADING=y CONFIG_SPARSE_IRQ=y # CONFIG_GENERIC_IRQ_DEBUGFS is not set # end of IRQ subsystem CONFIG_GENERIC_IRQ_MULTI_HANDLER=y CONFIG_GENERIC_TIME_VSYSCALL=y CONFIG_GENERIC_CLOCKEVENTS=y CONFIG_ARCH_HAS_TICK_BROADCAST=y CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y CONFIG_CONTEXT_TRACKING=y CONFIG_CONTEXT_TRACKING_IDLE=y # # Timers subsystem # CONFIG_TICK_ONESHOT=y CONFIG_NO_HZ_COMMON=y # CONFIG_HZ_PERIODIC is not set CONFIG_NO_HZ_IDLE=y # CONFIG_NO_HZ_FULL is not set CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y # end of Timers subsystem CONFIG_BPF=y CONFIG_HAVE_EBPF_JIT=y # # BPF subsystem # # CONFIG_BPF_SYSCALL is not set # CONFIG_BPF_JIT is not set # end of BPF subsystem CONFIG_PREEMPT_BUILD=y # CONFIG_PREEMPT_NONE is not set # CONFIG_PREEMPT_VOLUNTARY is not set CONFIG_PREEMPT=y CONFIG_PREEMPT_COUNT=y CONFIG_PREEMPTION=y # # CPU/Task time and stats accounting # CONFIG_TICK_CPU_ACCOUNTING=y # CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set # CONFIG_IRQ_TIME_ACCOUNTING is not set CONFIG_SCHED_THERMAL_PRESSURE=y CONFIG_BSD_PROCESS_ACCT=y # CONFIG_BSD_PROCESS_ACCT_V3 is not set # CONFIG_TASKSTATS is not set # CONFIG_PSI is not set # end of CPU/Task time and stats accounting CONFIG_CPU_ISOLATION=y # # RCU Subsystem # CONFIG_TREE_RCU=y CONFIG_PREEMPT_RCU=y # CONFIG_RCU_EXPERT is not set CONFIG_SRCU=y CONFIG_TREE_SRCU=y CONFIG_RCU_STALL_COMMON=y CONFIG_RCU_NEED_SEGCBLIST=y # end of RCU Subsystem # CONFIG_IKCONFIG is not set # CONFIG_IKHEADERS is not set CONFIG_LOG_BUF_SHIFT=17 CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13 # CONFIG_PRINTK_INDEX is not set CONFIG_GENERIC_SCHED_CLOCK=y # # Scheduler features # # CONFIG_UCLAMP_TASK is not set # end of Scheduler features CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5" CONFIG_GCC10_NO_ARRAY_BOUNDS=y CONFIG_CC_NO_ARRAY_BOUNDS=y CONFIG_CGROUPS=y CONFIG_PAGE_COUNTER=y # CONFIG_CGROUP_FAVOR_DYNMODS is not set CONFIG_MEMCG=y CONFIG_MEMCG_KMEM=y CONFIG_BLK_CGROUP=y CONFIG_CGROUP_WRITEBACK=y CONFIG_CGROUP_SCHED=y CONFIG_FAIR_GROUP_SCHED=y CONFIG_CFS_BANDWIDTH=y # CONFIG_RT_GROUP_SCHED is not set CONFIG_CGROUP_PIDS=y # CONFIG_CGROUP_RDMA is not set CONFIG_CGROUP_FREEZER=y # CONFIG_CPUSETS is not set CONFIG_CGROUP_DEVICE=y CONFIG_CGROUP_CPUACCT=y CONFIG_CGROUP_PERF=y # CONFIG_CGROUP_MISC is not set # CONFIG_CGROUP_DEBUG is not set CONFIG_NAMESPACES=y # CONFIG_UTS_NS is not set # CONFIG_IPC_NS is not set # CONFIG_USER_NS is not set # CONFIG_PID_NS is not set CONFIG_NET_NS=y CONFIG_CHECKPOINT_RESTORE=y # CONFIG_SCHED_AUTOGROUP is not set # CONFIG_SYSFS_DEPRECATED is not set # CONFIG_RELAY is not set CONFIG_BLK_DEV_INITRD=y CONFIG_INITRAMFS_SOURCE="" CONFIG_RD_GZIP=y CONFIG_RD_BZIP2=y # CONFIG_RD_LZMA is not set CONFIG_RD_XZ=y # CONFIG_RD_LZO is not set # CONFIG_RD_LZ4 is not set # CONFIG_RD_ZSTD is not set # CONFIG_BOOT_CONFIG is not set CONFIG_INITRAMFS_PRESERVE_MTIME=y CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set CONFIG_LD_ORPHAN_WARN=y CONFIG_SYSCTL=y CONFIG_HAVE_UID16=y CONFIG_EXPERT=y CONFIG_UID16=y CONFIG_MULTIUSER=y # CONFIG_SGETMASK_SYSCALL is not set CONFIG_SYSFS_SYSCALL=y CONFIG_FHANDLE=y CONFIG_POSIX_TIMERS=y CONFIG_PRINTK=y CONFIG_BUG=y # CONFIG_ELF_CORE is not set CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_FUTEX_PI=y CONFIG_EPOLL=y CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y CONFIG_AIO=y CONFIG_IO_URING=y CONFIG_ADVISE_SYSCALLS=y CONFIG_MEMBARRIER=y CONFIG_KALLSYMS=y CONFIG_KALLSYMS_ALL=y CONFIG_KALLSYMS_BASE_RELATIVE=y CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y CONFIG_KCMP=y CONFIG_RSEQ=y # CONFIG_DEBUG_RSEQ is not set CONFIG_EMBEDDED=y CONFIG_HAVE_PERF_EVENTS=y CONFIG_PERF_USE_VMALLOC=y # CONFIG_PC104 is not set # # Kernel Performance Events And Counters # CONFIG_PERF_EVENTS=y # CONFIG_DEBUG_PERF_USE_VMALLOC is not set # end of Kernel Performance Events And Counters # CONFIG_PROFILING is not set # end of General setup CONFIG_ARM=y CONFIG_ARM_HAS_GROUP_RELOCS=y CONFIG_SYS_SUPPORTS_APM_EMULATION=y CONFIG_HAVE_PROC_CPU=y CONFIG_STACKTRACE_SUPPORT=y CONFIG_LOCKDEP_SUPPORT=y CONFIG_FIX_EARLYCON_MEM=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_ARCH_SUPPORTS_UPROBES=y CONFIG_ARM_PATCH_PHYS_VIRT=y CONFIG_GENERIC_BUG=y CONFIG_PGTABLE_LEVELS=3 # # System Type # CONFIG_MMU=y CONFIG_ARCH_MMAP_RND_BITS_MIN=8 CONFIG_ARCH_MMAP_RND_BITS_MAX=16 CONFIG_ARCH_MULTIPLATFORM=y # # Platform selection # # # CPU Core family selection # # CONFIG_ARCH_MULTI_V6 is not set CONFIG_ARCH_MULTI_V7=y CONFIG_ARCH_MULTI_V6_V7=y # end of Platform selection # CONFIG_ARCH_VIRT is not set # CONFIG_ARCH_AIROHA is not set # CONFIG_ARCH_ACTIONS is not set # CONFIG_ARCH_ALPINE is not set # CONFIG_ARCH_ARTPEC is not set # CONFIG_ARCH_ASPEED is not set # CONFIG_ARCH_AT91 is not set # CONFIG_ARCH_AXXIA is not set # CONFIG_ARCH_BCM is not set # CONFIG_ARCH_BERLIN is not set # CONFIG_ARCH_DIGICOLOR is not set # CONFIG_ARCH_DOVE is not set # CONFIG_ARCH_EXYNOS is not set # CONFIG_ARCH_HIGHBANK is not set # CONFIG_ARCH_HISI is not set # CONFIG_ARCH_HPE is not set # CONFIG_ARCH_MXC is not set CONFIG_ARCH_KEYSTONE=y # CONFIG_ARCH_MEDIATEK is not set # CONFIG_ARCH_MESON is not set # CONFIG_ARCH_MILBEAUT is not set # CONFIG_ARCH_MMP is not set # CONFIG_ARCH_MSTARV7 is not set # CONFIG_ARCH_MVEBU is not set # CONFIG_ARCH_NPCM is not set # # TI OMAP/AM/DM/DRA Family # # CONFIG_ARCH_OMAP3 is not set # CONFIG_ARCH_OMAP4 is not set # CONFIG_SOC_OMAP5 is not set # CONFIG_SOC_AM33XX is not set # CONFIG_SOC_AM43XX is not set # CONFIG_SOC_DRA7XX is not set # end of TI OMAP/AM/DM/DRA Family # CONFIG_ARCH_QCOM is not set # CONFIG_ARCH_RDA is not set # CONFIG_ARCH_REALTEK is not set # CONFIG_ARCH_ROCKCHIP is not set # CONFIG_ARCH_S5PV210 is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_INTEL_SOCFPGA is not set # CONFIG_PLAT_SPEAR is not set # CONFIG_ARCH_STI is not set # CONFIG_ARCH_STM32 is not set # CONFIG_ARCH_SUNPLUS is not set # CONFIG_ARCH_SUNXI is not set # CONFIG_ARCH_TEGRA is not set # CONFIG_ARCH_UNIPHIER is not set # CONFIG_ARCH_U8500 is not set # CONFIG_ARCH_REALVIEW is not set # CONFIG_ARCH_VEXPRESS is not set # CONFIG_ARCH_WM8850 is not set # CONFIG_ARCH_ZYNQ is not set # # Processor Type # CONFIG_CPU_V7=y CONFIG_CPU_THUMB_CAPABLE=y CONFIG_CPU_32v6K=y CONFIG_CPU_32v7=y CONFIG_CPU_ABRT_EV7=y CONFIG_CPU_PABRT_V7=y CONFIG_CPU_CACHE_V7=y CONFIG_CPU_CACHE_VIPT=y CONFIG_CPU_COPY_V6=y CONFIG_CPU_TLB_V7=y CONFIG_CPU_HAS_ASID=y CONFIG_CPU_CP15=y CONFIG_CPU_CP15_MMU=y # # Processor Features # CONFIG_ARM_LPAE=y CONFIG_ARM_PV_FIXUP=y CONFIG_ARM_THUMB=y # CONFIG_ARM_THUMBEE is not set CONFIG_ARM_VIRT_EXT=y CONFIG_SWP_EMULATE=y CONFIG_CPU_LITTLE_ENDIAN=y # CONFIG_CPU_BIG_ENDIAN is not set # CONFIG_CPU_ICACHE_DISABLE is not set # CONFIG_CPU_ICACHE_MISMATCH_WORKAROUND is not set # CONFIG_CPU_BPREDICT_DISABLE is not set CONFIG_CPU_SPECTRE=y CONFIG_HARDEN_BRANCH_PREDICTOR=y CONFIG_HARDEN_BRANCH_HISTORY=y CONFIG_KUSER_HELPERS=y CONFIG_VDSO=y CONFIG_OUTER_CACHE=y CONFIG_OUTER_CACHE_SYNC=y CONFIG_MIGHT_HAVE_CACHE_L2X0=y CONFIG_CACHE_L2X0=y # CONFIG_CACHE_L2X0_PMU is not set # CONFIG_PL310_ERRATA_588369 is not set # CONFIG_PL310_ERRATA_727915 is not set # CONFIG_PL310_ERRATA_753970 is not set # CONFIG_PL310_ERRATA_769419 is not set CONFIG_ARM_L1_CACHE_SHIFT_6=y CONFIG_ARM_L1_CACHE_SHIFT=6 CONFIG_ARM_DMA_MEM_BUFFERABLE=y CONFIG_ARM_HEAVY_MB=y CONFIG_DEBUG_ALIGN_RODATA=y # CONFIG_ARM_ERRATA_430973 is not set CONFIG_ARM_ERRATA_643719=y # CONFIG_ARM_ERRATA_720789 is not set # CONFIG_ARM_ERRATA_754322 is not set # CONFIG_ARM_ERRATA_754327 is not set # CONFIG_ARM_ERRATA_764369 is not set # CONFIG_ARM_ERRATA_764319 is not set # CONFIG_ARM_ERRATA_775420 is not set CONFIG_ARM_ERRATA_798181=y # CONFIG_ARM_ERRATA_773022 is not set # CONFIG_ARM_ERRATA_818325_852422 is not set # CONFIG_ARM_ERRATA_821420 is not set # CONFIG_ARM_ERRATA_825619 is not set # CONFIG_ARM_ERRATA_857271 is not set # CONFIG_ARM_ERRATA_852421 is not set # CONFIG_ARM_ERRATA_852423 is not set # CONFIG_ARM_ERRATA_857272 is not set # end of System Type # # Bus support # # CONFIG_ARM_ERRATA_814220 is not set # end of Bus support # # Kernel Features # CONFIG_HAVE_SMP=y CONFIG_SMP=y CONFIG_SMP_ON_UP=y CONFIG_CURRENT_POINTER_IN_TPIDRURO=y CONFIG_IRQSTACKS=y CONFIG_ARM_CPU_TOPOLOGY=y # CONFIG_SCHED_MC is not set # CONFIG_SCHED_SMT is not set CONFIG_HAVE_ARM_ARCH_TIMER=y # CONFIG_MCPM is not set # CONFIG_BIG_LITTLE is not set CONFIG_VMSPLIT_3G=y # CONFIG_VMSPLIT_2G is not set # CONFIG_VMSPLIT_1G is not set CONFIG_PAGE_OFFSET=0xC0000000 CONFIG_NR_CPUS=8 CONFIG_HOTPLUG_CPU=y CONFIG_ARM_PSCI=y CONFIG_ARCH_NR_GPIO=512 CONFIG_HZ_FIXED=0 CONFIG_HZ_100=y # CONFIG_HZ_200 is not set # CONFIG_HZ_250 is not set # CONFIG_HZ_300 is not set # CONFIG_HZ_500 is not set # CONFIG_HZ_1000 is not set CONFIG_HZ=100 CONFIG_SCHED_HRTICK=y # CONFIG_THUMB2_KERNEL is not set CONFIG_ARM_PATCH_IDIV=y CONFIG_AEABI=y # CONFIG_OABI_COMPAT is not set CONFIG_ARCH_SELECT_MEMORY_MODEL=y CONFIG_ARCH_FLATMEM_ENABLE=y CONFIG_ARCH_SPARSEMEM_ENABLE=y CONFIG_HIGHMEM=y CONFIG_HIGHPTE=y CONFIG_HW_PERF_EVENTS=y CONFIG_ARM_MODULE_PLTS=y CONFIG_ARCH_FORCE_MAX_ORDER=11 CONFIG_ALIGNMENT_TRAP=y # CONFIG_UACCESS_WITH_MEMCPY is not set # CONFIG_PARAVIRT is not set # CONFIG_PARAVIRT_TIME_ACCOUNTING is not set # CONFIG_XEN is not set CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y CONFIG_STACKPROTECTOR_PER_TASK=y # end of Kernel Features # # Boot options # CONFIG_USE_OF=y CONFIG_ATAGS=y # CONFIG_UNUSED_BOARD_FILES is not set # CONFIG_DEPRECATED_PARAM_STRUCT is not set CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_BSS=0x0 CONFIG_ARM_APPENDED_DTB=y CONFIG_ARM_ATAG_DTB_COMPAT=y CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y # CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set CONFIG_CMDLINE="" # CONFIG_CRASH_DUMP is not set CONFIG_AUTO_ZRELADDR=y # CONFIG_EFI is not set # end of Boot options # # CPU Power Management # # # CPU Frequency scaling # CONFIG_CPU_FREQ=y CONFIG_CPU_FREQ_GOV_ATTR_SET=y CONFIG_CPU_FREQ_GOV_COMMON=y CONFIG_CPU_FREQ_STAT=y # CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set # CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set # CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y # CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set # CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set CONFIG_CPU_FREQ_GOV_PERFORMANCE=y CONFIG_CPU_FREQ_GOV_POWERSAVE=y CONFIG_CPU_FREQ_GOV_USERSPACE=y CONFIG_CPU_FREQ_GOV_ONDEMAND=y CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y # # CPU frequency scaling drivers # CONFIG_CPUFREQ_DT=y CONFIG_CPUFREQ_DT_PLATDEV=y # end of CPU Frequency scaling # # CPU Idle # CONFIG_CPU_IDLE=y CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y CONFIG_CPU_IDLE_GOV_LADDER=y CONFIG_CPU_IDLE_GOV_MENU=y # CONFIG_CPU_IDLE_GOV_TEO is not set CONFIG_DT_IDLE_STATES=y # # ARM CPU Idle Drivers # CONFIG_ARM_CPUIDLE=y # CONFIG_ARM_PSCI_CPUIDLE is not set # CONFIG_ARM_HIGHBANK_CPUIDLE is not set # end of ARM CPU Idle Drivers # end of CPU Idle # end of CPU Power Management # # Floating point emulation # # # At least one emulation must be selected # CONFIG_VFP=y CONFIG_VFPv3=y CONFIG_NEON=y CONFIG_KERNEL_MODE_NEON=y # end of Floating point emulation # # Power management options # # CONFIG_SUSPEND is not set CONFIG_PM=y CONFIG_PM_DEBUG=y # CONFIG_PM_ADVANCED_DEBUG is not set # CONFIG_DPM_WATCHDOG is not set # CONFIG_APM_EMULATION is not set CONFIG_PM_CLK=y CONFIG_PM_GENERIC_DOMAINS=y # CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set CONFIG_PM_GENERIC_DOMAINS_OF=y CONFIG_CPU_PM=y # CONFIG_ENERGY_MODEL is not set CONFIG_ARCH_SUSPEND_POSSIBLE=y CONFIG_ARM_CPU_SUSPEND=y CONFIG_ARCH_HIBERNATION_POSSIBLE=y # end of Power management options CONFIG_AS_VFP_VMRS_FPINST=y CONFIG_CPU_MITIGATIONS=y # # General architecture-dependent options # # CONFIG_KPROBES is not set CONFIG_JUMP_LABEL=y # CONFIG_STATIC_KEYS_SELFTEST is not set CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y CONFIG_ARCH_USE_BUILTIN_BSWAP=y CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y CONFIG_HAVE_OPTPROBES=y CONFIG_HAVE_NMI=y CONFIG_TRACE_IRQFLAGS_SUPPORT=y CONFIG_HAVE_ARCH_TRACEHOOK=y CONFIG_HAVE_DMA_CONTIGUOUS=y CONFIG_GENERIC_SMP_IDLE_THREAD=y CONFIG_GENERIC_IDLE_POLL_SETUP=y CONFIG_ARCH_HAS_FORTIFY_SOURCE=y CONFIG_ARCH_HAS_KEEPINITRD=y CONFIG_ARCH_HAS_SET_MEMORY=y CONFIG_ARCH_HAS_CPU_FINALIZE_INIT=y CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y CONFIG_ARCH_32BIT_OFF_T=y CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y CONFIG_HAVE_RSEQ=y CONFIG_HAVE_HW_BREAKPOINT=y CONFIG_HAVE_PERF_REGS=y CONFIG_HAVE_PERF_USER_STACK_DUMP=y CONFIG_HAVE_ARCH_JUMP_LABEL=y CONFIG_MMU_GATHER_TABLE_FREE=y CONFIG_MMU_GATHER_RCU_TABLE_FREE=y CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y CONFIG_HAVE_ARCH_SECCOMP=y CONFIG_HAVE_ARCH_SECCOMP_FILTER=y CONFIG_SECCOMP=y CONFIG_SECCOMP_FILTER=y # CONFIG_SECCOMP_CACHE_DEBUG is not set CONFIG_HAVE_STACKPROTECTOR=y CONFIG_STACKPROTECTOR=y CONFIG_STACKPROTECTOR_STRONG=y CONFIG_LTO_NONE=y CONFIG_HAVE_CONTEXT_TRACKING_USER=y CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y CONFIG_HAVE_MOD_ARCH_SPECIFIC=y CONFIG_MODULES_USE_ELF_REL=y CONFIG_HAVE_IRQ_EXIT_ON_IRQ_STACK=y CONFIG_HAVE_SOFTIRQ_ON_OWN_STACK=y CONFIG_SOFTIRQ_ON_OWN_STACK=y CONFIG_ARCH_HAS_ELF_RANDOMIZE=y CONFIG_HAVE_ARCH_MMAP_RND_BITS=y CONFIG_HAVE_EXIT_THREAD=y CONFIG_ARCH_MMAP_RND_BITS=8 CONFIG_PAGE_SIZE_LESS_THAN_64KB=y CONFIG_PAGE_SIZE_LESS_THAN_256KB=y CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y CONFIG_CLONE_BACKWARDS=y CONFIG_OLD_SIGSUSPEND3=y CONFIG_OLD_SIGACTION=y CONFIG_COMPAT_32BIT_TIME=y CONFIG_HAVE_ARCH_VMAP_STACK=y CONFIG_VMAP_STACK=y CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y CONFIG_STRICT_KERNEL_RWX=y CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y CONFIG_STRICT_MODULE_RWX=y # CONFIG_LOCK_EVENT_COUNTS is not set CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y CONFIG_HAVE_ARCH_PFN_VALID=y # # GCOV-based kernel profiling # # CONFIG_GCOV_KERNEL is not set CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y # end of GCOV-based kernel profiling CONFIG_HAVE_GCC_PLUGINS=y CONFIG_GCC_PLUGINS=y # CONFIG_GCC_PLUGIN_LATENT_ENTROPY is not set # end of General architecture-dependent options CONFIG_RT_MUTEXES=y CONFIG_BASE_SMALL=0 CONFIG_MODULES=y CONFIG_MODULE_FORCE_LOAD=y CONFIG_MODULE_UNLOAD=y CONFIG_MODULE_FORCE_UNLOAD=y # CONFIG_MODULE_UNLOAD_TAINT_TRACKING is not set CONFIG_MODVERSIONS=y CONFIG_MODULE_SRCVERSION_ALL=y # CONFIG_MODULE_SIG is not set CONFIG_MODULE_COMPRESS_NONE=y # CONFIG_MODULE_COMPRESS_GZIP is not set # CONFIG_MODULE_COMPRESS_XZ is not set # CONFIG_MODULE_COMPRESS_ZSTD is not set # CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set CONFIG_MODPROBE_PATH="/sbin/modprobe" # CONFIG_TRIM_UNUSED_KSYMS is not set CONFIG_MODULES_TREE_LOOKUP=y CONFIG_BLOCK=y CONFIG_BLOCK_LEGACY_AUTOLOAD=y CONFIG_BLK_DEV_BSG_COMMON=y CONFIG_BLK_DEV_BSGLIB=y # CONFIG_BLK_DEV_INTEGRITY is not set # CONFIG_BLK_DEV_ZONED is not set # CONFIG_BLK_DEV_THROTTLING is not set # CONFIG_BLK_WBT is not set # CONFIG_BLK_CGROUP_IOLATENCY is not set # CONFIG_BLK_CGROUP_IOCOST is not set # CONFIG_BLK_CGROUP_IOPRIO is not set CONFIG_BLK_DEBUG_FS=y # CONFIG_BLK_SED_OPAL is not set # CONFIG_BLK_INLINE_ENCRYPTION is not set # # Partition Types # CONFIG_PARTITION_ADVANCED=y # CONFIG_ACORN_PARTITION is not set # CONFIG_AIX_PARTITION is not set # CONFIG_OSF_PARTITION is not set # CONFIG_AMIGA_PARTITION is not set # CONFIG_ATARI_PARTITION is not set # CONFIG_MAC_PARTITION is not set CONFIG_MSDOS_PARTITION=y # CONFIG_BSD_DISKLABEL is not set # CONFIG_MINIX_SUBPARTITION is not set # CONFIG_SOLARIS_X86_PARTITION is not set # CONFIG_UNIXWARE_DISKLABEL is not set # CONFIG_LDM_PARTITION is not set # CONFIG_SGI_PARTITION is not set # CONFIG_ULTRIX_PARTITION is not set # CONFIG_SUN_PARTITION is not set # CONFIG_KARMA_PARTITION is not set # CONFIG_EFI_PARTITION is not set # CONFIG_SYSV68_PARTITION is not set CONFIG_CMDLINE_PARTITION=y # end of Partition Types CONFIG_BLK_MQ_VIRTIO=y CONFIG_BLK_PM=y # # IO Schedulers # CONFIG_MQ_IOSCHED_DEADLINE=y CONFIG_MQ_IOSCHED_KYBER=y # CONFIG_IOSCHED_BFQ is not set # end of IO Schedulers CONFIG_ASN1=y CONFIG_UNINLINE_SPIN_UNLOCK=y CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y CONFIG_MUTEX_SPIN_ON_OWNER=y CONFIG_RWSEM_SPIN_ON_OWNER=y CONFIG_LOCK_SPIN_ON_OWNER=y CONFIG_ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE=y CONFIG_FREEZER=y # # Executable file formats # CONFIG_BINFMT_ELF=y # CONFIG_BINFMT_ELF_FDPIC is not set CONFIG_ELFCORE=y CONFIG_BINFMT_SCRIPT=y CONFIG_ARCH_HAS_BINFMT_FLAT=y # CONFIG_BINFMT_FLAT is not set CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y # CONFIG_BINFMT_MISC is not set CONFIG_COREDUMP=y # end of Executable file formats # # Memory Management options # # CONFIG_SWAP is not set # # SLAB allocator options # # CONFIG_SLAB is not set CONFIG_SLUB=y # CONFIG_SLOB is not set CONFIG_SLAB_MERGE_DEFAULT=y # CONFIG_SLAB_FREELIST_RANDOM is not set # CONFIG_SLAB_FREELIST_HARDENED is not set # CONFIG_SLUB_STATS is not set CONFIG_SLUB_CPU_PARTIAL=y # end of SLAB allocator options # CONFIG_SHUFFLE_PAGE_ALLOCATOR is not set CONFIG_COMPAT_BRK=y CONFIG_SELECT_MEMORY_MODEL=y CONFIG_FLATMEM_MANUAL=y # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_HAVE_FAST_GUP=y CONFIG_ARCH_KEEP_MEMBLOCK=y CONFIG_MEMORY_ISOLATION=y CONFIG_SPLIT_PTLOCK_CPUS=4 CONFIG_COMPACTION=y CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1 # CONFIG_PAGE_REPORTING is not set CONFIG_MIGRATION=y CONFIG_CONTIG_ALLOC=y CONFIG_PCP_BATCH_SCALE_MAX=5 CONFIG_PHYS_ADDR_T_64BIT=y CONFIG_BOUNCE=y # CONFIG_KSM is not set CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 CONFIG_ARCH_WANT_GENERAL_HUGETLB=y # CONFIG_TRANSPARENT_HUGEPAGE is not set CONFIG_CMA=y # CONFIG_CMA_DEBUG is not set # CONFIG_CMA_DEBUGFS is not set # CONFIG_CMA_SYSFS is not set CONFIG_CMA_AREAS=7 CONFIG_GENERIC_EARLY_IOREMAP=y # CONFIG_IDLE_PAGE_TRACKING is not set CONFIG_ARCH_HAS_CURRENT_STACK_POINTER=y CONFIG_ZONE_DMA=y CONFIG_VM_EVENT_COUNTERS=y # CONFIG_PERCPU_STATS is not set # CONFIG_GUP_TEST is not set CONFIG_ARCH_HAS_PTE_SPECIAL=y CONFIG_KMAP_LOCAL=y CONFIG_KMAP_LOCAL_NON_LINEAR_PTE_ARRAY=y # CONFIG_ANON_VMA_NAME is not set # CONFIG_USERFAULTFD is not set # CONFIG_LRU_GEN is not set CONFIG_LOCK_MM_AND_FIND_VMA=y # # Data Access Monitoring # # CONFIG_DAMON is not set # end of Data Access Monitoring # end of Memory Management options CONFIG_NET=y CONFIG_NET_INGRESS=y CONFIG_NET_EGRESS=y CONFIG_SKB_EXTENSIONS=y # # Networking options # CONFIG_PACKET=y # CONFIG_PACKET_DIAG is not set CONFIG_UNIX=y CONFIG_UNIX_SCM=y CONFIG_AF_UNIX_OOB=y # CONFIG_UNIX_DIAG is not set # CONFIG_TLS is not set CONFIG_XFRM=y CONFIG_XFRM_ALGO=m CONFIG_XFRM_USER=m # CONFIG_XFRM_SUB_POLICY is not set # CONFIG_XFRM_MIGRATE is not set # CONFIG_XFRM_STATISTICS is not set CONFIG_NET_KEY=m # CONFIG_NET_KEY_MIGRATE is not set CONFIG_INET=y CONFIG_IP_MULTICAST=y # CONFIG_IP_ADVANCED_ROUTER is not set CONFIG_IP_ROUTE_CLASSID=y CONFIG_IP_PNP=y CONFIG_IP_PNP_DHCP=y CONFIG_IP_PNP_BOOTP=y CONFIG_IP_PNP_RARP=y # CONFIG_NET_IPIP is not set # CONFIG_NET_IPGRE_DEMUX is not set CONFIG_NET_IP_TUNNEL=m # CONFIG_IP_MROUTE is not set CONFIG_SYN_COOKIES=y # CONFIG_NET_IPVTI is not set CONFIG_NET_UDP_TUNNEL=m # CONFIG_NET_FOU is not set # CONFIG_INET_AH is not set # CONFIG_INET_ESP is not set # CONFIG_INET_IPCOMP is not set CONFIG_INET_TABLE_PERTURB_ORDER=16 CONFIG_INET_DIAG=y CONFIG_INET_TCP_DIAG=y CONFIG_INET_UDP_DIAG=y CONFIG_INET_RAW_DIAG=y # CONFIG_INET_DIAG_DESTROY is not set # CONFIG_TCP_CONG_ADVANCED is not set CONFIG_TCP_CONG_CUBIC=y CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TCP_MD5SIG is not set # CONFIG_IPV6 is not set # CONFIG_MPTCP is not set # CONFIG_NETWORK_SECMARK is not set # CONFIG_NETWORK_PHY_TIMESTAMPING is not set CONFIG_NETFILTER=y CONFIG_NETFILTER_ADVANCED=y CONFIG_BRIDGE_NETFILTER=m # # Core Netfilter Configuration # CONFIG_NETFILTER_INGRESS=y CONFIG_NETFILTER_EGRESS=y CONFIG_NETFILTER_SKIP_EGRESS=y CONFIG_NETFILTER_FAMILY_BRIDGE=y CONFIG_NETFILTER_FAMILY_ARP=y # CONFIG_NETFILTER_NETLINK_ACCT is not set # CONFIG_NETFILTER_NETLINK_QUEUE is not set # CONFIG_NETFILTER_NETLINK_LOG is not set # CONFIG_NETFILTER_NETLINK_OSF is not set CONFIG_NF_CONNTRACK=m # CONFIG_NF_LOG_SYSLOG is not set # CONFIG_NF_CONNTRACK_MARK is not set # CONFIG_NF_CONNTRACK_ZONES is not set CONFIG_NF_CONNTRACK_PROCFS=y # CONFIG_NF_CONNTRACK_EVENTS is not set # CONFIG_NF_CONNTRACK_TIMEOUT is not set # CONFIG_NF_CONNTRACK_TIMESTAMP is not set # CONFIG_NF_CONNTRACK_LABELS is not set CONFIG_NF_CT_PROTO_DCCP=y CONFIG_NF_CT_PROTO_SCTP=y CONFIG_NF_CT_PROTO_UDPLITE=y # CONFIG_NF_CONNTRACK_AMANDA is not set # CONFIG_NF_CONNTRACK_FTP is not set # CONFIG_NF_CONNTRACK_H323 is not set # CONFIG_NF_CONNTRACK_IRC is not set # CONFIG_NF_CONNTRACK_NETBIOS_NS is not set # CONFIG_NF_CONNTRACK_SNMP is not set # CONFIG_NF_CONNTRACK_PPTP is not set # CONFIG_NF_CONNTRACK_SANE is not set # CONFIG_NF_CONNTRACK_SIP is not set # CONFIG_NF_CONNTRACK_TFTP is not set # CONFIG_NF_CT_NETLINK is not set CONFIG_NF_NAT=m CONFIG_NF_NAT_MASQUERADE=y # CONFIG_NF_TABLES is not set CONFIG_NETFILTER_XTABLES=m # # Xtables combined modules # CONFIG_NETFILTER_XT_MARK=m # CONFIG_NETFILTER_XT_CONNMARK is not set # # Xtables targets # CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m # CONFIG_NETFILTER_XT_TARGET_CONNMARK is not set # CONFIG_NETFILTER_XT_TARGET_HMARK is not set CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m # CONFIG_NETFILTER_XT_TARGET_LOG is not set CONFIG_NETFILTER_XT_TARGET_MARK=m CONFIG_NETFILTER_XT_NAT=m # CONFIG_NETFILTER_XT_TARGET_NETMAP is not set # CONFIG_NETFILTER_XT_TARGET_NFLOG is not set # CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set # CONFIG_NETFILTER_XT_TARGET_RATEEST is not set # CONFIG_NETFILTER_XT_TARGET_REDIRECT is not set CONFIG_NETFILTER_XT_TARGET_MASQUERADE=m # CONFIG_NETFILTER_XT_TARGET_TEE is not set # CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set # # Xtables matches # # CONFIG_NETFILTER_XT_MATCH_ADDRTYPE is not set # CONFIG_NETFILTER_XT_MATCH_BPF is not set # CONFIG_NETFILTER_XT_MATCH_CGROUP is not set # CONFIG_NETFILTER_XT_MATCH_CLUSTER is not set CONFIG_NETFILTER_XT_MATCH_COMMENT=m # CONFIG_NETFILTER_XT_MATCH_CONNBYTES is not set # CONFIG_NETFILTER_XT_MATCH_CONNLABEL is not set # CONFIG_NETFILTER_XT_MATCH_CONNLIMIT is not set # CONFIG_NETFILTER_XT_MATCH_CONNMARK is not set # CONFIG_NETFILTER_XT_MATCH_CONNTRACK is not set CONFIG_NETFILTER_XT_MATCH_CPU=m # CONFIG_NETFILTER_XT_MATCH_DCCP is not set # CONFIG_NETFILTER_XT_MATCH_DEVGROUP is not set # CONFIG_NETFILTER_XT_MATCH_DSCP is not set # CONFIG_NETFILTER_XT_MATCH_ECN is not set # CONFIG_NETFILTER_XT_MATCH_ESP is not set # CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set # CONFIG_NETFILTER_XT_MATCH_HELPER is not set # CONFIG_NETFILTER_XT_MATCH_HL is not set # CONFIG_NETFILTER_XT_MATCH_IPCOMP is not set CONFIG_NETFILTER_XT_MATCH_IPRANGE=m # CONFIG_NETFILTER_XT_MATCH_L2TP is not set CONFIG_NETFILTER_XT_MATCH_LENGTH=m CONFIG_NETFILTER_XT_MATCH_LIMIT=m CONFIG_NETFILTER_XT_MATCH_MAC=m CONFIG_NETFILTER_XT_MATCH_MARK=m CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m # CONFIG_NETFILTER_XT_MATCH_NFACCT is not set # CONFIG_NETFILTER_XT_MATCH_OSF is not set # CONFIG_NETFILTER_XT_MATCH_OWNER is not set CONFIG_NETFILTER_XT_MATCH_POLICY=m # CONFIG_NETFILTER_XT_MATCH_PHYSDEV is not set CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m # CONFIG_NETFILTER_XT_MATCH_QUOTA is not set # CONFIG_NETFILTER_XT_MATCH_RATEEST is not set # CONFIG_NETFILTER_XT_MATCH_REALM is not set # CONFIG_NETFILTER_XT_MATCH_RECENT is not set CONFIG_NETFILTER_XT_MATCH_SCTP=m # CONFIG_NETFILTER_XT_MATCH_SOCKET is not set # CONFIG_NETFILTER_XT_MATCH_STATE is not set # CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set # CONFIG_NETFILTER_XT_MATCH_STRING is not set # CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set # CONFIG_NETFILTER_XT_MATCH_TIME is not set # CONFIG_NETFILTER_XT_MATCH_U32 is not set # end of Core Netfilter Configuration # CONFIG_IP_SET is not set # CONFIG_IP_VS is not set # # IP: Netfilter Configuration # CONFIG_NF_DEFRAG_IPV4=m # CONFIG_NF_SOCKET_IPV4 is not set # CONFIG_NF_TPROXY_IPV4 is not set # CONFIG_NF_DUP_IPV4 is not set # CONFIG_NF_LOG_ARP is not set # CONFIG_NF_LOG_IPV4 is not set # CONFIG_NF_REJECT_IPV4 is not set CONFIG_IP_NF_IPTABLES=m # CONFIG_IP_NF_MATCH_AH is not set # CONFIG_IP_NF_MATCH_ECN is not set # CONFIG_IP_NF_MATCH_TTL is not set CONFIG_IP_NF_FILTER=m # CONFIG_IP_NF_TARGET_REJECT is not set # CONFIG_IP_NF_TARGET_SYNPROXY is not set CONFIG_IP_NF_NAT=m CONFIG_IP_NF_TARGET_MASQUERADE=m # CONFIG_IP_NF_TARGET_NETMAP is not set # CONFIG_IP_NF_TARGET_REDIRECT is not set # CONFIG_IP_NF_MANGLE is not set # CONFIG_IP_NF_RAW is not set CONFIG_IP_NF_ARPTABLES=m CONFIG_IP_NF_ARPFILTER=m CONFIG_IP_NF_ARP_MANGLE=m # end of IP: Netfilter Configuration # CONFIG_NF_CONNTRACK_BRIDGE is not set CONFIG_BRIDGE_NF_EBTABLES=m CONFIG_BRIDGE_EBT_BROUTE=m CONFIG_BRIDGE_EBT_T_FILTER=m CONFIG_BRIDGE_EBT_T_NAT=m CONFIG_BRIDGE_EBT_802_3=m CONFIG_BRIDGE_EBT_AMONG=m CONFIG_BRIDGE_EBT_ARP=m CONFIG_BRIDGE_EBT_IP=m CONFIG_BRIDGE_EBT_LIMIT=m CONFIG_BRIDGE_EBT_MARK=m CONFIG_BRIDGE_EBT_PKTTYPE=m CONFIG_BRIDGE_EBT_STP=m CONFIG_BRIDGE_EBT_VLAN=m CONFIG_BRIDGE_EBT_ARPREPLY=m CONFIG_BRIDGE_EBT_DNAT=m CONFIG_BRIDGE_EBT_MARK_T=m CONFIG_BRIDGE_EBT_REDIRECT=m CONFIG_BRIDGE_EBT_SNAT=m CONFIG_BRIDGE_EBT_LOG=m CONFIG_BRIDGE_EBT_NFLOG=m # CONFIG_BPFILTER is not set # CONFIG_IP_DCCP is not set CONFIG_IP_SCTP=m # CONFIG_SCTP_DBG_OBJCNT is not set CONFIG_SCTP_DEFAULT_COOKIE_HMAC_MD5=y # CONFIG_SCTP_DEFAULT_COOKIE_HMAC_SHA1 is not set # CONFIG_SCTP_DEFAULT_COOKIE_HMAC_NONE is not set CONFIG_SCTP_COOKIE_HMAC_MD5=y # CONFIG_SCTP_COOKIE_HMAC_SHA1 is not set CONFIG_INET_SCTP_DIAG=m # CONFIG_RDS is not set # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_L2TP is not set CONFIG_STP=m CONFIG_BRIDGE=m CONFIG_BRIDGE_IGMP_SNOOPING=y # CONFIG_BRIDGE_VLAN_FILTERING is not set # CONFIG_BRIDGE_MRP is not set # CONFIG_BRIDGE_CFM is not set CONFIG_NET_DSA=m # CONFIG_NET_DSA_TAG_AR9331 is not set # CONFIG_NET_DSA_TAG_BRCM is not set # CONFIG_NET_DSA_TAG_BRCM_LEGACY is not set # CONFIG_NET_DSA_TAG_BRCM_PREPEND is not set # CONFIG_NET_DSA_TAG_HELLCREEK is not set # CONFIG_NET_DSA_TAG_GSWIP is not set # CONFIG_NET_DSA_TAG_DSA is not set # CONFIG_NET_DSA_TAG_EDSA is not set # CONFIG_NET_DSA_TAG_MTK is not set # CONFIG_NET_DSA_TAG_KSZ is not set # CONFIG_NET_DSA_TAG_OCELOT is not set # CONFIG_NET_DSA_TAG_OCELOT_8021Q is not set # CONFIG_NET_DSA_TAG_QCA is not set # CONFIG_NET_DSA_TAG_RTL4_A is not set # CONFIG_NET_DSA_TAG_RTL8_4 is not set # CONFIG_NET_DSA_TAG_RZN1_A5PSW is not set # CONFIG_NET_DSA_TAG_LAN9303 is not set # CONFIG_NET_DSA_TAG_SJA1105 is not set # CONFIG_NET_DSA_TAG_TRAILER is not set # CONFIG_NET_DSA_TAG_XRS700X is not set CONFIG_VLAN_8021Q=m # CONFIG_VLAN_8021Q_GVRP is not set # CONFIG_VLAN_8021Q_MVRP is not set CONFIG_LLC=m # CONFIG_LLC2 is not set # CONFIG_ATALK is not set # CONFIG_X25 is not set # CONFIG_LAPB is not set # CONFIG_PHONET is not set # CONFIG_IEEE802154 is not set CONFIG_NET_SCHED=y # # Queueing/Scheduling # CONFIG_NET_SCH_HTB=m CONFIG_NET_SCH_HFSC=m CONFIG_NET_SCH_PRIO=m CONFIG_NET_SCH_MULTIQ=m CONFIG_NET_SCH_RED=m CONFIG_NET_SCH_SFB=m CONFIG_NET_SCH_SFQ=m CONFIG_NET_SCH_TEQL=m CONFIG_NET_SCH_TBF=m # CONFIG_NET_SCH_CBS is not set # CONFIG_NET_SCH_ETF is not set # CONFIG_NET_SCH_TAPRIO is not set CONFIG_NET_SCH_GRED=m CONFIG_NET_SCH_NETEM=m CONFIG_NET_SCH_DRR=m CONFIG_NET_SCH_MQPRIO=m # CONFIG_NET_SCH_SKBPRIO is not set CONFIG_NET_SCH_CHOKE=m CONFIG_NET_SCH_QFQ=m CONFIG_NET_SCH_CODEL=m CONFIG_NET_SCH_FQ_CODEL=m # CONFIG_NET_SCH_CAKE is not set # CONFIG_NET_SCH_FQ is not set # CONFIG_NET_SCH_HHF is not set # CONFIG_NET_SCH_PIE is not set CONFIG_NET_SCH_INGRESS=m # CONFIG_NET_SCH_PLUG is not set # CONFIG_NET_SCH_ETS is not set # CONFIG_NET_SCH_DEFAULT is not set # # Classification # CONFIG_NET_CLS=y CONFIG_NET_CLS_BASIC=m CONFIG_NET_CLS_ROUTE4=m CONFIG_NET_CLS_FW=m CONFIG_NET_CLS_U32=m # CONFIG_CLS_U32_PERF is not set CONFIG_CLS_U32_MARK=y CONFIG_NET_CLS_FLOW=m # CONFIG_NET_CLS_CGROUP is not set # CONFIG_NET_CLS_BPF is not set # CONFIG_NET_CLS_FLOWER is not set # CONFIG_NET_CLS_MATCHALL is not set CONFIG_NET_EMATCH=y CONFIG_NET_EMATCH_STACK=32 CONFIG_NET_EMATCH_CMP=m CONFIG_NET_EMATCH_NBYTE=m CONFIG_NET_EMATCH_U32=m CONFIG_NET_EMATCH_META=m CONFIG_NET_EMATCH_TEXT=m # CONFIG_NET_EMATCH_CANID is not set # CONFIG_NET_EMATCH_IPT is not set CONFIG_NET_CLS_ACT=y CONFIG_NET_ACT_POLICE=m CONFIG_NET_ACT_GACT=m CONFIG_GACT_PROB=y CONFIG_NET_ACT_MIRRED=m # CONFIG_NET_ACT_SAMPLE is not set CONFIG_NET_ACT_IPT=m CONFIG_NET_ACT_NAT=m CONFIG_NET_ACT_PEDIT=m CONFIG_NET_ACT_SIMP=m CONFIG_NET_ACT_SKBEDIT=m CONFIG_NET_ACT_CSUM=m # CONFIG_NET_ACT_MPLS is not set # CONFIG_NET_ACT_VLAN is not set # CONFIG_NET_ACT_BPF is not set # CONFIG_NET_ACT_SKBMOD is not set # CONFIG_NET_ACT_IFE is not set # CONFIG_NET_ACT_TUNNEL_KEY is not set # CONFIG_NET_ACT_GATE is not set # CONFIG_NET_TC_SKB_EXT is not set CONFIG_NET_SCH_FIFO=y # CONFIG_DCB is not set CONFIG_DNS_RESOLVER=y # CONFIG_BATMAN_ADV is not set # CONFIG_OPENVSWITCH is not set # CONFIG_VSOCKETS is not set # CONFIG_NETLINK_DIAG is not set # CONFIG_MPLS is not set # CONFIG_NET_NSH is not set # CONFIG_HSR is not set CONFIG_NET_SWITCHDEV=y # CONFIG_NET_L3_MASTER_DEV is not set # CONFIG_QRTR is not set # CONFIG_NET_NCSI is not set CONFIG_PCPU_DEV_REFCNT=y CONFIG_RPS=y CONFIG_RFS_ACCEL=y CONFIG_SOCK_RX_QUEUE_MAPPING=y CONFIG_XPS=y # CONFIG_CGROUP_NET_PRIO is not set # CONFIG_CGROUP_NET_CLASSID is not set CONFIG_NET_RX_BUSY_POLL=y CONFIG_BQL=y CONFIG_NET_FLOW_LIMIT=y # # Network testing # # CONFIG_NET_PKTGEN is not set # end of Network testing # end of Networking options # CONFIG_HAMRADIO is not set CONFIG_CAN=m CONFIG_CAN_RAW=m CONFIG_CAN_BCM=m CONFIG_CAN_GW=m # CONFIG_CAN_J1939 is not set # CONFIG_CAN_ISOTP is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set # CONFIG_AF_KCM is not set # CONFIG_MCTP is not set # CONFIG_WIRELESS is not set # CONFIG_RFKILL is not set # CONFIG_NET_9P is not set # CONFIG_CAIF is not set # CONFIG_CEPH_LIB is not set # CONFIG_NFC is not set # CONFIG_PSAMPLE is not set # CONFIG_NET_IFE is not set # CONFIG_LWTUNNEL is not set CONFIG_DST_CACHE=y CONFIG_GRO_CELLS=y CONFIG_NET_SELFTESTS=y CONFIG_NET_DEVLINK=y CONFIG_FAILOVER=y CONFIG_ETHTOOL_NETLINK=y # # Device Drivers # CONFIG_HAVE_PCI=y # CONFIG_PCI is not set # CONFIG_PCCARD is not set # # Generic Driver Options # CONFIG_UEVENT_HELPER=y CONFIG_UEVENT_HELPER_PATH="" CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y # CONFIG_DEVTMPFS_SAFE is not set CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y # # Firmware loader # CONFIG_FW_LOADER=y CONFIG_EXTRA_FIRMWARE="" # CONFIG_FW_LOADER_USER_HELPER is not set # CONFIG_FW_LOADER_COMPRESS is not set # CONFIG_FW_UPLOAD is not set # end of Firmware loader CONFIG_WANT_DEV_COREDUMP=y CONFIG_ALLOW_DEV_COREDUMP=y CONFIG_DEV_COREDUMP=y # CONFIG_DEBUG_DRIVER is not set # CONFIG_DEBUG_DEVRES is not set # CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set # CONFIG_TEST_ASYNC_DRIVER_PROBE is not set CONFIG_GENERIC_CPU_AUTOPROBE=y CONFIG_GENERIC_CPU_VULNERABILITIES=y CONFIG_SOC_BUS=y CONFIG_REGMAP=y CONFIG_REGMAP_I2C=y CONFIG_REGMAP_SPI=y CONFIG_REGMAP_MMIO=y CONFIG_REGMAP_IRQ=y CONFIG_DMA_SHARED_BUFFER=y # CONFIG_DMA_FENCE_TRACE is not set CONFIG_GENERIC_ARCH_TOPOLOGY=y # end of Generic Driver Options # # Bus devices # # CONFIG_BRCMSTB_GISB_ARB is not set # CONFIG_MOXTET is not set # CONFIG_VEXPRESS_CONFIG is not set # CONFIG_MHI_BUS is not set # CONFIG_MHI_BUS_EP is not set # end of Bus devices # CONFIG_CONNECTOR is not set # # Firmware Drivers # # # ARM System Control and Management Interface Protocol # # CONFIG_ARM_SCMI_PROTOCOL is not set # end of ARM System Control and Management Interface Protocol # CONFIG_ARM_SCPI_PROTOCOL is not set # CONFIG_FIRMWARE_MEMMAP is not set # CONFIG_FW_CFG_SYSFS is not set CONFIG_TI_SCI_PROTOCOL=y # CONFIG_TRUSTED_FOUNDATIONS is not set # CONFIG_GOOGLE_FIRMWARE is not set CONFIG_ARM_PSCI_FW=y # CONFIG_ARM_PSCI_CHECKER is not set CONFIG_HAVE_ARM_SMCCC=y CONFIG_HAVE_ARM_SMCCC_DISCOVERY=y CONFIG_ARM_SMCCC_SOC_ID=y # # Tegra firmware driver # # end of Tegra firmware driver # end of Firmware Drivers # CONFIG_GNSS is not set CONFIG_MTD=y CONFIG_MTD_TESTS=m # # Partition parsers # # CONFIG_MTD_AR7_PARTS is not set CONFIG_MTD_CMDLINE_PARTS=y CONFIG_MTD_OF_PARTS=y # CONFIG_MTD_AFS_PARTS is not set # CONFIG_MTD_REDBOOT_PARTS is not set # end of Partition parsers # # User Modules And Translation Layers # CONFIG_MTD_BLKDEVS=y CONFIG_MTD_BLOCK=y # # Note that in some cases UBI block is preferred. See MTD_UBI_BLOCK. # # CONFIG_FTL is not set # CONFIG_NFTL is not set # CONFIG_INFTL is not set # CONFIG_RFD_FTL is not set # CONFIG_SSFDC is not set # CONFIG_SM_FTL is not set # CONFIG_MTD_OOPS is not set # CONFIG_MTD_PARTITIONED_MASTER is not set # # RAM/ROM/Flash chip drivers # CONFIG_MTD_CFI=y # CONFIG_MTD_JEDECPROBE is not set CONFIG_MTD_GEN_PROBE=y # CONFIG_MTD_CFI_ADV_OPTIONS is not set CONFIG_MTD_MAP_BANK_WIDTH_1=y CONFIG_MTD_MAP_BANK_WIDTH_2=y CONFIG_MTD_MAP_BANK_WIDTH_4=y CONFIG_MTD_CFI_I1=y CONFIG_MTD_CFI_I2=y # CONFIG_MTD_CFI_INTELEXT is not set CONFIG_MTD_CFI_AMDSTD=y # CONFIG_MTD_CFI_STAA is not set CONFIG_MTD_CFI_UTIL=y # CONFIG_MTD_RAM is not set CONFIG_MTD_ROM=y # CONFIG_MTD_ABSENT is not set # end of RAM/ROM/Flash chip drivers # # Mapping drivers for chip access # CONFIG_MTD_COMPLEX_MAPPINGS=y CONFIG_MTD_PHYSMAP=y # CONFIG_MTD_PHYSMAP_COMPAT is not set CONFIG_MTD_PHYSMAP_OF=y # CONFIG_MTD_PHYSMAP_VERSATILE is not set # CONFIG_MTD_PHYSMAP_GEMINI is not set # CONFIG_MTD_PHYSMAP_IXP4XX is not set # CONFIG_MTD_PHYSMAP_GPIO_ADDR is not set # CONFIG_MTD_PLATRAM is not set # end of Mapping drivers for chip access # # Self-contained MTD device drivers # # CONFIG_MTD_DATAFLASH is not set # CONFIG_MTD_MCHP23K256 is not set # CONFIG_MTD_MCHP48L640 is not set # CONFIG_MTD_SST25L is not set # CONFIG_MTD_BCM47XXSFLASH is not set # CONFIG_MTD_SLRAM is not set # CONFIG_MTD_PHRAM is not set # CONFIG_MTD_MTDRAM is not set # CONFIG_MTD_BLOCK2MTD is not set # # Disk-On-Chip Device Drivers # # CONFIG_MTD_DOCG3 is not set # end of Self-contained MTD device drivers # # NAND # # CONFIG_MTD_ONENAND is not set # CONFIG_MTD_RAW_NAND is not set # CONFIG_MTD_SPI_NAND is not set # # ECC engine support # # CONFIG_MTD_NAND_ECC_SW_HAMMING is not set # CONFIG_MTD_NAND_ECC_SW_BCH is not set # CONFIG_MTD_NAND_ECC_MXIC is not set # end of ECC engine support # end of NAND # # LPDDR & LPDDR2 PCM memory drivers # # CONFIG_MTD_LPDDR is not set # CONFIG_MTD_LPDDR2_NVM is not set # end of LPDDR & LPDDR2 PCM memory drivers CONFIG_MTD_SPI_NOR=y # CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set # CONFIG_MTD_SPI_NOR_SWP_DISABLE is not set CONFIG_MTD_SPI_NOR_SWP_DISABLE_ON_VOLATILE=y # CONFIG_MTD_SPI_NOR_SWP_KEEP is not set CONFIG_MTD_UBI=y CONFIG_MTD_UBI_WL_THRESHOLD=4096 CONFIG_MTD_UBI_BEB_LIMIT=20 # CONFIG_MTD_UBI_FASTMAP is not set # CONFIG_MTD_UBI_GLUEBI is not set # CONFIG_MTD_UBI_BLOCK is not set CONFIG_MTD_HYPERBUS=y CONFIG_DTC=y CONFIG_OF=y # CONFIG_OF_UNITTEST is not set CONFIG_OF_FLATTREE=y CONFIG_OF_EARLY_FLATTREE=y CONFIG_OF_KOBJ=y CONFIG_OF_DYNAMIC=y CONFIG_OF_ADDRESS=y CONFIG_OF_IRQ=y CONFIG_OF_RESERVED_MEM=y CONFIG_OF_RESOLVE=y CONFIG_OF_OVERLAY=y CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y # CONFIG_PARPORT is not set CONFIG_BLK_DEV=y # CONFIG_BLK_DEV_NULL_BLK is not set # CONFIG_ZRAM is not set CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_LOOP_MIN_COUNT=8 # CONFIG_BLK_DEV_DRBD is not set # CONFIG_BLK_DEV_NBD is not set CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_COUNT=16 CONFIG_BLK_DEV_RAM_SIZE=131072 # CONFIG_ATA_OVER_ETH is not set CONFIG_VIRTIO_BLK=y # CONFIG_BLK_DEV_RBD is not set # CONFIG_BLK_DEV_UBLK is not set # # NVME Support # # CONFIG_NVME_FC is not set # CONFIG_NVME_TCP is not set # CONFIG_NVME_TARGET is not set # end of NVME Support # # Misc devices # CONFIG_AD525X_DPOT=y CONFIG_AD525X_DPOT_I2C=y CONFIG_AD525X_DPOT_SPI=y # CONFIG_DUMMY_IRQ is not set CONFIG_ICS932S401=y # CONFIG_ENCLOSURE_SERVICES is not set # CONFIG_APDS9802ALS is not set # CONFIG_ISL29003 is not set # CONFIG_ISL29020 is not set # CONFIG_SENSORS_TSL2550 is not set # CONFIG_SENSORS_BH1770 is not set # CONFIG_SENSORS_APDS990X is not set # CONFIG_HMC6352 is not set # CONFIG_DS1682 is not set # CONFIG_LATTICE_ECP3_CONFIG is not set CONFIG_SRAM=y CONFIG_SRAM_EXEC=y # CONFIG_XILINX_SDFEC is not set # CONFIG_OPEN_DICE is not set # CONFIG_VCPU_STALL_DETECTOR is not set CONFIG_DMA_BUF_PHYS=y # CONFIG_C2PORT is not set # # EEPROM support # CONFIG_EEPROM_AT24=m # CONFIG_EEPROM_AT25 is not set # CONFIG_EEPROM_LEGACY is not set # CONFIG_EEPROM_MAX6875 is not set CONFIG_EEPROM_93CX6=y # CONFIG_EEPROM_93XX46 is not set # CONFIG_EEPROM_IDT_89HPESX is not set # CONFIG_EEPROM_EE1004 is not set # end of EEPROM support # # Texas Instruments shared transport line discipline # # CONFIG_TI_ST is not set # end of Texas Instruments shared transport line discipline # CONFIG_SENSORS_LIS3_SPI is not set # CONFIG_SENSORS_LIS3_I2C is not set # CONFIG_ALTERA_STAPL is not set # CONFIG_ECHO is not set # CONFIG_PVPANIC is not set # end of Misc devices # # SCSI device support # CONFIG_SCSI_MOD=y # CONFIG_RAID_ATTRS is not set # CONFIG_SCSI is not set # end of SCSI device support # CONFIG_ATA is not set # CONFIG_MD is not set # CONFIG_TARGET_CORE is not set CONFIG_NETDEVICES=y CONFIG_NET_CORE=y # CONFIG_BONDING is not set # CONFIG_DUMMY is not set # CONFIG_WIREGUARD is not set # CONFIG_EQUALIZER is not set # CONFIG_IFB is not set # CONFIG_NET_TEAM is not set # CONFIG_MACVLAN is not set # CONFIG_IPVLAN is not set # CONFIG_VXLAN is not set # CONFIG_GENEVE is not set # CONFIG_BAREUDP is not set # CONFIG_GTP is not set # CONFIG_AMT is not set # CONFIG_MACSEC is not set # CONFIG_NETCONSOLE is not set # CONFIG_TUN is not set # CONFIG_TUN_VNET_CROSS_LE is not set # CONFIG_VETH is not set CONFIG_VIRTIO_NET=y # CONFIG_NLMON is not set # # Distributed Switch Architecture drivers # # CONFIG_B53 is not set # CONFIG_NET_DSA_BCM_SF2 is not set # CONFIG_NET_DSA_LOOP is not set # CONFIG_NET_DSA_LANTIQ_GSWIP is not set # CONFIG_NET_DSA_MT7530 is not set # CONFIG_NET_DSA_MV88E6060 is not set # CONFIG_NET_DSA_MICROCHIP_KSZ_COMMON is not set # CONFIG_NET_DSA_MV88E6XXX is not set # CONFIG_NET_DSA_AR9331 is not set # CONFIG_NET_DSA_QCA8K is not set # CONFIG_NET_DSA_SJA1105 is not set # CONFIG_NET_DSA_XRS700X_I2C is not set # CONFIG_NET_DSA_XRS700X_MDIO is not set # CONFIG_NET_DSA_REALTEK is not set # CONFIG_NET_DSA_SMSC_LAN9303_I2C is not set # CONFIG_NET_DSA_SMSC_LAN9303_MDIO is not set # CONFIG_NET_DSA_VITESSE_VSC73XX_SPI is not set # CONFIG_NET_DSA_VITESSE_VSC73XX_PLATFORM is not set # end of Distributed Switch Architecture drivers CONFIG_ETHERNET=y # CONFIG_NET_VENDOR_ALACRITECH is not set # CONFIG_ALTERA_TSE is not set # CONFIG_NET_VENDOR_AMAZON is not set # CONFIG_NET_VENDOR_AQUANTIA is not set # CONFIG_NET_VENDOR_ARC is not set # CONFIG_NET_VENDOR_ASIX is not set # CONFIG_NET_VENDOR_BROADCOM is not set # CONFIG_NET_VENDOR_CADENCE is not set # CONFIG_NET_VENDOR_CAVIUM is not set # CONFIG_NET_VENDOR_CIRRUS is not set # CONFIG_NET_VENDOR_CORTINA is not set # CONFIG_NET_VENDOR_DAVICOM is not set # CONFIG_DNET is not set # CONFIG_NET_VENDOR_ENGLEDER is not set # CONFIG_NET_VENDOR_EZCHIP is not set # CONFIG_NET_VENDOR_FARADAY is not set # CONFIG_NET_VENDOR_FUNGIBLE is not set # CONFIG_NET_VENDOR_GOOGLE is not set # CONFIG_NET_VENDOR_HISILICON is not set # CONFIG_NET_VENDOR_HUAWEI is not set # CONFIG_NET_VENDOR_INTEL is not set CONFIG_NET_VENDOR_ADI=y # CONFIG_ADIN1110 is not set # CONFIG_NET_VENDOR_LITEX is not set # CONFIG_NET_VENDOR_MARVELL is not set # CONFIG_NET_VENDOR_MELLANOX is not set # CONFIG_NET_VENDOR_MICREL is not set # CONFIG_NET_VENDOR_MICROCHIP is not set # CONFIG_NET_VENDOR_MICROSEMI is not set # CONFIG_NET_VENDOR_MICROSOFT is not set # CONFIG_NET_VENDOR_NI is not set CONFIG_NET_VENDOR_NATSEMI=y # CONFIG_NET_VENDOR_NETRONOME is not set # CONFIG_NET_VENDOR_8390 is not set # CONFIG_ETHOC is not set # CONFIG_NET_VENDOR_PENSANDO is not set # CONFIG_NET_VENDOR_QUALCOMM is not set # CONFIG_NET_VENDOR_RENESAS is not set # CONFIG_NET_VENDOR_ROCKER is not set # CONFIG_NET_VENDOR_SAMSUNG is not set # CONFIG_NET_VENDOR_SEEQ is not set # CONFIG_NET_VENDOR_SOLARFLARE is not set # CONFIG_NET_VENDOR_SMSC is not set # CONFIG_NET_VENDOR_SOCIONEXT is not set # CONFIG_NET_VENDOR_STMICRO is not set # CONFIG_NET_VENDOR_SYNOPSYS is not set CONFIG_NET_VENDOR_TI=y CONFIG_TI_DAVINCI_MDIO=y # CONFIG_TI_CPSW_PHY_SEL is not set CONFIG_TI_KEYSTONE_NETCP=y CONFIG_TI_KEYSTONE_NETCP_ETHSS=y # CONFIG_TI_PRUETH is not set CONFIG_TI_ICSS_IEP=m # CONFIG_NET_VENDOR_VERTEXCOM is not set # CONFIG_NET_VENDOR_VIA is not set # CONFIG_NET_VENDOR_WANGXUN is not set # CONFIG_NET_VENDOR_WIZNET is not set # CONFIG_NET_VENDOR_XILINX is not set CONFIG_PHYLINK=m CONFIG_PHYLIB=y CONFIG_SWPHY=y CONFIG_FIXED_PHY=y # CONFIG_SFP is not set # # MII PHY device drivers # # CONFIG_AMD_PHY is not set # CONFIG_ADIN_PHY is not set # CONFIG_ADIN1100_PHY is not set # CONFIG_AQUANTIA_PHY is not set # CONFIG_AX88796B_PHY is not set # CONFIG_BROADCOM_PHY is not set # CONFIG_BCM54140_PHY is not set # CONFIG_BCM7XXX_PHY is not set # CONFIG_BCM84881_PHY is not set # CONFIG_BCM87XX_PHY is not set # CONFIG_CICADA_PHY is not set # CONFIG_CORTINA_PHY is not set # CONFIG_DAVICOM_PHY is not set # CONFIG_ICPLUS_PHY is not set # CONFIG_LXT_PHY is not set # CONFIG_INTEL_XWAY_PHY is not set # CONFIG_LSI_ET1011C_PHY is not set # CONFIG_MARVELL_PHY is not set # CONFIG_MARVELL_10G_PHY is not set # CONFIG_MARVELL_88X2222_PHY is not set # CONFIG_MAXLINEAR_GPHY is not set # CONFIG_MEDIATEK_GE_PHY is not set # CONFIG_MICREL_PHY is not set # CONFIG_MICROCHIP_PHY is not set # CONFIG_MICROCHIP_T1_PHY is not set # CONFIG_MICROSEMI_PHY is not set # CONFIG_MOTORCOMM_PHY is not set # CONFIG_NATIONAL_PHY is not set # CONFIG_NXP_C45_TJA11XX_PHY is not set # CONFIG_NXP_TJA11XX_PHY is not set # CONFIG_AT803X_PHY is not set # CONFIG_QSEMI_PHY is not set # CONFIG_REALTEK_PHY is not set # CONFIG_RENESAS_PHY is not set # CONFIG_ROCKCHIP_PHY is not set # CONFIG_SMSC_PHY is not set # CONFIG_STE10XP is not set # CONFIG_TERANETICS_PHY is not set # CONFIG_DP83822_PHY is not set # CONFIG_DP83TC811_PHY is not set CONFIG_DP83848_PHY=y CONFIG_DP83867_PHY=y # CONFIG_DP83869_PHY is not set # CONFIG_DP83TD510_PHY is not set # CONFIG_VITESSE_PHY is not set # CONFIG_XILINX_GMII2RGMII is not set # CONFIG_MICREL_KS8995MA is not set # CONFIG_PSE_CONTROLLER is not set CONFIG_CAN_DEV=m # CONFIG_CAN_VCAN is not set # CONFIG_CAN_VXCAN is not set CONFIG_CAN_NETLINK=y CONFIG_CAN_CALC_BITTIMING=y CONFIG_CAN_RX_OFFLOAD=y # CONFIG_CAN_CAN327 is not set CONFIG_CAN_FLEXCAN=m # CONFIG_CAN_GRCAN is not set # CONFIG_CAN_SLCAN is not set # CONFIG_CAN_TI_HECC is not set CONFIG_CAN_C_CAN=m CONFIG_CAN_C_CAN_PLATFORM=m # CONFIG_CAN_CC770 is not set # CONFIG_CAN_CTUCANFD_PLATFORM is not set # CONFIG_CAN_IFI_CANFD is not set CONFIG_CAN_M_CAN=m # CONFIG_CAN_M_CAN_PLATFORM is not set # CONFIG_CAN_M_CAN_TCAN4X5X is not set # CONFIG_CAN_SJA1000 is not set # CONFIG_CAN_SOFTING is not set # # CAN SPI interfaces # # CONFIG_CAN_HI311X is not set CONFIG_CAN_MCP251X=m # CONFIG_CAN_MCP251XFD is not set # end of CAN SPI interfaces # CONFIG_CAN_DEBUG_DEVICES is not set CONFIG_MDIO_DEVICE=y CONFIG_MDIO_BUS=y CONFIG_FWNODE_MDIO=y CONFIG_OF_MDIO=y CONFIG_MDIO_DEVRES=y CONFIG_MDIO_BITBANG=y # CONFIG_MDIO_BCM_UNIMAC is not set # CONFIG_MDIO_GPIO is not set # CONFIG_MDIO_HISI_FEMAC is not set # CONFIG_MDIO_MSCC_MIIM is not set # CONFIG_MDIO_IPQ4019 is not set # CONFIG_MDIO_IPQ8064 is not set # # MDIO Multiplexers # # CONFIG_MDIO_BUS_MUX_GPIO is not set # CONFIG_MDIO_BUS_MUX_MULTIPLEXER is not set # CONFIG_MDIO_BUS_MUX_MMIOREG is not set # # PCS device drivers # # end of PCS device drivers # CONFIG_PPP is not set # CONFIG_SLIP is not set # # Host-side USB support is needed for USB Network Adapter support # # CONFIG_WLAN is not set # CONFIG_WAN is not set # # Wireless WAN # # CONFIG_WWAN is not set # end of Wireless WAN # CONFIG_NETDEVSIM is not set CONFIG_NET_FAILOVER=y # CONFIG_ISDN is not set # # Input device support # CONFIG_INPUT=y # CONFIG_INPUT_FF_MEMLESS is not set # CONFIG_INPUT_SPARSEKMAP is not set # CONFIG_INPUT_MATRIXKMAP is not set # # Userland interfaces # # CONFIG_INPUT_MOUSEDEV is not set # CONFIG_INPUT_JOYDEV is not set CONFIG_INPUT_EVDEV=y # CONFIG_INPUT_EVBUG is not set # # Input Device Drivers # # CONFIG_INPUT_KEYBOARD is not set # CONFIG_INPUT_MOUSE is not set # CONFIG_INPUT_JOYSTICK is not set # CONFIG_INPUT_TABLET is not set # CONFIG_INPUT_TOUCHSCREEN is not set CONFIG_INPUT_MISC=y # CONFIG_INPUT_AD714X is not set # CONFIG_INPUT_ATMEL_CAPTOUCH is not set # CONFIG_INPUT_BMA150 is not set # CONFIG_INPUT_E3X0_BUTTON is not set # CONFIG_INPUT_MMA8450 is not set # CONFIG_INPUT_GPIO_BEEPER is not set CONFIG_INPUT_GPIO_DECODER=m # CONFIG_INPUT_GPIO_VIBRA is not set CONFIG_INPUT_CPCAP_PWRBUTTON=m # CONFIG_INPUT_KXTJ9 is not set # CONFIG_INPUT_REGULATOR_HAPTIC is not set # CONFIG_INPUT_TPS65218_PWRBUTTON is not set # CONFIG_INPUT_TWL6040_VIBRA is not set # CONFIG_INPUT_UINPUT is not set # CONFIG_INPUT_PALMAS_PWRBUTTON is not set # CONFIG_INPUT_PCF8574 is not set # CONFIG_INPUT_PWM_BEEPER is not set # CONFIG_INPUT_PWM_VIBRA is not set # CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set # CONFIG_INPUT_DA7280_HAPTICS is not set CONFIG_INPUT_ADXL34X=m CONFIG_INPUT_ADXL34X_I2C=m CONFIG_INPUT_ADXL34X_SPI=m # CONFIG_INPUT_IBM_PANEL is not set # CONFIG_INPUT_IQS269A is not set # CONFIG_INPUT_IQS626A is not set # CONFIG_INPUT_IQS7222 is not set # CONFIG_INPUT_CMA3000 is not set # CONFIG_INPUT_DRV260X_HAPTICS is not set # CONFIG_INPUT_DRV2665_HAPTICS is not set # CONFIG_INPUT_DRV2667_HAPTICS is not set # CONFIG_RMI4_CORE is not set # # Hardware I/O ports # CONFIG_SERIO=y CONFIG_SERIO_SERPORT=y # CONFIG_SERIO_LIBPS2 is not set # CONFIG_SERIO_RAW is not set # CONFIG_SERIO_ALTERA_PS2 is not set # CONFIG_SERIO_PS2MULT is not set # CONFIG_SERIO_ARC_PS2 is not set # CONFIG_SERIO_APBPS2 is not set # CONFIG_SERIO_GPIO_PS2 is not set # CONFIG_USERIO is not set # CONFIG_GAMEPORT is not set # end of Hardware I/O ports # end of Input device support # # Character devices # CONFIG_TTY=y CONFIG_VT=y CONFIG_CONSOLE_TRANSLATIONS=y CONFIG_VT_CONSOLE=y CONFIG_HW_CONSOLE=y CONFIG_VT_HW_CONSOLE_BINDING=y CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 CONFIG_LDISC_AUTOLOAD=y # # Serial drivers # CONFIG_SERIAL_EARLYCON=y CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y CONFIG_SERIAL_8250_16550A_VARIANTS=y # CONFIG_SERIAL_8250_FINTEK is not set CONFIG_SERIAL_8250_CONSOLE=y CONFIG_SERIAL_8250_DMA=y CONFIG_SERIAL_8250_NR_UARTS=10 CONFIG_SERIAL_8250_RUNTIME_UARTS=10 CONFIG_SERIAL_8250_EXTENDED=y # CONFIG_SERIAL_8250_MANY_PORTS is not set CONFIG_SERIAL_8250_SHARE_IRQ=y # CONFIG_SERIAL_8250_DETECT_IRQ is not set # CONFIG_SERIAL_8250_RSA is not set CONFIG_SERIAL_8250_FSL=y # CONFIG_SERIAL_8250_DW is not set # CONFIG_SERIAL_8250_RT288X is not set # CONFIG_SERIAL_8250_PRUSS is not set CONFIG_SERIAL_OF_PLATFORM=y # # Non-8250 serial port support # # CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set # CONFIG_SERIAL_MAX3100 is not set # CONFIG_SERIAL_MAX310X is not set # CONFIG_SERIAL_UARTLITE is not set CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y # CONFIG_SERIAL_SIFIVE is not set # CONFIG_SERIAL_SCCNXP is not set # CONFIG_SERIAL_SC16IS7XX is not set # CONFIG_SERIAL_ALTERA_JTAGUART is not set # CONFIG_SERIAL_ALTERA_UART is not set # CONFIG_SERIAL_XILINX_PS_UART is not set # CONFIG_SERIAL_ARC is not set # CONFIG_SERIAL_FSL_LPUART is not set # CONFIG_SERIAL_FSL_LINFLEXUART is not set # CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set # CONFIG_SERIAL_ST_ASC is not set # CONFIG_SERIAL_SPRD is not set # end of Serial drivers CONFIG_SERIAL_MCTRL_GPIO=y # CONFIG_SERIAL_NONSTANDARD is not set # CONFIG_N_GSM is not set # CONFIG_NULL_TTY is not set CONFIG_HVC_DRIVER=y # CONFIG_HVC_DCC is not set # CONFIG_RPMSG_TTY is not set CONFIG_SERIAL_DEV_BUS=y CONFIG_SERIAL_DEV_CTRL_TTYPORT=y # CONFIG_TTY_PRINTK is not set CONFIG_VIRTIO_CONSOLE=y # CONFIG_IPMI_HANDLER is not set # CONFIG_IPMB_DEVICE_INTERFACE is not set CONFIG_HW_RANDOM=y # CONFIG_HW_RANDOM_TIMERIOMEM is not set # CONFIG_HW_RANDOM_BA431 is not set # CONFIG_HW_RANDOM_VIRTIO is not set CONFIG_HW_RANDOM_KEYSTONE=y # CONFIG_HW_RANDOM_CCTRNG is not set # CONFIG_HW_RANDOM_XIPHERA is not set CONFIG_HW_RANDOM_ARM_SMCCC_TRNG=y CONFIG_DEVMEM=y # CONFIG_TCG_TPM is not set # CONFIG_XILLYBUS is not set CONFIG_RANDOM_TRUST_CPU=y CONFIG_RANDOM_TRUST_BOOTLOADER=y # end of Character devices # # I2C support # CONFIG_I2C=y CONFIG_I2C_BOARDINFO=y CONFIG_I2C_COMPAT=y CONFIG_I2C_CHARDEV=y CONFIG_I2C_MUX=y # # Multiplexer I2C Chip support # CONFIG_I2C_ARB_GPIO_CHALLENGE=m # CONFIG_I2C_MUX_GPIO is not set # CONFIG_I2C_MUX_GPMUX is not set # CONFIG_I2C_MUX_LTC4306 is not set # CONFIG_I2C_MUX_PCA9541 is not set CONFIG_I2C_MUX_PCA954x=y CONFIG_I2C_MUX_PINCTRL=y # CONFIG_I2C_MUX_REG is not set CONFIG_I2C_DEMUX_PINCTRL=y # CONFIG_I2C_MUX_MLXCPLD is not set # end of Multiplexer I2C Chip support # CONFIG_I2C_ATR is not set CONFIG_I2C_HELPER_AUTO=y # # I2C Hardware Bus support # # # I2C system bus drivers (mostly embedded / system-on-chip) # # CONFIG_I2C_CBUS_GPIO is not set CONFIG_I2C_DAVINCI=y # CONFIG_I2C_DESIGNWARE_PLATFORM is not set CONFIG_I2C_EMEV2=m # CONFIG_I2C_GPIO is not set # CONFIG_I2C_OCORES is not set # CONFIG_I2C_PCA_PLATFORM is not set # CONFIG_I2C_RK3X is not set # CONFIG_I2C_SIMTEC is not set # CONFIG_I2C_XILINX is not set # # External I2C/SMBus adapter drivers # # CONFIG_I2C_TAOS_EVM is not set # # Other I2C/SMBus bus drivers # # CONFIG_I2C_VIRTIO is not set # end of I2C Hardware Bus support # CONFIG_I2C_STUB is not set CONFIG_I2C_SLAVE=y CONFIG_I2C_SLAVE_EEPROM=y # CONFIG_I2C_SLAVE_TESTUNIT is not set # CONFIG_I2C_DEBUG_CORE is not set # CONFIG_I2C_DEBUG_ALGO is not set # CONFIG_I2C_DEBUG_BUS is not set # end of I2C support # CONFIG_I3C is not set CONFIG_SPI=y # CONFIG_SPI_DEBUG is not set CONFIG_SPI_MASTER=y CONFIG_SPI_MEM=y # # SPI Master Controller Drivers # # CONFIG_SPI_ALTERA is not set # CONFIG_SPI_AXI_SPI_ENGINE is not set CONFIG_SPI_BITBANG=y # CONFIG_SPI_CADENCE is not set CONFIG_SPI_CADENCE_QUADSPI=y # CONFIG_SPI_CADENCE_XSPI is not set CONFIG_SPI_DAVINCI=y # CONFIG_SPI_DESIGNWARE is not set # CONFIG_SPI_NXP_FLEXSPI is not set CONFIG_SPI_GPIO=m # CONFIG_SPI_FSL_SPI is not set # CONFIG_SPI_MICROCHIP_CORE is not set # CONFIG_SPI_MICROCHIP_CORE_QSPI is not set # CONFIG_SPI_OC_TINY is not set # CONFIG_SPI_ROCKCHIP is not set # CONFIG_SPI_SC18IS602 is not set # CONFIG_SPI_SIFIVE is not set # CONFIG_SPI_MXIC is not set # CONFIG_SPI_XCOMM is not set # CONFIG_SPI_XILINX is not set # CONFIG_SPI_ZYNQMP_GQSPI is not set # CONFIG_SPI_AMD is not set # # SPI Multiplexer support # # CONFIG_SPI_MUX is not set # # SPI Protocol Masters # # CONFIG_SPI_SPIDEV is not set # CONFIG_SPI_LOOPBACK_TEST is not set # CONFIG_SPI_TLE62X0 is not set # CONFIG_SPI_SLAVE is not set CONFIG_SPI_DYNAMIC=y # CONFIG_SPMI is not set # CONFIG_HSI is not set CONFIG_PPS=y # CONFIG_PPS_DEBUG is not set # # PPS clients support # # CONFIG_PPS_CLIENT_KTIMER is not set # CONFIG_PPS_CLIENT_LDISC is not set # CONFIG_PPS_CLIENT_GPIO is not set # # PPS generators support # # # PTP clock support # # CONFIG_PTP_1588_CLOCK is not set CONFIG_PTP_1588_CLOCK_OPTIONAL=y # # Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. # # end of PTP clock support CONFIG_PINCTRL=y CONFIG_GENERIC_PINCTRL_GROUPS=y CONFIG_PINMUX=y CONFIG_GENERIC_PINMUX_FUNCTIONS=y CONFIG_PINCONF=y CONFIG_GENERIC_PINCONF=y # CONFIG_DEBUG_PINCTRL is not set # CONFIG_PINCTRL_CY8C95X0 is not set # CONFIG_PINCTRL_MCP23S08 is not set # CONFIG_PINCTRL_MICROCHIP_SGPIO is not set # CONFIG_PINCTRL_OCELOT is not set CONFIG_PINCTRL_PALMAS=y CONFIG_PINCTRL_SINGLE=y # CONFIG_PINCTRL_STMFX is not set # CONFIG_PINCTRL_SX150X is not set # # Renesas pinctrl drivers # # end of Renesas pinctrl drivers CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y CONFIG_GPIOLIB=y CONFIG_GPIOLIB_FASTPATH_LIMIT=512 CONFIG_OF_GPIO=y CONFIG_GPIOLIB_IRQCHIP=y CONFIG_DEBUG_GPIO=y CONFIG_GPIO_SYSFS=y CONFIG_GPIO_CDEV=y CONFIG_GPIO_CDEV_V1=y # # Memory mapped GPIO drivers # # CONFIG_GPIO_74XX_MMIO is not set # CONFIG_GPIO_ALTERA is not set # CONFIG_GPIO_CADENCE is not set CONFIG_GPIO_DAVINCI=y # CONFIG_GPIO_DWAPB is not set # CONFIG_GPIO_FTGPIO010 is not set # CONFIG_GPIO_GENERIC_PLATFORM is not set # CONFIG_GPIO_GRGPIO is not set # CONFIG_GPIO_HLWD is not set # CONFIG_GPIO_LOGICVC is not set # CONFIG_GPIO_MB86S7X is not set # CONFIG_GPIO_MPC8XXX is not set # CONFIG_GPIO_SIFIVE is not set CONFIG_GPIO_SYSCON=y # CONFIG_GPIO_XILINX is not set # CONFIG_GPIO_ZEVIO is not set # CONFIG_GPIO_AMD_FCH is not set # end of Memory mapped GPIO drivers # # I2C GPIO expanders # # CONFIG_GPIO_ADNP is not set # CONFIG_GPIO_GW_PLD is not set # CONFIG_GPIO_MAX7300 is not set # CONFIG_GPIO_MAX732X is not set CONFIG_GPIO_PCA953X=y CONFIG_GPIO_PCA953X_IRQ=y # CONFIG_GPIO_PCA9570 is not set CONFIG_GPIO_PCF857X=y CONFIG_GPIO_TPIC2810=m # end of I2C GPIO expanders # # MFD GPIO expanders # # CONFIG_HTC_EGPIO is not set # CONFIG_GPIO_LP873X is not set # CONFIG_GPIO_LP87565 is not set CONFIG_GPIO_PALMAS=y # CONFIG_GPIO_TPS65218 is not set # CONFIG_GPIO_TPS6586X is not set CONFIG_GPIO_TPS65910=y # CONFIG_GPIO_TWL6040 is not set # end of MFD GPIO expanders # # SPI GPIO expanders # # CONFIG_GPIO_74X164 is not set # CONFIG_GPIO_MAX3191X is not set # CONFIG_GPIO_MAX7301 is not set # CONFIG_GPIO_MC33880 is not set CONFIG_GPIO_PISOSR=m # CONFIG_GPIO_XRA1403 is not set # end of SPI GPIO expanders # # Virtual GPIO drivers # # CONFIG_GPIO_AGGREGATOR is not set # CONFIG_GPIO_MOCKUP is not set # CONFIG_GPIO_VIRTIO is not set # CONFIG_GPIO_SIM is not set # end of Virtual GPIO drivers CONFIG_W1=m # # 1-wire Bus Masters # # CONFIG_W1_MASTER_DS2482 is not set # CONFIG_W1_MASTER_DS1WM is not set # CONFIG_W1_MASTER_GPIO is not set # CONFIG_W1_MASTER_SGI is not set # end of 1-wire Bus Masters # # 1-wire Slaves # # CONFIG_W1_SLAVE_THERM is not set # CONFIG_W1_SLAVE_SMEM is not set # CONFIG_W1_SLAVE_DS2405 is not set # CONFIG_W1_SLAVE_DS2408 is not set # CONFIG_W1_SLAVE_DS2413 is not set # CONFIG_W1_SLAVE_DS2406 is not set # CONFIG_W1_SLAVE_DS2423 is not set # CONFIG_W1_SLAVE_DS2805 is not set # CONFIG_W1_SLAVE_DS2430 is not set # CONFIG_W1_SLAVE_DS2431 is not set # CONFIG_W1_SLAVE_DS2433 is not set # CONFIG_W1_SLAVE_DS2438 is not set # CONFIG_W1_SLAVE_DS250X is not set # CONFIG_W1_SLAVE_DS2780 is not set # CONFIG_W1_SLAVE_DS2781 is not set # CONFIG_W1_SLAVE_DS28E04 is not set # CONFIG_W1_SLAVE_DS28E17 is not set # end of 1-wire Slaves CONFIG_POWER_RESET=y # CONFIG_POWER_RESET_BRCMKONA is not set # CONFIG_POWER_RESET_BRCMSTB is not set CONFIG_POWER_RESET_GPIO=y CONFIG_POWER_RESET_GPIO_RESTART=y # CONFIG_POWER_RESET_LTC2952 is not set # CONFIG_POWER_RESET_REGULATOR is not set # CONFIG_POWER_RESET_RESTART is not set # CONFIG_POWER_RESET_VERSATILE is not set CONFIG_POWER_RESET_KEYSTONE=y # CONFIG_POWER_RESET_SYSCON is not set # CONFIG_POWER_RESET_SYSCON_POWEROFF is not set # CONFIG_SYSCON_REBOOT_MODE is not set # CONFIG_NVMEM_REBOOT_MODE is not set # CONFIG_POWER_SUPPLY is not set CONFIG_HWMON=y # CONFIG_HWMON_DEBUG_CHIP is not set # # Native drivers # # CONFIG_SENSORS_AD7314 is not set # CONFIG_SENSORS_AD7414 is not set # CONFIG_SENSORS_AD7418 is not set # CONFIG_SENSORS_ADM1021 is not set # CONFIG_SENSORS_ADM1025 is not set # CONFIG_SENSORS_ADM1026 is not set # CONFIG_SENSORS_ADM1029 is not set # CONFIG_SENSORS_ADM1031 is not set # CONFIG_SENSORS_ADM1177 is not set # CONFIG_SENSORS_ADM9240 is not set # CONFIG_SENSORS_ADT7310 is not set # CONFIG_SENSORS_ADT7410 is not set # CONFIG_SENSORS_ADT7411 is not set # CONFIG_SENSORS_ADT7462 is not set # CONFIG_SENSORS_ADT7470 is not set # CONFIG_SENSORS_ADT7475 is not set # CONFIG_SENSORS_AHT10 is not set # CONFIG_SENSORS_AS370 is not set # CONFIG_SENSORS_ASC7621 is not set # CONFIG_SENSORS_AXI_FAN_CONTROL is not set # CONFIG_SENSORS_ATXP1 is not set # CONFIG_SENSORS_DS620 is not set # CONFIG_SENSORS_DS1621 is not set # CONFIG_SENSORS_F71805F is not set # CONFIG_SENSORS_F71882FG is not set # CONFIG_SENSORS_F75375S is not set # CONFIG_SENSORS_FTSTEUTATES is not set # CONFIG_SENSORS_GL518SM is not set # CONFIG_SENSORS_GL520SM is not set # CONFIG_SENSORS_G760A is not set # CONFIG_SENSORS_G762 is not set # CONFIG_SENSORS_GPIO_FAN is not set # CONFIG_SENSORS_HIH6130 is not set CONFIG_SENSORS_IIO_HWMON=y # CONFIG_SENSORS_IT87 is not set # CONFIG_SENSORS_JC42 is not set # CONFIG_SENSORS_POWR1220 is not set # CONFIG_SENSORS_LINEAGE is not set # CONFIG_SENSORS_LTC2945 is not set # CONFIG_SENSORS_LTC2947_I2C is not set # CONFIG_SENSORS_LTC2947_SPI is not set # CONFIG_SENSORS_LTC2990 is not set # CONFIG_SENSORS_LTC2992 is not set # CONFIG_SENSORS_LTC4151 is not set # CONFIG_SENSORS_LTC4215 is not set # CONFIG_SENSORS_LTC4222 is not set # CONFIG_SENSORS_LTC4245 is not set # CONFIG_SENSORS_LTC4260 is not set # CONFIG_SENSORS_LTC4261 is not set # CONFIG_SENSORS_MAX1111 is not set # CONFIG_SENSORS_MAX127 is not set # CONFIG_SENSORS_MAX16065 is not set # CONFIG_SENSORS_MAX1619 is not set # CONFIG_SENSORS_MAX1668 is not set # CONFIG_SENSORS_MAX197 is not set # CONFIG_SENSORS_MAX31722 is not set # CONFIG_SENSORS_MAX31730 is not set # CONFIG_SENSORS_MAX31760 is not set # CONFIG_SENSORS_MAX6620 is not set # CONFIG_SENSORS_MAX6621 is not set # CONFIG_SENSORS_MAX6639 is not set # CONFIG_SENSORS_MAX6642 is not set # CONFIG_SENSORS_MAX6650 is not set # CONFIG_SENSORS_MAX6697 is not set # CONFIG_SENSORS_MAX31790 is not set # CONFIG_SENSORS_MCP3021 is not set # CONFIG_SENSORS_TC654 is not set # CONFIG_SENSORS_TPS23861 is not set # CONFIG_SENSORS_MR75203 is not set # CONFIG_SENSORS_ADCXX is not set # CONFIG_SENSORS_LM63 is not set # CONFIG_SENSORS_LM70 is not set # CONFIG_SENSORS_LM73 is not set CONFIG_SENSORS_LM75=y # CONFIG_SENSORS_LM77 is not set # CONFIG_SENSORS_LM78 is not set # CONFIG_SENSORS_LM80 is not set # CONFIG_SENSORS_LM83 is not set # CONFIG_SENSORS_LM85 is not set # CONFIG_SENSORS_LM87 is not set # CONFIG_SENSORS_LM90 is not set # CONFIG_SENSORS_LM92 is not set # CONFIG_SENSORS_LM93 is not set # CONFIG_SENSORS_LM95234 is not set # CONFIG_SENSORS_LM95241 is not set # CONFIG_SENSORS_LM95245 is not set # CONFIG_SENSORS_PC87360 is not set # CONFIG_SENSORS_PC87427 is not set # CONFIG_SENSORS_NTC_THERMISTOR is not set # CONFIG_SENSORS_NCT6683 is not set # CONFIG_SENSORS_NCT6775_I2C is not set # CONFIG_SENSORS_NCT7802 is not set # CONFIG_SENSORS_NCT7904 is not set # CONFIG_SENSORS_NPCM7XX is not set # CONFIG_SENSORS_OCC_P8_I2C is not set # CONFIG_SENSORS_PCF8591 is not set # CONFIG_PMBUS is not set # CONFIG_SENSORS_PWM_FAN is not set # CONFIG_SENSORS_SBTSI is not set # CONFIG_SENSORS_SBRMI is not set # CONFIG_SENSORS_SHT15 is not set # CONFIG_SENSORS_SHT21 is not set # CONFIG_SENSORS_SHT3x is not set # CONFIG_SENSORS_SHT4x is not set # CONFIG_SENSORS_SHTC1 is not set # CONFIG_SENSORS_DME1737 is not set # CONFIG_SENSORS_EMC1403 is not set # CONFIG_SENSORS_EMC2103 is not set # CONFIG_SENSORS_EMC2305 is not set # CONFIG_SENSORS_EMC6W201 is not set # CONFIG_SENSORS_SMSC47M1 is not set # CONFIG_SENSORS_SMSC47M192 is not set # CONFIG_SENSORS_SMSC47B397 is not set # CONFIG_SENSORS_SCH5627 is not set # CONFIG_SENSORS_SCH5636 is not set # CONFIG_SENSORS_STTS751 is not set # CONFIG_SENSORS_SMM665 is not set # CONFIG_SENSORS_ADC128D818 is not set # CONFIG_SENSORS_ADS7828 is not set # CONFIG_SENSORS_ADS7871 is not set # CONFIG_SENSORS_AMC6821 is not set # CONFIG_SENSORS_INA209 is not set # CONFIG_SENSORS_INA2XX is not set # CONFIG_SENSORS_INA238 is not set # CONFIG_SENSORS_INA3221 is not set # CONFIG_SENSORS_TC74 is not set # CONFIG_SENSORS_THMC50 is not set # CONFIG_SENSORS_TMP102 is not set # CONFIG_SENSORS_TMP103 is not set # CONFIG_SENSORS_TMP108 is not set # CONFIG_SENSORS_TMP401 is not set # CONFIG_SENSORS_TMP421 is not set # CONFIG_SENSORS_TMP464 is not set # CONFIG_SENSORS_TMP513 is not set # CONFIG_SENSORS_VT1211 is not set # CONFIG_SENSORS_W83773G is not set # CONFIG_SENSORS_W83781D is not set # CONFIG_SENSORS_W83791D is not set # CONFIG_SENSORS_W83792D is not set # CONFIG_SENSORS_W83793 is not set # CONFIG_SENSORS_W83795 is not set # CONFIG_SENSORS_W83L785TS is not set # CONFIG_SENSORS_W83L786NG is not set # CONFIG_SENSORS_W83627HF is not set # CONFIG_SENSORS_W83627EHF is not set CONFIG_THERMAL=y # CONFIG_THERMAL_NETLINK is not set # CONFIG_THERMAL_STATISTICS is not set CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 CONFIG_THERMAL_HWMON=y CONFIG_THERMAL_OF=y CONFIG_THERMAL_WRITABLE_TRIPS=y CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y # CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set # CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set CONFIG_THERMAL_GOV_FAIR_SHARE=y CONFIG_THERMAL_GOV_STEP_WISE=y CONFIG_THERMAL_GOV_BANG_BANG=y CONFIG_THERMAL_GOV_USER_SPACE=y CONFIG_CPU_THERMAL=y CONFIG_CPU_FREQ_THERMAL=y # CONFIG_DEVFREQ_THERMAL is not set CONFIG_THERMAL_EMULATION=y # CONFIG_THERMAL_MMIO is not set # CONFIG_GENERIC_ADC_THERMAL is not set CONFIG_WATCHDOG=y CONFIG_WATCHDOG_CORE=y # CONFIG_WATCHDOG_NOWAYOUT is not set CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED=y CONFIG_WATCHDOG_OPEN_TIMEOUT=0 # CONFIG_WATCHDOG_SYSFS is not set # CONFIG_WATCHDOG_HRTIMER_PRETIMEOUT is not set # # Watchdog Pretimeout Governors # # CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set # # Watchdog Device Drivers # # CONFIG_SOFT_WATCHDOG is not set # CONFIG_GPIO_WATCHDOG is not set # CONFIG_XILINX_WATCHDOG is not set # CONFIG_ZIIRAVE_WATCHDOG is not set # CONFIG_CADENCE_WATCHDOG is not set # CONFIG_FTWDT010_WATCHDOG is not set # CONFIG_DW_WATCHDOG is not set CONFIG_DAVINCI_WATCHDOG=m # CONFIG_MAX63XX_WATCHDOG is not set # CONFIG_ARM_SMC_WATCHDOG is not set # CONFIG_MEN_A21_WDT is not set CONFIG_SSB_POSSIBLE=y # CONFIG_SSB is not set CONFIG_BCMA_POSSIBLE=y CONFIG_BCMA=m CONFIG_BCMA_HOST_SOC=y CONFIG_BCMA_SFLASH=y CONFIG_BCMA_DRIVER_GMAC_CMN=y CONFIG_BCMA_DRIVER_GPIO=y # CONFIG_BCMA_DEBUG is not set # # Multifunction device drivers # CONFIG_MFD_CORE=y CONFIG_MFD_ACT8945A=y # CONFIG_MFD_AS3711 is not set # CONFIG_MFD_AS3722 is not set # CONFIG_PMIC_ADP5520 is not set # CONFIG_MFD_AAT2870_CORE is not set # CONFIG_MFD_ATMEL_FLEXCOM is not set # CONFIG_MFD_ATMEL_HLCDC is not set # CONFIG_MFD_BCM590XX is not set # CONFIG_MFD_BD9571MWV is not set # CONFIG_MFD_AXP20X_I2C is not set # CONFIG_MFD_MADERA is not set # CONFIG_MFD_ASIC3 is not set # CONFIG_PMIC_DA903X is not set # CONFIG_MFD_DA9052_SPI is not set # CONFIG_MFD_DA9052_I2C is not set # CONFIG_MFD_DA9055 is not set # CONFIG_MFD_DA9062 is not set # CONFIG_MFD_DA9063 is not set # CONFIG_MFD_DA9150 is not set # CONFIG_MFD_GATEWORKS_GSC is not set # CONFIG_MFD_MC13XXX_SPI is not set # CONFIG_MFD_MC13XXX_I2C is not set # CONFIG_MFD_MP2629 is not set # CONFIG_MFD_HI6421_PMIC is not set # CONFIG_HTC_PASIC3 is not set # CONFIG_HTC_I2CPLD is not set # CONFIG_MFD_IQS62X is not set # CONFIG_MFD_KEMPLD is not set # CONFIG_MFD_88PM800 is not set # CONFIG_MFD_88PM805 is not set # CONFIG_MFD_88PM860X is not set # CONFIG_MFD_MAX14577 is not set # CONFIG_MFD_MAX77620 is not set # CONFIG_MFD_MAX77650 is not set # CONFIG_MFD_MAX77686 is not set # CONFIG_MFD_MAX77693 is not set # CONFIG_MFD_MAX77714 is not set # CONFIG_MFD_MAX77843 is not set # CONFIG_MFD_MAX8907 is not set # CONFIG_MFD_MAX8925 is not set # CONFIG_MFD_MAX8997 is not set # CONFIG_MFD_MAX8998 is not set # CONFIG_MFD_MT6360 is not set # CONFIG_MFD_MT6370 is not set # CONFIG_MFD_MT6397 is not set # CONFIG_MFD_MENF21BMC is not set # CONFIG_MFD_OCELOT is not set # CONFIG_EZX_PCAP is not set CONFIG_MFD_CPCAP=y # CONFIG_MFD_NTXEC is not set # CONFIG_MFD_RETU is not set # CONFIG_MFD_PCF50633 is not set # CONFIG_MFD_PM8XXX is not set # CONFIG_MFD_SY7636A is not set # CONFIG_MFD_RT4831 is not set # CONFIG_MFD_RT5033 is not set # CONFIG_MFD_RT5120 is not set # CONFIG_MFD_RC5T583 is not set # CONFIG_MFD_RK808 is not set # CONFIG_MFD_RN5T618 is not set # CONFIG_MFD_SEC_CORE is not set # CONFIG_MFD_SI476X_CORE is not set # CONFIG_MFD_SM501 is not set # CONFIG_MFD_SKY81452 is not set # CONFIG_MFD_STMPE is not set CONFIG_MFD_SYSCON=y # CONFIG_MFD_LP3943 is not set # CONFIG_MFD_LP8788 is not set # CONFIG_MFD_TI_LMU is not set CONFIG_MFD_PALMAS=y # CONFIG_TPS6105X is not set # CONFIG_TPS65010 is not set # CONFIG_TPS6507X is not set # CONFIG_MFD_TPS65086 is not set CONFIG_MFD_TPS65090=y CONFIG_MFD_TPS65217=y CONFIG_MFD_TI_LP873X=y CONFIG_MFD_TI_LP87565=y CONFIG_MFD_TPS65218=y # CONFIG_MFD_TPS65219 is not set CONFIG_MFD_TPS6586X=y CONFIG_MFD_TPS65910=y # CONFIG_MFD_TPS65912_I2C is not set # CONFIG_MFD_TPS65912_SPI is not set # CONFIG_MFD_TPS6594_I2C is not set # CONFIG_MFD_TPS6594_SPI is not set # CONFIG_TWL4030_CORE is not set CONFIG_TWL6040_CORE=y # CONFIG_MFD_WL1273_CORE is not set # CONFIG_MFD_LM3533 is not set # CONFIG_MFD_TC3589X is not set # CONFIG_MFD_T7L66XB is not set # CONFIG_MFD_TC6387XB is not set # CONFIG_MFD_TC6393XB is not set # CONFIG_MFD_TQMX86 is not set # CONFIG_MFD_LOCHNAGAR is not set # CONFIG_MFD_ARIZONA_I2C is not set # CONFIG_MFD_ARIZONA_SPI is not set # CONFIG_MFD_WM8400 is not set # CONFIG_MFD_WM831X_I2C is not set # CONFIG_MFD_WM831X_SPI is not set # CONFIG_MFD_WM8350_I2C is not set # CONFIG_MFD_WM8994 is not set # CONFIG_MFD_ROHM_BD718XX is not set # CONFIG_MFD_ROHM_BD71828 is not set # CONFIG_MFD_ROHM_BD957XMUF is not set # CONFIG_MFD_STPMIC1 is not set # CONFIG_MFD_STMFX is not set # CONFIG_MFD_ATC260X_I2C is not set # CONFIG_MFD_QCOM_PM8008 is not set # CONFIG_RAVE_SP_CORE is not set # CONFIG_MFD_INTEL_M10_BMC is not set # CONFIG_MFD_RSMU_I2C is not set # CONFIG_MFD_RSMU_SPI is not set # end of Multifunction device drivers CONFIG_REGULATOR=y # CONFIG_REGULATOR_DEBUG is not set CONFIG_REGULATOR_FIXED_VOLTAGE=y # CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set # CONFIG_REGULATOR_USERSPACE_CONSUMER is not set # CONFIG_REGULATOR_88PG86X is not set CONFIG_REGULATOR_ACT8945A=y # CONFIG_REGULATOR_AD5398 is not set CONFIG_REGULATOR_CPCAP=y # CONFIG_REGULATOR_DA9121 is not set # CONFIG_REGULATOR_DA9210 is not set # CONFIG_REGULATOR_DA9211 is not set # CONFIG_REGULATOR_FAN53555 is not set # CONFIG_REGULATOR_FAN53880 is not set CONFIG_REGULATOR_GPIO=y # CONFIG_REGULATOR_ISL9305 is not set # CONFIG_REGULATOR_ISL6271A is not set # CONFIG_REGULATOR_LP3971 is not set # CONFIG_REGULATOR_LP3972 is not set # CONFIG_REGULATOR_LP872X is not set CONFIG_REGULATOR_LP873X=y # CONFIG_REGULATOR_LP8755 is not set CONFIG_REGULATOR_LP87565=y # CONFIG_REGULATOR_LTC3589 is not set # CONFIG_REGULATOR_LTC3676 is not set # CONFIG_REGULATOR_MAX1586 is not set # CONFIG_REGULATOR_MAX8649 is not set # CONFIG_REGULATOR_MAX8660 is not set # CONFIG_REGULATOR_MAX8893 is not set # CONFIG_REGULATOR_MAX8952 is not set # CONFIG_REGULATOR_MAX8973 is not set # CONFIG_REGULATOR_MAX20086 is not set # CONFIG_REGULATOR_MAX77826 is not set # CONFIG_REGULATOR_MCP16502 is not set # CONFIG_REGULATOR_MP5416 is not set # CONFIG_REGULATOR_MP8859 is not set # CONFIG_REGULATOR_MP886X is not set # CONFIG_REGULATOR_MPQ7920 is not set # CONFIG_REGULATOR_MT6311 is not set CONFIG_REGULATOR_PALMAS=y # CONFIG_REGULATOR_PCA9450 is not set # CONFIG_REGULATOR_PF8X00 is not set # CONFIG_REGULATOR_PFUZE100 is not set # CONFIG_REGULATOR_PV88060 is not set # CONFIG_REGULATOR_PV88080 is not set # CONFIG_REGULATOR_PV88090 is not set # CONFIG_REGULATOR_PWM is not set # CONFIG_REGULATOR_RT4801 is not set # CONFIG_REGULATOR_RT5190A is not set # CONFIG_REGULATOR_RT5759 is not set # CONFIG_REGULATOR_RT6160 is not set # CONFIG_REGULATOR_RT6245 is not set # CONFIG_REGULATOR_RTQ2134 is not set # CONFIG_REGULATOR_RTMV20 is not set # CONFIG_REGULATOR_RTQ6752 is not set # CONFIG_REGULATOR_SLG51000 is not set # CONFIG_REGULATOR_SY8106A is not set # CONFIG_REGULATOR_SY8824X is not set # CONFIG_REGULATOR_SY8827N is not set # CONFIG_REGULATOR_TPS51632 is not set CONFIG_REGULATOR_TPS62360=y # CONFIG_REGULATOR_TPS6286X is not set CONFIG_REGULATOR_TPS65023=y CONFIG_REGULATOR_TPS6507X=y CONFIG_REGULATOR_TPS65090=y # CONFIG_REGULATOR_TPS65132 is not set CONFIG_REGULATOR_TPS65217=y CONFIG_REGULATOR_TPS65218=y CONFIG_REGULATOR_TPS6524X=y CONFIG_REGULATOR_TPS6586X=y CONFIG_REGULATOR_TPS65910=y # CONFIG_REGULATOR_VCTRL is not set # CONFIG_RC_CORE is not set # # CEC support # # CONFIG_MEDIA_CEC_SUPPORT is not set # end of CEC support # CONFIG_MEDIA_SUPPORT is not set # # Graphics support # # CONFIG_IMX_IPUV3_CORE is not set # CONFIG_DRM is not set # CONFIG_DRM_DEBUG_MODESET_LOCK is not set # # ARM devices # # end of ARM devices # # Frame buffer Devices # # CONFIG_FB is not set # end of Frame buffer Devices # # Backlight & LCD device support # # CONFIG_LCD_CLASS_DEVICE is not set # CONFIG_BACKLIGHT_CLASS_DEVICE is not set # end of Backlight & LCD device support # # Console display driver support # CONFIG_DUMMY_CONSOLE=y # end of Console display driver support # end of Graphics support # CONFIG_SOUND is not set # # HID support # # CONFIG_HID is not set # # I2C HID support # # CONFIG_I2C_HID_OF is not set # CONFIG_I2C_HID_OF_ELAN is not set # CONFIG_I2C_HID_OF_GOODIX is not set # end of I2C HID support # end of HID support CONFIG_USB_OHCI_LITTLE_ENDIAN=y # CONFIG_USB_SUPPORT is not set # CONFIG_MMC is not set # CONFIG_MEMSTICK is not set # CONFIG_NEW_LEDS is not set # CONFIG_ACCESSIBILITY is not set # CONFIG_INFINIBAND is not set CONFIG_EDAC_ATOMIC_SCRUB=y CONFIG_EDAC_SUPPORT=y CONFIG_EDAC=y CONFIG_EDAC_LEGACY_SYSFS=y # CONFIG_EDAC_DEBUG is not set CONFIG_EDAC_TI=m CONFIG_RTC_LIB=y # CONFIG_RTC_CLASS is not set CONFIG_DMADEVICES=y # CONFIG_DMADEVICES_DEBUG is not set # # DMA Devices # CONFIG_DMA_ENGINE=y CONFIG_DMA_VIRTUAL_CHANNELS=y CONFIG_DMA_OF=y # CONFIG_ALTERA_MSGDMA is not set # CONFIG_DW_AXI_DMAC is not set # CONFIG_FSL_EDMA is not set # CONFIG_FSL_QDMA is not set # CONFIG_INTEL_IDMA64 is not set # CONFIG_NBPFAXI_DMA is not set # CONFIG_XILINX_ZYNQMP_DPDMA is not set # CONFIG_QCOM_HIDMA_MGMT is not set # CONFIG_QCOM_HIDMA is not set CONFIG_DW_DMAC_CORE=y CONFIG_DW_DMAC=y # CONFIG_SF_PDMA is not set CONFIG_TI_EDMA=y # # DMA Clients # # CONFIG_ASYNC_TX_DMA is not set # CONFIG_DMATEST is not set # # DMABUF options # CONFIG_SYNC_FILE=y # CONFIG_SW_SYNC is not set # CONFIG_UDMABUF is not set # CONFIG_DMABUF_MOVE_NOTIFY is not set # CONFIG_DMABUF_DEBUG is not set # CONFIG_DMABUF_SELFTESTS is not set # CONFIG_DMABUF_HEAPS is not set # CONFIG_DMABUF_SYSFS_STATS is not set # end of DMABUF options # CONFIG_AUXDISPLAY is not set CONFIG_UIO=m # CONFIG_UIO_PDRV_GENIRQ is not set # CONFIG_UIO_DMEM_GENIRQ is not set # CONFIG_UIO_PRUSS is not set # CONFIG_VFIO is not set # CONFIG_VIRT_DRIVERS is not set CONFIG_VIRTIO_ANCHOR=y CONFIG_VIRTIO=y CONFIG_VIRTIO_MENU=y # CONFIG_VIRTIO_BALLOON is not set # CONFIG_VIRTIO_INPUT is not set CONFIG_VIRTIO_MMIO=y # CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES is not set # CONFIG_VDPA is not set CONFIG_VHOST_MENU=y # CONFIG_VHOST_NET is not set # CONFIG_VHOST_CROSS_ENDIAN_LEGACY is not set # # Microsoft Hyper-V guest support # # end of Microsoft Hyper-V guest support # CONFIG_GREYBUS is not set # CONFIG_COMEDI is not set CONFIG_STAGING=y # # IIO staging drivers # # # Accelerometers # # CONFIG_ADIS16203 is not set # CONFIG_ADIS16240 is not set # end of Accelerometers # # Analog to digital converters # # CONFIG_AD7816 is not set # end of Analog to digital converters # # Analog digital bi-direction converters # # CONFIG_ADT7316 is not set # end of Analog digital bi-direction converters # # Direct Digital Synthesis # # CONFIG_AD9832 is not set # CONFIG_AD9834 is not set # end of Direct Digital Synthesis # # Network Analyzer, Impedance Converters # # CONFIG_AD5933 is not set # end of Network Analyzer, Impedance Converters # # Active energy metering IC # # CONFIG_ADE7854 is not set # end of Active energy metering IC # # Resolver to digital converters # # CONFIG_AD2S1210 is not set # end of Resolver to digital converters # end of IIO staging drivers # CONFIG_STAGING_MEDIA is not set CONFIG_STAGING_BOARD=y # CONFIG_PI433 is not set # CONFIG_XIL_AXIS_FIFO is not set # CONFIG_FIELDBUS_DEV is not set # CONFIG_GOLDFISH is not set # CONFIG_CHROME_PLATFORMS is not set # CONFIG_MELLANOX_PLATFORM is not set CONFIG_HAVE_CLK=y CONFIG_HAVE_CLK_PREPARE=y CONFIG_COMMON_CLK=y # # Clock driver for ARM Reference designs # # CONFIG_CLK_ICST is not set # CONFIG_CLK_SP810 is not set # end of Clock driver for ARM Reference designs # CONFIG_LMK04832 is not set # CONFIG_COMMON_CLK_MAX9485 is not set # CONFIG_COMMON_CLK_SI5341 is not set # CONFIG_COMMON_CLK_SI5351 is not set # CONFIG_COMMON_CLK_SI514 is not set # CONFIG_COMMON_CLK_SI544 is not set # CONFIG_COMMON_CLK_SI570 is not set # CONFIG_COMMON_CLK_CDCE706 is not set # CONFIG_COMMON_CLK_CDCE925 is not set # CONFIG_COMMON_CLK_CS2000_CP is not set # CONFIG_CLK_TWL6040 is not set # CONFIG_COMMON_CLK_AXI_CLKGEN is not set CONFIG_COMMON_CLK_PALMAS=y # CONFIG_COMMON_CLK_PWM is not set # CONFIG_COMMON_CLK_RS9_PCIE is not set # CONFIG_COMMON_CLK_VC5 is not set # CONFIG_COMMON_CLK_VC7 is not set # CONFIG_COMMON_CLK_FIXED_MMIO is not set CONFIG_COMMON_CLK_KEYSTONE=y CONFIG_TI_SCI_CLK=y # CONFIG_TI_SCI_CLK_PROBE_FROM_FW is not set CONFIG_TI_SYSCON_CLK=y # CONFIG_XILINX_VCU is not set # CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set CONFIG_HWSPINLOCK=y # # Clock Source drivers # CONFIG_TIMER_OF=y CONFIG_TIMER_PROBE=y CONFIG_CLKSRC_MMIO=y CONFIG_KEYSTONE_TIMER=y CONFIG_ARM_ARCH_TIMER=y CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y # CONFIG_MICROCHIP_PIT64B is not set # end of Clock Source drivers CONFIG_MAILBOX=y # CONFIG_PLATFORM_MHU is not set # CONFIG_ALTERA_MBOX is not set CONFIG_TI_MESSAGE_MANAGER=y # CONFIG_MAILBOX_TEST is not set CONFIG_IOMMU_SUPPORT=y # # Generic IOMMU Pagetable Support # # CONFIG_IOMMU_IO_PGTABLE_LPAE is not set # CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set # end of Generic IOMMU Pagetable Support # CONFIG_IOMMU_DEBUGFS is not set # CONFIG_ARM_SMMU is not set # # Remoteproc drivers # CONFIG_REMOTEPROC=y CONFIG_REMOTEPROC_CDEV=y CONFIG_KEYSTONE_REMOTEPROC=y CONFIG_PRU_REMOTEPROC=m # end of Remoteproc drivers # # Rpmsg drivers # CONFIG_RPMSG=y # CONFIG_RPMSG_CHAR is not set # CONFIG_RPMSG_CTRL is not set CONFIG_RPMSG_NS=m # CONFIG_RPMSG_QCOM_GLINK_RPM is not set CONFIG_RPMSG_VIRTIO=m # CONFIG_RPMSG_PRU is not set # end of Rpmsg drivers # # Rpmsg virtual device drivers # CONFIG_RPMSG_KDRV=y # CONFIG_RPMSG_KDRV_DEMO is not set CONFIG_RPMSG_KDRV_DISPLAY=y CONFIG_RPMSG_KDRV_ETH_SWITCH=m # end of Rpmsg virtual device drivers # CONFIG_SOUNDWIRE is not set # # SOC (System On Chip) specific Drivers # # # Amlogic SoC drivers # # end of Amlogic SoC drivers # # Broadcom SoC drivers # # CONFIG_SOC_BRCMSTB is not set # end of Broadcom SoC drivers # # NXP/Freescale QorIQ SoC drivers # # CONFIG_QUICC_ENGINE is not set # end of NXP/Freescale QorIQ SoC drivers # # fujitsu SoC drivers # # end of fujitsu SoC drivers # # i.MX SoC drivers # # end of i.MX SoC drivers # # Enable LiteX SoC Builder specific drivers # # CONFIG_LITEX_SOC_CONTROLLER is not set # end of Enable LiteX SoC Builder specific drivers # # Qualcomm SoC drivers # # end of Qualcomm SoC drivers CONFIG_SOC_TI=y CONFIG_KEYSTONE_NAVIGATOR_QMSS=y CONFIG_KEYSTONE_NAVIGATOR_DMA=y CONFIG_TI_SCI_PM_DOMAINS=y CONFIG_TI_PRUSS=m # # Xilinx SoC drivers # # end of Xilinx SoC drivers # end of SOC (System On Chip) specific Drivers CONFIG_PM_DEVFREQ=y # # DEVFREQ Governors # CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y # CONFIG_DEVFREQ_GOV_PERFORMANCE is not set # CONFIG_DEVFREQ_GOV_POWERSAVE is not set # CONFIG_DEVFREQ_GOV_USERSPACE is not set # CONFIG_DEVFREQ_GOV_PASSIVE is not set # # DEVFREQ Drivers # # CONFIG_PM_DEVFREQ_EVENT is not set CONFIG_EXTCON=y # # Extcon Device Drivers # # CONFIG_EXTCON_ADC_JACK is not set # CONFIG_EXTCON_FSA9480 is not set # CONFIG_EXTCON_GPIO is not set # CONFIG_EXTCON_MAX3355 is not set CONFIG_EXTCON_PALMAS=m # CONFIG_EXTCON_PTN5150 is not set # CONFIG_EXTCON_RT8973A is not set # CONFIG_EXTCON_SM5502 is not set CONFIG_EXTCON_USB_GPIO=m CONFIG_MEMORY=y CONFIG_TI_AEMIF=y # CONFIG_OMAP_GPMC is not set CONFIG_IIO=y CONFIG_IIO_BUFFER=y # CONFIG_IIO_BUFFER_CB is not set # CONFIG_IIO_BUFFER_DMA is not set # CONFIG_IIO_BUFFER_DMAENGINE is not set # CONFIG_IIO_BUFFER_HW_CONSUMER is not set CONFIG_IIO_KFIFO_BUF=y CONFIG_IIO_TRIGGERED_BUFFER=y CONFIG_IIO_CONFIGFS=y CONFIG_IIO_TRIGGER=y CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 # CONFIG_IIO_SW_DEVICE is not set CONFIG_IIO_SW_TRIGGER=y # CONFIG_IIO_TRIGGERED_EVENT is not set # # Accelerometers # # CONFIG_ADIS16201 is not set # CONFIG_ADIS16209 is not set # CONFIG_ADXL313_I2C is not set # CONFIG_ADXL313_SPI is not set # CONFIG_ADXL355_I2C is not set # CONFIG_ADXL355_SPI is not set # CONFIG_ADXL367_SPI is not set # CONFIG_ADXL367_I2C is not set # CONFIG_ADXL372_SPI is not set # CONFIG_ADXL372_I2C is not set # CONFIG_BMA180 is not set # CONFIG_BMA220 is not set # CONFIG_BMA400 is not set # CONFIG_BMC150_ACCEL is not set # CONFIG_BMI088_ACCEL is not set # CONFIG_DA280 is not set # CONFIG_DA311 is not set # CONFIG_DMARD06 is not set # CONFIG_DMARD09 is not set # CONFIG_DMARD10 is not set # CONFIG_FXLS8962AF_I2C is not set # CONFIG_FXLS8962AF_SPI is not set # CONFIG_IIO_ST_ACCEL_3AXIS is not set # CONFIG_KXSD9 is not set # CONFIG_KXCJK1013 is not set # CONFIG_MC3230 is not set # CONFIG_MMA7455_I2C is not set # CONFIG_MMA7455_SPI is not set # CONFIG_MMA7660 is not set # CONFIG_MMA8452 is not set # CONFIG_MMA9551 is not set # CONFIG_MMA9553 is not set # CONFIG_MSA311 is not set # CONFIG_MXC4005 is not set # CONFIG_MXC6255 is not set # CONFIG_SCA3000 is not set # CONFIG_SCA3300 is not set # CONFIG_STK8312 is not set # CONFIG_STK8BA50 is not set # end of Accelerometers # # Analog to digital converters # # CONFIG_AD7091R5 is not set # CONFIG_AD7124 is not set # CONFIG_AD7192 is not set # CONFIG_AD7266 is not set # CONFIG_AD7280 is not set # CONFIG_AD7291 is not set # CONFIG_AD7292 is not set # CONFIG_AD7298 is not set # CONFIG_AD7476 is not set # CONFIG_AD7606_IFACE_PARALLEL is not set # CONFIG_AD7606_IFACE_SPI is not set # CONFIG_AD7766 is not set # CONFIG_AD7768_1 is not set # CONFIG_AD7780 is not set # CONFIG_AD7791 is not set # CONFIG_AD7793 is not set # CONFIG_AD7887 is not set # CONFIG_AD7923 is not set # CONFIG_AD7949 is not set # CONFIG_AD799X is not set # CONFIG_ADI_AXI_ADC is not set # CONFIG_CC10001_ADC is not set CONFIG_CPCAP_ADC=m # CONFIG_ENVELOPE_DETECTOR is not set # CONFIG_HI8435 is not set # CONFIG_HX711 is not set # CONFIG_INA2XX_ADC is not set # CONFIG_LTC2471 is not set # CONFIG_LTC2485 is not set # CONFIG_LTC2496 is not set # CONFIG_LTC2497 is not set # CONFIG_MAX1027 is not set # CONFIG_MAX11100 is not set # CONFIG_MAX1118 is not set # CONFIG_MAX11205 is not set # CONFIG_MAX1241 is not set # CONFIG_MAX1363 is not set # CONFIG_MAX9611 is not set # CONFIG_MCP320X is not set # CONFIG_MCP3422 is not set # CONFIG_MCP3911 is not set # CONFIG_NAU7802 is not set # CONFIG_PALMAS_GPADC is not set # CONFIG_RICHTEK_RTQ6056 is not set # CONFIG_SD_ADC_MODULATOR is not set # CONFIG_TI_ADC081C is not set # CONFIG_TI_ADC0832 is not set # CONFIG_TI_ADC084S021 is not set # CONFIG_TI_ADC12138 is not set # CONFIG_TI_ADC108S102 is not set # CONFIG_TI_ADC128S052 is not set # CONFIG_TI_ADC161S626 is not set # CONFIG_TI_ADS1015 is not set # CONFIG_TI_ADS7950 is not set # CONFIG_TI_ADS8344 is not set # CONFIG_TI_ADS8688 is not set # CONFIG_TI_ADS124S08 is not set # CONFIG_TI_ADS131E08 is not set # CONFIG_TI_TLC4541 is not set # CONFIG_TI_TSC2046 is not set CONFIG_VF610_ADC=m # CONFIG_XILINX_XADC is not set # end of Analog to digital converters # # Analog to digital and digital to analog converters # # CONFIG_AD74413R is not set # end of Analog to digital and digital to analog converters # # Analog Front Ends # # CONFIG_IIO_RESCALE is not set # end of Analog Front Ends # # Amplifiers # # CONFIG_AD8366 is not set # CONFIG_ADA4250 is not set # CONFIG_HMC425 is not set # end of Amplifiers # # Capacitance to digital converters # # CONFIG_AD7150 is not set # CONFIG_AD7746 is not set # end of Capacitance to digital converters # # Chemical Sensors # # CONFIG_ATLAS_PH_SENSOR is not set # CONFIG_ATLAS_EZO_SENSOR is not set # CONFIG_BME680 is not set # CONFIG_CCS811 is not set # CONFIG_IAQCORE is not set # CONFIG_PMS7003 is not set # CONFIG_SCD30_CORE is not set # CONFIG_SCD4X is not set # CONFIG_SENSIRION_SGP30 is not set # CONFIG_SENSIRION_SGP40 is not set # CONFIG_SPS30_I2C is not set # CONFIG_SPS30_SERIAL is not set # CONFIG_SENSEAIR_SUNRISE_CO2 is not set # CONFIG_VZ89X is not set # end of Chemical Sensors # # Hid Sensor IIO Common # # end of Hid Sensor IIO Common # # IIO SCMI Sensors # # end of IIO SCMI Sensors # # SSP Sensor Common # # CONFIG_IIO_SSP_SENSORHUB is not set # end of SSP Sensor Common # # Digital to analog converters # # CONFIG_AD3552R is not set # CONFIG_AD5064 is not set # CONFIG_AD5360 is not set # CONFIG_AD5380 is not set # CONFIG_AD5421 is not set # CONFIG_AD5446 is not set # CONFIG_AD5449 is not set # CONFIG_AD5592R is not set # CONFIG_AD5593R is not set # CONFIG_AD5504 is not set # CONFIG_AD5624R_SPI is not set # CONFIG_LTC2688 is not set # CONFIG_AD5686_SPI is not set # CONFIG_AD5696_I2C is not set # CONFIG_AD5755 is not set # CONFIG_AD5758 is not set # CONFIG_AD5761 is not set # CONFIG_AD5764 is not set # CONFIG_AD5766 is not set # CONFIG_AD5770R is not set # CONFIG_AD5791 is not set # CONFIG_AD7293 is not set # CONFIG_AD7303 is not set # CONFIG_AD8801 is not set # CONFIG_DPOT_DAC is not set # CONFIG_DS4424 is not set # CONFIG_LTC1660 is not set # CONFIG_LTC2632 is not set # CONFIG_M62332 is not set # CONFIG_MAX517 is not set # CONFIG_MAX5821 is not set # CONFIG_MCP4725 is not set # CONFIG_MCP4922 is not set # CONFIG_TI_DAC082S085 is not set # CONFIG_TI_DAC5571 is not set # CONFIG_TI_DAC7311 is not set # CONFIG_TI_DAC7612 is not set # CONFIG_VF610_DAC is not set # end of Digital to analog converters # # IIO dummy driver # # end of IIO dummy driver # # Filters # # end of Filters # # Frequency Synthesizers DDS/PLL # # # Clock Generator/Distribution # # CONFIG_AD9523 is not set # end of Clock Generator/Distribution # # Phase-Locked Loop (PLL) frequency synthesizers # # CONFIG_ADF4350 is not set # CONFIG_ADF4371 is not set # CONFIG_ADMV1013 is not set # CONFIG_ADMV4420 is not set # CONFIG_ADRF6780 is not set # end of Phase-Locked Loop (PLL) frequency synthesizers # end of Frequency Synthesizers DDS/PLL # # Digital gyroscope sensors # # CONFIG_ADIS16080 is not set # CONFIG_ADIS16130 is not set # CONFIG_ADIS16136 is not set # CONFIG_ADIS16260 is not set # CONFIG_ADXRS290 is not set # CONFIG_ADXRS450 is not set # CONFIG_BMG160 is not set # CONFIG_FXAS21002C is not set CONFIG_MPU3050=y CONFIG_MPU3050_I2C=y # CONFIG_IIO_ST_GYRO_3AXIS is not set # CONFIG_ITG3200 is not set # end of Digital gyroscope sensors # # Health Sensors # # # Heart Rate Monitors # # CONFIG_AFE4403 is not set # CONFIG_AFE4404 is not set # CONFIG_MAX30100 is not set # CONFIG_MAX30102 is not set # end of Heart Rate Monitors # end of Health Sensors # # Humidity sensors # # CONFIG_AM2315 is not set # CONFIG_DHT11 is not set # CONFIG_HDC100X is not set # CONFIG_HDC2010 is not set # CONFIG_HTS221 is not set # CONFIG_HTU21 is not set # CONFIG_SI7005 is not set # CONFIG_SI7020 is not set # end of Humidity sensors # # Inertial measurement units # # CONFIG_ADIS16400 is not set # CONFIG_ADIS16460 is not set # CONFIG_ADIS16475 is not set # CONFIG_ADIS16480 is not set # CONFIG_BMI160_I2C is not set # CONFIG_BMI160_SPI is not set # CONFIG_BOSCH_BNO055_SERIAL is not set # CONFIG_BOSCH_BNO055_I2C is not set # CONFIG_FXOS8700_I2C is not set # CONFIG_FXOS8700_SPI is not set # CONFIG_KMX61 is not set # CONFIG_INV_ICM42600_I2C is not set # CONFIG_INV_ICM42600_SPI is not set # CONFIG_INV_MPU6050_I2C is not set # CONFIG_INV_MPU6050_SPI is not set # CONFIG_IIO_ST_LSM6DSX is not set # CONFIG_IIO_ST_LSM9DS0 is not set # end of Inertial measurement units # # Light sensors # # CONFIG_ADJD_S311 is not set # CONFIG_ADUX1020 is not set # CONFIG_AL3010 is not set # CONFIG_AL3320A is not set # CONFIG_APDS9300 is not set # CONFIG_APDS9960 is not set # CONFIG_AS73211 is not set # CONFIG_BH1750 is not set # CONFIG_BH1780 is not set # CONFIG_CM32181 is not set # CONFIG_CM3232 is not set # CONFIG_CM3323 is not set # CONFIG_CM3605 is not set # CONFIG_CM36651 is not set # CONFIG_GP2AP002 is not set # CONFIG_GP2AP020A00F is not set # CONFIG_SENSORS_ISL29018 is not set # CONFIG_SENSORS_ISL29028 is not set # CONFIG_ISL29125 is not set # CONFIG_JSA1212 is not set # CONFIG_RPR0521 is not set # CONFIG_LTR501 is not set # CONFIG_LTRF216A is not set # CONFIG_LV0104CS is not set # CONFIG_MAX44000 is not set # CONFIG_MAX44009 is not set # CONFIG_NOA1305 is not set # CONFIG_OPT3001 is not set # CONFIG_PA12203001 is not set # CONFIG_SI1133 is not set # CONFIG_SI1145 is not set # CONFIG_STK3310 is not set # CONFIG_ST_UVIS25 is not set # CONFIG_TCS3414 is not set # CONFIG_TCS3472 is not set # CONFIG_SENSORS_TSL2563 is not set # CONFIG_TSL2583 is not set # CONFIG_TSL2591 is not set # CONFIG_TSL2772 is not set # CONFIG_TSL4531 is not set # CONFIG_US5182D is not set # CONFIG_VCNL4000 is not set # CONFIG_VCNL4035 is not set # CONFIG_VEML6030 is not set # CONFIG_VEML6070 is not set # CONFIG_VL6180 is not set # CONFIG_ZOPT2201 is not set # end of Light sensors # # Magnetometer sensors # # CONFIG_AK8974 is not set CONFIG_AK8975=y # CONFIG_AK09911 is not set # CONFIG_BMC150_MAGN_I2C is not set # CONFIG_BMC150_MAGN_SPI is not set # CONFIG_MAG3110 is not set # CONFIG_MMC35240 is not set # CONFIG_IIO_ST_MAGN_3AXIS is not set # CONFIG_SENSORS_HMC5843_I2C is not set # CONFIG_SENSORS_HMC5843_SPI is not set # CONFIG_SENSORS_RM3100_I2C is not set # CONFIG_SENSORS_RM3100_SPI is not set # CONFIG_YAMAHA_YAS530 is not set # end of Magnetometer sensors # # Multiplexers # # CONFIG_IIO_MUX is not set # end of Multiplexers # # Inclinometer sensors # # end of Inclinometer sensors # # Triggers - standalone # CONFIG_IIO_HRTIMER_TRIGGER=y # CONFIG_IIO_INTERRUPT_TRIGGER is not set # CONFIG_IIO_TIGHTLOOP_TRIGGER is not set # CONFIG_IIO_SYSFS_TRIGGER is not set # end of Triggers - standalone # # Linear and angular position sensors # # end of Linear and angular position sensors # # Digital potentiometers # # CONFIG_AD5110 is not set # CONFIG_AD5272 is not set # CONFIG_DS1803 is not set # CONFIG_MAX5432 is not set # CONFIG_MAX5481 is not set # CONFIG_MAX5487 is not set # CONFIG_MCP4018 is not set # CONFIG_MCP4131 is not set # CONFIG_MCP4531 is not set # CONFIG_MCP41010 is not set # CONFIG_TPL0102 is not set # end of Digital potentiometers # # Digital potentiostats # # CONFIG_LMP91000 is not set # end of Digital potentiostats # # Pressure sensors # # CONFIG_ABP060MG is not set # CONFIG_BMP280 is not set # CONFIG_DLHL60D is not set # CONFIG_DPS310 is not set # CONFIG_HP03 is not set # CONFIG_ICP10100 is not set # CONFIG_MPL115_I2C is not set # CONFIG_MPL115_SPI is not set # CONFIG_MPL3115 is not set # CONFIG_MS5611 is not set # CONFIG_MS5637 is not set # CONFIG_IIO_ST_PRESS is not set # CONFIG_T5403 is not set # CONFIG_HP206C is not set # CONFIG_ZPA2326 is not set # end of Pressure sensors # # Lightning sensors # # CONFIG_AS3935 is not set # end of Lightning sensors # # Proximity and distance sensors # # CONFIG_ISL29501 is not set # CONFIG_LIDAR_LITE_V2 is not set # CONFIG_MB1232 is not set # CONFIG_PING is not set # CONFIG_RFD77402 is not set # CONFIG_SRF04 is not set # CONFIG_SX9310 is not set # CONFIG_SX9324 is not set # CONFIG_SX9360 is not set # CONFIG_SX9500 is not set # CONFIG_SRF08 is not set # CONFIG_VCNL3020 is not set # CONFIG_VL53L0X_I2C is not set # end of Proximity and distance sensors # # Resolver to digital converters # # CONFIG_AD2S90 is not set # CONFIG_AD2S1200 is not set # end of Resolver to digital converters # # Temperature sensors # # CONFIG_LTC2983 is not set # CONFIG_MAXIM_THERMOCOUPLE is not set # CONFIG_MLX90614 is not set # CONFIG_MLX90632 is not set # CONFIG_TMP006 is not set # CONFIG_TMP007 is not set # CONFIG_TMP117 is not set # CONFIG_TSYS01 is not set # CONFIG_TSYS02D is not set # CONFIG_MAX31856 is not set # CONFIG_MAX31865 is not set # end of Temperature sensors CONFIG_PWM=y CONFIG_PWM_SYSFS=y # CONFIG_PWM_DEBUG is not set # CONFIG_PWM_ATMEL_TCB is not set # CONFIG_PWM_CLK is not set # CONFIG_PWM_FSL_FTM is not set # CONFIG_PWM_PCA9685 is not set # CONFIG_PWM_TIECAP is not set # CONFIG_PWM_XILINX is not set # # IRQ chip support # CONFIG_IRQCHIP=y CONFIG_ARM_GIC=y CONFIG_ARM_GIC_MAX_NR=1 # CONFIG_AL_FIC is not set # CONFIG_XILINX_INTC is not set CONFIG_KEYSTONE_IRQ=y CONFIG_TI_PRUSS_INTC=m # end of IRQ chip support # CONFIG_IPACK_BUS is not set CONFIG_ARCH_HAS_RESET_CONTROLLER=y CONFIG_RESET_CONTROLLER=y # CONFIG_RESET_SIMPLE is not set CONFIG_RESET_TI_SCI=y CONFIG_RESET_TI_SYSCON=y # CONFIG_RESET_TI_TPS380X is not set # # PHY Subsystem # CONFIG_GENERIC_PHY=y # CONFIG_PHY_CAN_TRANSCEIVER is not set # # PHY drivers for Broadcom platforms # # CONFIG_BCM_KONA_USB2_PHY is not set # end of PHY drivers for Broadcom platforms # CONFIG_PHY_CADENCE_TORRENT is not set # CONFIG_PHY_CADENCE_DPHY is not set # CONFIG_PHY_CADENCE_DPHY_RX is not set # CONFIG_PHY_CADENCE_SIERRA is not set # CONFIG_PHY_CADENCE_SALVO is not set # CONFIG_PHY_PXA_28NM_HSIC is not set # CONFIG_PHY_PXA_28NM_USB2 is not set # CONFIG_PHY_LAN966X_SERDES is not set # CONFIG_PHY_OCELOT_SERDES is not set # end of PHY Subsystem # CONFIG_POWERCAP is not set # CONFIG_MCB is not set # # Performance monitor support # # CONFIG_ARM_CCI_PMU is not set # CONFIG_ARM_CCN is not set CONFIG_ARM_PMU=y # end of Performance monitor support CONFIG_RAS=y # # Android # # CONFIG_ANDROID_BINDER_IPC is not set # end of Android # CONFIG_LIBNVDIMM is not set # CONFIG_DAX is not set CONFIG_NVMEM=y CONFIG_NVMEM_SYSFS=y # CONFIG_NVMEM_RMEM is not set # CONFIG_NVMEM_U_BOOT_ENV is not set # # HW tracing support # # CONFIG_STM is not set # CONFIG_INTEL_TH is not set # end of HW tracing support # CONFIG_FPGA is not set # CONFIG_FSI is not set # CONFIG_TEE is not set CONFIG_PM_OPP=y # CONFIG_SIOX is not set # CONFIG_SLIMBUS is not set # CONFIG_INTERCONNECT is not set # CONFIG_COUNTER is not set # CONFIG_MOST is not set # CONFIG_PECI is not set # CONFIG_HTE is not set # end of Device Drivers # # File systems # CONFIG_DCACHE_WORD_ACCESS=y # CONFIG_VALIDATE_FS_PARSER is not set CONFIG_FS_IOMAP=y CONFIG_EXT2_FS=y # CONFIG_EXT2_FS_XATTR is not set CONFIG_EXT3_FS=y # CONFIG_EXT3_FS_POSIX_ACL is not set # CONFIG_EXT3_FS_SECURITY is not set CONFIG_EXT4_FS=y CONFIG_EXT4_FS_POSIX_ACL=y CONFIG_EXT4_FS_SECURITY=y # CONFIG_EXT4_DEBUG is not set CONFIG_JBD2=y # CONFIG_JBD2_DEBUG is not set CONFIG_FS_MBCACHE=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set # CONFIG_XFS_FS is not set # CONFIG_GFS2_FS is not set # CONFIG_OCFS2_FS is not set # CONFIG_BTRFS_FS is not set # CONFIG_NILFS2_FS is not set # CONFIG_F2FS_FS is not set CONFIG_FS_POSIX_ACL=y CONFIG_EXPORTFS=y # CONFIG_EXPORTFS_BLOCK_OPS is not set CONFIG_FILE_LOCKING=y # CONFIG_FS_ENCRYPTION is not set # CONFIG_FS_VERITY is not set CONFIG_FSNOTIFY=y CONFIG_DNOTIFY=y CONFIG_INOTIFY_USER=y # CONFIG_FANOTIFY is not set # CONFIG_QUOTA is not set CONFIG_AUTOFS4_FS=y CONFIG_AUTOFS_FS=y # CONFIG_FUSE_FS is not set CONFIG_OVERLAY_FS=y # CONFIG_OVERLAY_FS_REDIRECT_DIR is not set CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y # CONFIG_OVERLAY_FS_INDEX is not set # CONFIG_OVERLAY_FS_METACOPY is not set # # Caches # # CONFIG_FSCACHE is not set # end of Caches # # CD-ROM/DVD Filesystems # # CONFIG_ISO9660_FS is not set # CONFIG_UDF_FS is not set # end of CD-ROM/DVD Filesystems # # DOS/FAT/EXFAT/NT Filesystems # # CONFIG_MSDOS_FS is not set # CONFIG_VFAT_FS is not set # CONFIG_EXFAT_FS is not set # CONFIG_NTFS_FS is not set # CONFIG_NTFS3_FS is not set # end of DOS/FAT/EXFAT/NT Filesystems # # Pseudo filesystems # CONFIG_PROC_FS=y CONFIG_PROC_SYSCTL=y CONFIG_PROC_PAGE_MONITOR=y CONFIG_PROC_CHILDREN=y CONFIG_KERNFS=y CONFIG_SYSFS=y CONFIG_TMPFS=y CONFIG_TMPFS_POSIX_ACL=y CONFIG_TMPFS_XATTR=y CONFIG_ARCH_SUPPORTS_HUGETLBFS=y # CONFIG_HUGETLBFS is not set CONFIG_MEMFD_CREATE=y CONFIG_CONFIGFS_FS=y # end of Pseudo filesystems CONFIG_MISC_FILESYSTEMS=y # CONFIG_ORANGEFS_FS is not set # CONFIG_ADFS_FS is not set # CONFIG_AFFS_FS is not set # CONFIG_ECRYPT_FS is not set # CONFIG_HFS_FS is not set # CONFIG_HFSPLUS_FS is not set # CONFIG_BEFS_FS is not set # CONFIG_BFS_FS is not set # CONFIG_EFS_FS is not set # CONFIG_JFFS2_FS is not set CONFIG_UBIFS_FS=y # CONFIG_UBIFS_FS_ADVANCED_COMPR is not set CONFIG_UBIFS_FS_LZO=y CONFIG_UBIFS_FS_ZLIB=y CONFIG_UBIFS_FS_ZSTD=y # CONFIG_UBIFS_ATIME_SUPPORT is not set CONFIG_UBIFS_FS_XATTR=y CONFIG_UBIFS_FS_SECURITY=y # CONFIG_UBIFS_FS_AUTHENTICATION is not set # CONFIG_CRAMFS is not set # CONFIG_SQUASHFS is not set # CONFIG_VXFS_FS is not set # CONFIG_MINIX_FS is not set # CONFIG_OMFS_FS is not set # CONFIG_HPFS_FS is not set # CONFIG_QNX4FS_FS is not set # CONFIG_QNX6FS_FS is not set # CONFIG_ROMFS_FS is not set CONFIG_PSTORE=y CONFIG_PSTORE_DEFAULT_KMSG_BYTES=10240 CONFIG_PSTORE_DEFLATE_COMPRESS=y # CONFIG_PSTORE_LZO_COMPRESS is not set # CONFIG_PSTORE_LZ4_COMPRESS is not set # CONFIG_PSTORE_LZ4HC_COMPRESS is not set # CONFIG_PSTORE_842_COMPRESS is not set # CONFIG_PSTORE_ZSTD_COMPRESS is not set CONFIG_PSTORE_COMPRESS=y CONFIG_PSTORE_DEFLATE_COMPRESS_DEFAULT=y CONFIG_PSTORE_COMPRESS_DEFAULT="deflate" CONFIG_PSTORE_CONSOLE=y CONFIG_PSTORE_PMSG=y CONFIG_PSTORE_RAM=y # CONFIG_PSTORE_BLK is not set # CONFIG_SYSV_FS is not set # CONFIG_UFS_FS is not set # CONFIG_EROFS_FS is not set # CONFIG_NETWORK_FILESYSTEMS is not set CONFIG_NLS=y CONFIG_NLS_DEFAULT="iso8859-1" CONFIG_NLS_CODEPAGE_437=y # CONFIG_NLS_CODEPAGE_737 is not set # CONFIG_NLS_CODEPAGE_775 is not set # CONFIG_NLS_CODEPAGE_850 is not set # CONFIG_NLS_CODEPAGE_852 is not set # CONFIG_NLS_CODEPAGE_855 is not set # CONFIG_NLS_CODEPAGE_857 is not set # CONFIG_NLS_CODEPAGE_860 is not set # CONFIG_NLS_CODEPAGE_861 is not set # CONFIG_NLS_CODEPAGE_862 is not set # CONFIG_NLS_CODEPAGE_863 is not set # CONFIG_NLS_CODEPAGE_864 is not set # CONFIG_NLS_CODEPAGE_865 is not set # CONFIG_NLS_CODEPAGE_866 is not set # CONFIG_NLS_CODEPAGE_869 is not set # CONFIG_NLS_CODEPAGE_936 is not set # CONFIG_NLS_CODEPAGE_950 is not set # CONFIG_NLS_CODEPAGE_932 is not set # CONFIG_NLS_CODEPAGE_949 is not set # CONFIG_NLS_CODEPAGE_874 is not set # CONFIG_NLS_ISO8859_8 is not set # CONFIG_NLS_CODEPAGE_1250 is not set # CONFIG_NLS_CODEPAGE_1251 is not set # CONFIG_NLS_ASCII is not set CONFIG_NLS_ISO8859_1=y # CONFIG_NLS_ISO8859_2 is not set # CONFIG_NLS_ISO8859_3 is not set # CONFIG_NLS_ISO8859_4 is not set # CONFIG_NLS_ISO8859_5 is not set # CONFIG_NLS_ISO8859_6 is not set # CONFIG_NLS_ISO8859_7 is not set # CONFIG_NLS_ISO8859_9 is not set # CONFIG_NLS_ISO8859_13 is not set # CONFIG_NLS_ISO8859_14 is not set # CONFIG_NLS_ISO8859_15 is not set # CONFIG_NLS_KOI8_R is not set # CONFIG_NLS_KOI8_U is not set # CONFIG_NLS_MAC_ROMAN is not set # CONFIG_NLS_MAC_CELTIC is not set # CONFIG_NLS_MAC_CENTEURO is not set # CONFIG_NLS_MAC_CROATIAN is not set # CONFIG_NLS_MAC_CYRILLIC is not set # CONFIG_NLS_MAC_GAELIC is not set # CONFIG_NLS_MAC_GREEK is not set # CONFIG_NLS_MAC_ICELAND is not set # CONFIG_NLS_MAC_INUIT is not set # CONFIG_NLS_MAC_ROMANIAN is not set # CONFIG_NLS_MAC_TURKISH is not set CONFIG_NLS_UTF8=y # CONFIG_DLM is not set # CONFIG_UNICODE is not set CONFIG_IO_WQ=y # end of File systems # # Security options # CONFIG_KEYS=y # CONFIG_KEYS_REQUEST_CACHE is not set # CONFIG_PERSISTENT_KEYRINGS is not set # CONFIG_TRUSTED_KEYS is not set # CONFIG_ENCRYPTED_KEYS is not set # CONFIG_KEY_DH_OPERATIONS is not set # CONFIG_SECURITY_DMESG_RESTRICT is not set # CONFIG_SECURITY is not set # CONFIG_SECURITYFS is not set CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y # CONFIG_HARDENED_USERCOPY is not set # CONFIG_FORTIFY_SOURCE is not set # CONFIG_STATIC_USERMODEHELPER is not set CONFIG_DEFAULT_SECURITY_DAC=y CONFIG_LSM="landlock,lockdown,yama,loadpin,safesetid,integrity,bpf" # # Kernel hardening options # # # Memory initialization # CONFIG_CC_HAS_AUTO_VAR_INIT_PATTERN=y CONFIG_CC_HAS_AUTO_VAR_INIT_ZERO_BARE=y CONFIG_CC_HAS_AUTO_VAR_INIT_ZERO=y # CONFIG_INIT_STACK_NONE is not set # CONFIG_INIT_STACK_ALL_PATTERN is not set CONFIG_INIT_STACK_ALL_ZERO=y # CONFIG_INIT_ON_ALLOC_DEFAULT_ON is not set # CONFIG_INIT_ON_FREE_DEFAULT_ON is not set CONFIG_CC_HAS_ZERO_CALL_USED_REGS=y # CONFIG_ZERO_CALL_USED_REGS is not set # end of Memory initialization CONFIG_RANDSTRUCT_NONE=y # CONFIG_RANDSTRUCT_FULL is not set # CONFIG_RANDSTRUCT_PERFORMANCE is not set # end of Kernel hardening options # end of Security options CONFIG_CRYPTO=y # # Crypto core or helper # CONFIG_CRYPTO_ALGAPI=y CONFIG_CRYPTO_ALGAPI2=y CONFIG_CRYPTO_AEAD=m CONFIG_CRYPTO_AEAD2=y CONFIG_CRYPTO_SKCIPHER=m CONFIG_CRYPTO_SKCIPHER2=y CONFIG_CRYPTO_HASH=y CONFIG_CRYPTO_HASH2=y CONFIG_CRYPTO_RNG=m CONFIG_CRYPTO_RNG2=y CONFIG_CRYPTO_RNG_DEFAULT=m CONFIG_CRYPTO_AKCIPHER2=y CONFIG_CRYPTO_AKCIPHER=y CONFIG_CRYPTO_KPP2=y CONFIG_CRYPTO_KPP=m CONFIG_CRYPTO_ACOMP2=y CONFIG_CRYPTO_MANAGER=y CONFIG_CRYPTO_MANAGER2=y CONFIG_CRYPTO_USER=m CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y CONFIG_CRYPTO_GF128MUL=m CONFIG_CRYPTO_NULL=m CONFIG_CRYPTO_NULL2=y # CONFIG_CRYPTO_PCRYPT is not set CONFIG_CRYPTO_CRYPTD=m CONFIG_CRYPTO_AUTHENC=m CONFIG_CRYPTO_TEST=m CONFIG_CRYPTO_SIMD=m CONFIG_CRYPTO_ENGINE=m # end of Crypto core or helper # # Public-key cryptography # CONFIG_CRYPTO_RSA=y # CONFIG_CRYPTO_DH is not set CONFIG_CRYPTO_ECC=m CONFIG_CRYPTO_ECDH=m # CONFIG_CRYPTO_ECDSA is not set # CONFIG_CRYPTO_ECRDSA is not set # CONFIG_CRYPTO_SM2 is not set # CONFIG_CRYPTO_CURVE25519 is not set # end of Public-key cryptography # # Block ciphers # CONFIG_CRYPTO_AES=y # CONFIG_CRYPTO_AES_TI is not set # CONFIG_CRYPTO_ANUBIS is not set # CONFIG_CRYPTO_ARIA is not set # CONFIG_CRYPTO_BLOWFISH is not set # CONFIG_CRYPTO_CAMELLIA is not set # CONFIG_CRYPTO_CAST5 is not set # CONFIG_CRYPTO_CAST6 is not set CONFIG_CRYPTO_DES=m # CONFIG_CRYPTO_FCRYPT is not set # CONFIG_CRYPTO_KHAZAD is not set # CONFIG_CRYPTO_SEED is not set # CONFIG_CRYPTO_SERPENT is not set # CONFIG_CRYPTO_SM4_GENERIC is not set # CONFIG_CRYPTO_TEA is not set # CONFIG_CRYPTO_TWOFISH is not set # end of Block ciphers # # Length-preserving ciphers and modes # # CONFIG_CRYPTO_ADIANTUM is not set CONFIG_CRYPTO_ARC4=m CONFIG_CRYPTO_CHACHA20=m CONFIG_CRYPTO_CBC=m # CONFIG_CRYPTO_CFB is not set CONFIG_CRYPTO_CTR=m # CONFIG_CRYPTO_CTS is not set CONFIG_CRYPTO_ECB=m # CONFIG_CRYPTO_HCTR2 is not set # CONFIG_CRYPTO_KEYWRAP is not set # CONFIG_CRYPTO_LRW is not set # CONFIG_CRYPTO_OFB is not set # CONFIG_CRYPTO_PCBC is not set # CONFIG_CRYPTO_XTS is not set # end of Length-preserving ciphers and modes # # AEAD (authenticated encryption with associated data) ciphers # # CONFIG_CRYPTO_AEGIS128 is not set # CONFIG_CRYPTO_CHACHA20POLY1305 is not set CONFIG_CRYPTO_CCM=m CONFIG_CRYPTO_GCM=m CONFIG_CRYPTO_SEQIV=m CONFIG_CRYPTO_ECHAINIV=m # CONFIG_CRYPTO_ESSIV is not set # end of AEAD (authenticated encryption with associated data) ciphers # # Hashes, digests, and MACs # # CONFIG_CRYPTO_BLAKE2B is not set CONFIG_CRYPTO_CMAC=m CONFIG_CRYPTO_GHASH=m CONFIG_CRYPTO_HMAC=m CONFIG_CRYPTO_MD4=m CONFIG_CRYPTO_MD5=m # CONFIG_CRYPTO_MICHAEL_MIC is not set # CONFIG_CRYPTO_POLY1305 is not set # CONFIG_CRYPTO_RMD160 is not set CONFIG_CRYPTO_SHA1=y CONFIG_CRYPTO_SHA256=m CONFIG_CRYPTO_SHA512=m # CONFIG_CRYPTO_SHA3 is not set # CONFIG_CRYPTO_SM3_GENERIC is not set # CONFIG_CRYPTO_STREEBOG is not set # CONFIG_CRYPTO_VMAC is not set # CONFIG_CRYPTO_WP512 is not set # CONFIG_CRYPTO_XCBC is not set # CONFIG_CRYPTO_XXHASH is not set # end of Hashes, digests, and MACs # # CRCs (cyclic redundancy checks) # CONFIG_CRYPTO_CRC32C=y # CONFIG_CRYPTO_CRC32 is not set # CONFIG_CRYPTO_CRCT10DIF is not set # end of CRCs (cyclic redundancy checks) # # Compression # CONFIG_CRYPTO_DEFLATE=y CONFIG_CRYPTO_LZO=y # CONFIG_CRYPTO_842 is not set # CONFIG_CRYPTO_LZ4 is not set # CONFIG_CRYPTO_LZ4HC is not set CONFIG_CRYPTO_ZSTD=y # end of Compression # # Random number generation # # CONFIG_CRYPTO_ANSI_CPRNG is not set CONFIG_CRYPTO_DRBG_MENU=m CONFIG_CRYPTO_DRBG_HMAC=y # CONFIG_CRYPTO_DRBG_HASH is not set # CONFIG_CRYPTO_DRBG_CTR is not set CONFIG_CRYPTO_DRBG=m CONFIG_CRYPTO_JITTERENTROPY=m # end of Random number generation # # Userspace interface # CONFIG_CRYPTO_USER_API=m CONFIG_CRYPTO_USER_API_HASH=m CONFIG_CRYPTO_USER_API_SKCIPHER=m CONFIG_CRYPTO_USER_API_RNG=m # CONFIG_CRYPTO_USER_API_RNG_CAVP is not set CONFIG_CRYPTO_USER_API_AEAD=m CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE=y # CONFIG_CRYPTO_STATS is not set # end of Userspace interface CONFIG_CRYPTO_HASH_INFO=y # # Accelerated Cryptographic Algorithms for CPU (arm) # # CONFIG_CRYPTO_CURVE25519_NEON is not set CONFIG_CRYPTO_GHASH_ARM_CE=m # CONFIG_CRYPTO_NHPOLY1305_NEON is not set # CONFIG_CRYPTO_POLY1305_ARM is not set # CONFIG_CRYPTO_BLAKE2S_ARM is not set # CONFIG_CRYPTO_BLAKE2B_NEON is not set CONFIG_CRYPTO_SHA1_ARM=m CONFIG_CRYPTO_SHA1_ARM_NEON=m CONFIG_CRYPTO_SHA1_ARM_CE=m CONFIG_CRYPTO_SHA2_ARM_CE=m CONFIG_CRYPTO_SHA256_ARM=m CONFIG_CRYPTO_SHA512_ARM=m CONFIG_CRYPTO_AES_ARM=m CONFIG_CRYPTO_AES_ARM_BS=m CONFIG_CRYPTO_AES_ARM_CE=m CONFIG_CRYPTO_CHACHA20_NEON=m CONFIG_CRYPTO_CRC32_ARM_CE=m # end of Accelerated Cryptographic Algorithms for CPU (arm) CONFIG_CRYPTO_HW=y # CONFIG_CRYPTO_DEV_ATMEL_ECC is not set # CONFIG_CRYPTO_DEV_ATMEL_SHA204A is not set CONFIG_CRYPTO_DEV_VIRTIO=m # CONFIG_CRYPTO_DEV_SAFEXCEL is not set # CONFIG_CRYPTO_DEV_CCREE is not set # CONFIG_CRYPTO_DEV_AMLOGIC_GXL is not set CONFIG_ASYMMETRIC_KEY_TYPE=y CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y CONFIG_X509_CERTIFICATE_PARSER=y # CONFIG_PKCS8_PRIVATE_KEY_PARSER is not set CONFIG_PKCS7_MESSAGE_PARSER=y # CONFIG_FIPS_SIGNATURE_SELFTEST is not set # # Certificates for signature checking # CONFIG_SYSTEM_TRUSTED_KEYRING=y CONFIG_SYSTEM_TRUSTED_KEYS="" # CONFIG_SYSTEM_EXTRA_CERTIFICATE is not set # CONFIG_SECONDARY_TRUSTED_KEYRING is not set # CONFIG_SYSTEM_BLACKLIST_KEYRING is not set # end of Certificates for signature checking # # Library routines # CONFIG_LINEAR_RANGES=y # CONFIG_PACKING is not set CONFIG_BITREVERSE=y CONFIG_HAVE_ARCH_BITREVERSE=y CONFIG_GENERIC_STRNCPY_FROM_USER=y CONFIG_GENERIC_STRNLEN_USER=y CONFIG_GENERIC_NET_UTILS=y # CONFIG_CORDIC is not set # CONFIG_PRIME_NUMBERS is not set CONFIG_RATIONAL=y CONFIG_GENERIC_PCI_IOMAP=y CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y # # Crypto library routines # CONFIG_CRYPTO_LIB_UTILS=y CONFIG_CRYPTO_LIB_AES=y CONFIG_CRYPTO_LIB_ARC4=m CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=m CONFIG_CRYPTO_LIB_CHACHA_GENERIC=m # CONFIG_CRYPTO_LIB_CHACHA is not set # CONFIG_CRYPTO_LIB_CURVE25519 is not set CONFIG_CRYPTO_LIB_DES=m CONFIG_CRYPTO_LIB_POLY1305_RSIZE=9 # CONFIG_CRYPTO_LIB_POLY1305 is not set # CONFIG_CRYPTO_LIB_CHACHA20POLY1305 is not set CONFIG_CRYPTO_LIB_SHA1=y CONFIG_CRYPTO_LIB_SHA256=m # end of Crypto library routines CONFIG_CRC_CCITT=m CONFIG_CRC16=y # CONFIG_CRC_T10DIF is not set # CONFIG_CRC64_ROCKSOFT is not set CONFIG_CRC_ITU_T=m CONFIG_CRC32=y # CONFIG_CRC32_SELFTEST is not set CONFIG_CRC32_SLICEBY8=y # CONFIG_CRC32_SLICEBY4 is not set # CONFIG_CRC32_SARWATE is not set # CONFIG_CRC32_BIT is not set # CONFIG_CRC64 is not set # CONFIG_CRC4 is not set # CONFIG_CRC7 is not set CONFIG_LIBCRC32C=m # CONFIG_CRC8 is not set CONFIG_XXHASH=y # CONFIG_RANDOM32_SELFTEST is not set CONFIG_ZLIB_INFLATE=y CONFIG_ZLIB_DEFLATE=y CONFIG_LZO_COMPRESS=y CONFIG_LZO_DECOMPRESS=y CONFIG_ZSTD_COMMON=y CONFIG_ZSTD_COMPRESS=y CONFIG_ZSTD_DECOMPRESS=y CONFIG_XZ_DEC=y CONFIG_XZ_DEC_X86=y CONFIG_XZ_DEC_POWERPC=y CONFIG_XZ_DEC_IA64=y CONFIG_XZ_DEC_ARM=y CONFIG_XZ_DEC_ARMTHUMB=y CONFIG_XZ_DEC_SPARC=y # CONFIG_XZ_DEC_MICROLZMA is not set CONFIG_XZ_DEC_BCJ=y # CONFIG_XZ_DEC_TEST is not set CONFIG_DECOMPRESS_GZIP=y CONFIG_DECOMPRESS_BZIP2=y CONFIG_DECOMPRESS_XZ=y CONFIG_GENERIC_ALLOCATOR=y CONFIG_REED_SOLOMON=y CONFIG_REED_SOLOMON_ENC8=y CONFIG_REED_SOLOMON_DEC8=y CONFIG_TEXTSEARCH=y CONFIG_TEXTSEARCH_KMP=m CONFIG_TEXTSEARCH_BM=m CONFIG_TEXTSEARCH_FSM=m CONFIG_ASSOCIATIVE_ARRAY=y CONFIG_HAS_IOMEM=y CONFIG_HAS_IOPORT_MAP=y CONFIG_HAS_DMA=y CONFIG_DMA_OPS=y CONFIG_NEED_DMA_MAP_STATE=y CONFIG_ARCH_DMA_ADDR_T_64BIT=y CONFIG_DMA_DECLARE_COHERENT=y CONFIG_ARCH_HAS_SETUP_DMA_OPS=y CONFIG_ARCH_HAS_TEARDOWN_DMA_OPS=y CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU=y CONFIG_SWIOTLB=y # CONFIG_DMA_RESTRICTED_POOL is not set CONFIG_DMA_NONCOHERENT_MMAP=y CONFIG_DMA_CMA=y # CONFIG_DMA_PERNUMA_CMA is not set # # Default contiguous memory area size: # CONFIG_CMA_SIZE_MBYTES=48 CONFIG_CMA_SIZE_SEL_MBYTES=y # CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set # CONFIG_CMA_SIZE_SEL_MIN is not set # CONFIG_CMA_SIZE_SEL_MAX is not set CONFIG_CMA_ALIGNMENT=8 # CONFIG_DMA_API_DEBUG is not set # CONFIG_DMA_MAP_BENCHMARK is not set CONFIG_SGL_ALLOC=y # CONFIG_FORCE_NR_CPUS is not set CONFIG_CPU_RMAP=y CONFIG_DQL=y CONFIG_GLOB=y # CONFIG_GLOB_SELFTEST is not set CONFIG_NLATTR=y CONFIG_CLZ_TAB=y # CONFIG_IRQ_POLL is not set CONFIG_MPILIB=y CONFIG_LIBFDT=y CONFIG_OID_REGISTRY=y CONFIG_HAVE_GENERIC_VDSO=y CONFIG_GENERIC_GETTIMEOFDAY=y CONFIG_GENERIC_VDSO_32=y CONFIG_SG_POOL=y CONFIG_SBITMAP=y # end of Library routines CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y # # Kernel hacking # # # printk and dmesg options # CONFIG_PRINTK_TIME=y # CONFIG_PRINTK_CALLER is not set # CONFIG_STACKTRACE_BUILD_ID is not set CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7 CONFIG_CONSOLE_LOGLEVEL_QUIET=4 CONFIG_MESSAGE_LOGLEVEL_DEFAULT=7 # CONFIG_BOOT_PRINTK_DELAY is not set CONFIG_DYNAMIC_DEBUG=y CONFIG_DYNAMIC_DEBUG_CORE=y CONFIG_SYMBOLIC_ERRNAME=y CONFIG_DEBUG_BUGVERBOSE=y # end of printk and dmesg options CONFIG_DEBUG_KERNEL=y # CONFIG_DEBUG_MISC is not set # # Compile-time checks and compiler options # CONFIG_AS_HAS_NON_CONST_LEB128=y CONFIG_DEBUG_INFO_NONE=y # CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT is not set # CONFIG_DEBUG_INFO_DWARF4 is not set # CONFIG_DEBUG_INFO_DWARF5 is not set CONFIG_FRAME_WARN=1024 # CONFIG_STRIP_ASM_SYMS is not set # CONFIG_READABLE_ASM is not set # CONFIG_HEADERS_INSTALL is not set # CONFIG_DEBUG_SECTION_MISMATCH is not set CONFIG_SECTION_MISMATCH_WARN_ONLY=y # CONFIG_VMLINUX_MAP is not set # CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set # end of Compile-time checks and compiler options # # Generic Kernel Debugging Instruments # CONFIG_MAGIC_SYSRQ=y CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1 CONFIG_MAGIC_SYSRQ_SERIAL=y CONFIG_MAGIC_SYSRQ_SERIAL_SEQUENCE="" CONFIG_DEBUG_FS=y CONFIG_DEBUG_FS_ALLOW_ALL=y # CONFIG_DEBUG_FS_DISALLOW_MOUNT is not set # CONFIG_DEBUG_FS_ALLOW_NONE is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_KGDB is not set # CONFIG_UBSAN is not set CONFIG_HAVE_KCSAN_COMPILER=y # end of Generic Kernel Debugging Instruments # # Networking Debugging # # CONFIG_NET_DEV_REFCNT_TRACKER is not set # CONFIG_NET_NS_REFCNT_TRACKER is not set # CONFIG_DEBUG_NET is not set # end of Networking Debugging # # Memory Debugging # # CONFIG_PAGE_EXTENSION is not set CONFIG_DEBUG_PAGEALLOC=y # CONFIG_DEBUG_PAGEALLOC_ENABLE_DEFAULT is not set # CONFIG_SLUB_DEBUG is not set # CONFIG_PAGE_OWNER is not set CONFIG_PAGE_POISONING=y # CONFIG_DEBUG_RODATA_TEST is not set # CONFIG_DEBUG_WX is not set # CONFIG_DEBUG_OBJECTS is not set # CONFIG_SHRINKER_DEBUG is not set CONFIG_HAVE_DEBUG_KMEMLEAK=y # CONFIG_DEBUG_KMEMLEAK is not set # CONFIG_DEBUG_STACK_USAGE is not set # CONFIG_SCHED_STACK_END_CHECK is not set # CONFIG_DEBUG_VM is not set CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y # CONFIG_DEBUG_VIRTUAL is not set # CONFIG_DEBUG_MEMORY_INIT is not set # CONFIG_DEBUG_PER_CPU_MAPS is not set # CONFIG_DEBUG_KMAP_LOCAL is not set # CONFIG_DEBUG_HIGHMEM is not set CONFIG_HAVE_ARCH_KASAN=y CONFIG_HAVE_ARCH_KASAN_VMALLOC=y CONFIG_CC_HAS_KASAN_GENERIC=y CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y # CONFIG_KASAN is not set CONFIG_HAVE_ARCH_KFENCE=y # CONFIG_KFENCE is not set # end of Memory Debugging # CONFIG_DEBUG_SHIRQ is not set # # Debug Oops, Lockups and Hangs # # CONFIG_PANIC_ON_OOPS is not set CONFIG_PANIC_ON_OOPS_VALUE=0 CONFIG_PANIC_TIMEOUT=0 # CONFIG_SOFTLOCKUP_DETECTOR is not set # CONFIG_DETECT_HUNG_TASK is not set # CONFIG_WQ_WATCHDOG is not set # CONFIG_TEST_LOCKUP is not set # end of Debug Oops, Lockups and Hangs # # Scheduler Debugging # CONFIG_SCHED_DEBUG=y CONFIG_SCHED_INFO=y CONFIG_SCHEDSTATS=y # end of Scheduler Debugging # CONFIG_DEBUG_TIMEKEEPING is not set # CONFIG_DEBUG_PREEMPT is not set # # Lock Debugging (spinlocks, mutexes, etc...) # CONFIG_LOCK_DEBUGGING_SUPPORT=y # CONFIG_PROVE_LOCKING is not set # CONFIG_LOCK_STAT is not set # CONFIG_DEBUG_RT_MUTEXES is not set # CONFIG_DEBUG_SPINLOCK is not set # CONFIG_DEBUG_MUTEXES is not set # CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set # CONFIG_DEBUG_RWSEMS is not set # CONFIG_DEBUG_LOCK_ALLOC is not set # CONFIG_DEBUG_ATOMIC_SLEEP is not set # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set # CONFIG_LOCK_TORTURE_TEST is not set # CONFIG_WW_MUTEX_SELFTEST is not set # CONFIG_SCF_TORTURE_TEST is not set # end of Lock Debugging (spinlocks, mutexes, etc...) # CONFIG_DEBUG_IRQFLAGS is not set # CONFIG_STACKTRACE is not set # CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set # CONFIG_DEBUG_KOBJECT is not set # # Debug kernel data structures # # CONFIG_DEBUG_LIST is not set # CONFIG_DEBUG_PLIST is not set # CONFIG_DEBUG_SG is not set # CONFIG_DEBUG_NOTIFIERS is not set # CONFIG_BUG_ON_DATA_CORRUPTION is not set # CONFIG_DEBUG_MAPLE_TREE is not set # end of Debug kernel data structures # CONFIG_DEBUG_CREDENTIALS is not set # # RCU Debugging # # CONFIG_RCU_SCALE_TEST is not set # CONFIG_RCU_TORTURE_TEST is not set # CONFIG_RCU_REF_SCALE_TEST is not set CONFIG_RCU_CPU_STALL_TIMEOUT=21 CONFIG_RCU_EXP_CPU_STALL_TIMEOUT=0 # CONFIG_RCU_TRACE is not set # CONFIG_RCU_EQS_DEBUG is not set # end of RCU Debugging # CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set # CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set # CONFIG_LATENCYTOP is not set CONFIG_HAVE_FUNCTION_TRACER=y CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y CONFIG_HAVE_DYNAMIC_FTRACE=y CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y CONFIG_HAVE_SYSCALL_TRACEPOINTS=y CONFIG_HAVE_C_RECORDMCOUNT=y CONFIG_HAVE_BUILDTIME_MCOUNT_SORT=y CONFIG_TRACING_SUPPORT=y # CONFIG_FTRACE is not set # CONFIG_SAMPLES is not set # CONFIG_STRICT_DEVMEM is not set # # arm Debugging # # CONFIG_ARM_PTDUMP_DEBUGFS is not set # CONFIG_UNWINDER_FRAME_POINTER is not set CONFIG_UNWINDER_ARM=y CONFIG_ARM_UNWIND=y CONFIG_BACKTRACE_VERBOSE=y CONFIG_DEBUG_USER=y # CONFIG_DEBUG_LL is not set CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" # CONFIG_PID_IN_CONTEXTIDR is not set # CONFIG_CORESIGHT is not set # end of arm Debugging # # Kernel Testing and Coverage # # CONFIG_KUNIT is not set # CONFIG_NOTIFIER_ERROR_INJECTION is not set # CONFIG_FAULT_INJECTION is not set CONFIG_ARCH_HAS_KCOV=y CONFIG_CC_HAS_SANCOV_TRACE_PC=y # CONFIG_KCOV is not set CONFIG_RUNTIME_TESTING_MENU=y # CONFIG_LKDTM is not set # CONFIG_TEST_MIN_HEAP is not set # CONFIG_TEST_DIV64 is not set # CONFIG_BACKTRACE_SELF_TEST is not set # CONFIG_TEST_REF_TRACKER is not set # CONFIG_RBTREE_TEST is not set # CONFIG_REED_SOLOMON_TEST is not set # CONFIG_INTERVAL_TREE_TEST is not set # CONFIG_PERCPU_TEST is not set # CONFIG_ATOMIC64_SELFTEST is not set # CONFIG_TEST_HEXDUMP is not set # CONFIG_STRING_SELFTEST is not set # CONFIG_TEST_STRING_HELPERS is not set # CONFIG_TEST_STRSCPY is not set # CONFIG_TEST_KSTRTOX is not set # CONFIG_TEST_PRINTF is not set # CONFIG_TEST_SCANF is not set # CONFIG_TEST_BITMAP is not set # CONFIG_TEST_UUID is not set # CONFIG_TEST_XARRAY is not set # CONFIG_TEST_MAPLE_TREE is not set # CONFIG_TEST_RHASHTABLE is not set # CONFIG_TEST_SIPHASH is not set # CONFIG_TEST_IDA is not set # CONFIG_TEST_LKM is not set # CONFIG_TEST_BITOPS is not set # CONFIG_TEST_VMALLOC is not set # CONFIG_TEST_USER_COPY is not set # CONFIG_TEST_BPF is not set # CONFIG_TEST_BLACKHOLE_DEV is not set # CONFIG_FIND_BIT_BENCHMARK is not set # CONFIG_TEST_FIRMWARE is not set # CONFIG_TEST_SYSCTL is not set # CONFIG_TEST_UDELAY is not set # CONFIG_TEST_STATIC_KEYS is not set # CONFIG_TEST_DYNAMIC_DEBUG is not set # CONFIG_TEST_KMOD is not set # CONFIG_TEST_MEMCAT_P is not set # CONFIG_TEST_MEMINIT is not set # CONFIG_TEST_FREE_PAGES is not set CONFIG_ARCH_USE_MEMTEST=y # CONFIG_MEMTEST is not set # end of Kernel Testing and Coverage # # Rust hacking # # end of Rust hacking # end of Kernel hacking
Kernel device tree:
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for K2G EVM
*
* Copyright (C) 2016-2017 Texas Instruments Incorporated - http://www.ti.com/
*/
/dts-v1/;
#include "keystone-k2g.dtsi"
/ {
compatible = "ti,k2g-evm", "ti,k2g", "ti,keystone";
memory@800000000 {
device_type = "memory";
reg = <0x00000008 0x00000000 0x00000000 0x20000000>;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
dsp_common_memory: dsp-common-memory@81f800000 {
compatible = "shared-dma-pool";
reg = <0x00000008 0x1f800000 0x00000000 0x800000>;
reusable;
status = "okay";
};
};
gpmc_nor@30000000 {
compatible = "cypress,S29", "cfi-flash";
reg = <0x0 0x30000000>,
<0x0 0x10000000>;
status = "okay";
#address-cells = <1>;
#size-cells = <1>;
bank-width = <2>;
device-width = <1>;
device_type = "nor";
partition@0.0 {
label = "uboot_1";
reg = <0x00200000 0x200000>;
};
partition@0.1 {
label = "uboot_2";
reg = <0x00400000 0x200000>;
};
partition@0.2 {
label = "uboot_env";
reg = <0x00600000 0x100000>;
};
partition@0.3 {
label = "itb_1";
reg = <0x00700000 0x03C00000>;
};
partition@0.4 {
label = "itb_2";
reg = <0x04300000 0x03C00000>;
};
partition@1.0 {
label = "gpmc_partition";
reg = <0x08000000 0x07FE0000>;
};
};
};
&k2g_pinctrl {
uart0_pins: pinmux_uart0_pins {
pinctrl-single,pins = <
K2G_CORE_IOPAD(0x11cc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* uart0_rxd.uart0_rxd */
K2G_CORE_IOPAD(0x11d0) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
>;
};
uart1_pins: pinmux_uart1_pins {
pinctrl-single,pins = <
K2G_CORE_IOPAD(0x11dc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* uart1_rxd.uart1_rxd */
K2G_CORE_IOPAD(0x11e0) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE0) /* uart1_txd.uart1_txd */
>;
};
uart2_pins: pinmux_uart2_pins {
pinctrl-single,pins = <
K2G_CORE_IOPAD(0x11ec) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* uart2_rxd.uart2_rxd */
K2G_CORE_IOPAD(0x11f0) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE0) /* uart2_txd.uart2_txd */
>;
};
i2c0_pins: pinmux_i2c0_pins {
pinctrl-single,pins = <
K2G_CORE_IOPAD(0x137c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
K2G_CORE_IOPAD(0x1380) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
>;
};
i2c1_pins: pinmux_i2c1_pins {
pinctrl-single,pins = <
K2G_CORE_IOPAD(0x1384) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* i2c1_scl.i2c1_scl */
K2G_CORE_IOPAD(0x1388) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* i2c1_sda.i2c1_sda */
>;
};
spi0_pins: pinmux_spi0_pins {
pinctrl-single,pins = <
K2G_CORE_IOPAD(0x1190) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* spi0_scs0.spi0_scs0 */
K2G_CORE_IOPAD(0x1198) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* spi0_clk.spi0_clk */
K2G_CORE_IOPAD(0x119C) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* spi0_miso.spi0_miso */
K2G_CORE_IOPAD(0x11A0) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* spi0_mosi.spi0_mosi */
>;
};
spi1_pins: pinmux_spi1_pins {
pinctrl-single,pins = <
K2G_CORE_IOPAD(0x11a4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* spi1_scs0.spi1_scs0 */
K2G_CORE_IOPAD(0x11ac) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* spi1_clk.spi1_clk */
K2G_CORE_IOPAD(0x11b0) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* spi1_miso.spi1_miso */
K2G_CORE_IOPAD(0x11b4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* spi1_mosi.spi1_mosi */
>;
};
spi2_pins: pinmux_spi2_pins {
pinctrl-single,pins = <
K2G_CORE_IOPAD(0x11B8) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* spi2_scs0.spi2_scs0 */
K2G_CORE_IOPAD(0x11C0) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* spi2_clk.spi2_clk */
K2G_CORE_IOPAD(0x11C4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* spi2_miso.spi2_miso */
K2G_CORE_IOPAD(0x11C8) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* spi2_mosi.spi2_mosi */
>;
};
dcan0_pins: pinmux_dcan0_pins {
pinctrl-single,pins = <
K2G_CORE_IOPAD(0x11fc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dcan0tx.dcan0tx */
K2G_CORE_IOPAD(0x1200) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE0) /* dcan0rx.dcan0rx */
>;
};
emac_pins: pinmux_emac_pins {
pinctrl-single,pins = <
K2G_CORE_IOPAD(0x113C) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE0) /* MII_RXD1.RGMII_RXD1 */
K2G_CORE_IOPAD(0x1138) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE0) /* MII_RXD2.RGMII_RXD2 */
K2G_CORE_IOPAD(0x1134) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE0) /* MII_RXD3.RGMII_RXD3 */
K2G_CORE_IOPAD(0x1140) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE0) /* MII_RXD0.RGMII_RXD0 */
K2G_CORE_IOPAD(0x1178) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE0) /* MII_TXD0.RGMII_TXD0 */
K2G_CORE_IOPAD(0x1174) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE0) /* MII_TXD1.RGMII_TXD1 */
K2G_CORE_IOPAD(0x1170) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE0) /* MII_TXD2.RGMII_TXD2 */
K2G_CORE_IOPAD(0x116C) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE0) /* MII_TXD3.RGMII_TXD3 */
K2G_CORE_IOPAD(0x1154) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE0) /* MII_TXCLK.RGMII_TXC */
K2G_CORE_IOPAD(0x117C) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE0) /* MII_TXEN.RGMII_TXCTL */
K2G_CORE_IOPAD(0x1120) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE0) /* MII_RXCLK.RGMII_RXC */
K2G_CORE_IOPAD(0x1144) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE0) /* MII_RXDV.RGMII_RXCTL */
>;
};
mdio_pins: pinmux_mdio_pins {
pinctrl-single,pins = <
K2G_CORE_IOPAD(0x118C) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* MDIO_CLK.MDIO_CLK */
K2G_CORE_IOPAD(0x1188) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* MDIO_DATA.MDIO_DATA */
>;
};
qspi_pins: pinmux_qspi_pins {
pinctrl-single,pins = <
K2G_CORE_IOPAD(0x1204) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_clk.qspi_clk */
K2G_CORE_IOPAD(0x1208) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_rclk.qspi_rclk */
K2G_CORE_IOPAD(0x120c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d0.qspi_d0 */
K2G_CORE_IOPAD(0x1210) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d1.qspi_d1 */
K2G_CORE_IOPAD(0x1214) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d2.qspi_d2 */
K2G_CORE_IOPAD(0x1218) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d3.qspi_d3 */
K2G_CORE_IOPAD(0x121c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_csn0.qspi_csn0 */
K2G_CORE_IOPAD(0x1220) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_csn1.qspi_csn1 */
>;
};
gpio1_pins: pinmux_gpio1_pins {
pinctrl-single,pins = <
K2G_CORE_IOPAD(0x1300) (BUFFER_CLASS_D | PIN_PULLDOWN | MUX_MODE3) /* GPIO1_17 - EEPROM_WP */
>;
};
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins>;
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&uart2_pins>;
status = "okay";
};
/* Enable GPIO0 though there is no PIN used as GPIO on the ARM. */
&gpio0 {
pinctrl-names = "default";
status = "okay";
gpio-line-names = "GPIO0_0","GPIO0_1","GPIO0_2","GPIO0_3","GPIO0_4","GPIO0_5","GPIO0_6","GPIO0_7","GPIO0_8","GPIO0_9","GPIO0_10","GPIO0_11","GPIO0_12","GPIO0_13","GPIO0_14","GPIO0_15","GPIO0_16","GPIO0_17","GPIO0_18","GPIO0_19","GPIO0_20","GPIO0_21","GPIO0_22","GPIO0_23","GPIO0_24","GPIO0_25","GPIO0_26","GPIO0_27","GPIO0_28","GPIO0_29","GPIO0_30","GPIO0_31","GPIO0_32","GPIO0_33","GPIO0_34","GPIO0_35","GPIO0_36","GPIO0_37","GPIO0_38","GPIO0_39","GPIO0_40","GPIO0_41","GPIO0_42","GPIO0_43","GPIO0_44","GPIO0_45","GPIO0_46","GPIO0_47","GPIO0_48","GPIO0_49","GPIO0_50","GPIO0_51","GPIO0_52","GPIO0_53","GPIO0_54","GPIO0_55","GPIO0_56","GPIO0_57","GPIO0_58","GPIO0_59","GPIO0_60","GPIO0_61","GPIO0_62","GPIO0_63","GPIO0_64","GPIO0_65","GPIO0_66","GPIO0_67","GPIO0_68","GPIO0_69","GPIO0_70","GPIO0_71","GPIO0_72","GPIO0_73","GPIO0_74","GPIO0_75","GPIO0_76","GPIO0_77","GPIO0_78","GPIO0_79","GPIO0_80","GPIO0_81","GPIO0_82","GPIO0_83","GPIO0_84","GPIO0_85","GPIO0_86","GPIO0_87","GPIO0_88","GPIO0_89","GPIO0_90","GPIO0_91","GPIO0_92","GPIO0_93","GPIO0_94","GPIO0_95","GPIO0_96","GPIO0_97","GPIO0_98","GPIO0_99","GPIO0_100","GPIO0_101","GPIO0_102","GPIO0_103","GPIO0_104","GPIO0_105","GPIO0_106","GPIO0_107","GPIO0_108","GPIO0_109","GPIO0_110","GPIO0_111","GPIO0_112","GPIO0_113","GPIO0_114","GPIO0_115","GPIO0_116","GPIO0_117","GPIO0_118","GPIO0_119","GPIO0_120","GPIO0_121","GPIO0_122","GPIO0_123","GPIO0_124","GPIO0_125","GPIO0_126","GPIO0_127","GPIO0_128","GPIO0_129","GPIO0_130","GPIO0_131","GPIO0_132","GPIO0_133","GPIO0_134","GPIO0_135","GPIO0_136","GPIO0_137","GPIO0_138","GPIO0_139","GPIO0_140","GPIO0_141","GPIO0_142","GPIO0_143";
};
&gpio1 {
pinctrl-names = "default";
pinctrl-0 = <&gpio1_pins>;
status = "okay";
gpio-line-names = "GPIO1_0","GPIO1_1","GPIO1_2","GPIO1_3","GPIO1_4","GPIO1_5","GPIO1_6","GPIO1_7","GPIO1_8","GPIO1_9","GPIO1_10","GPIO1_11","GPIO1_12","GPIO1_13","GPIO1_14","GPIO1_15","GPIO1_16","GPIO1_17","GPIO1_18","GPIO1_19","GPIO1_20","GPIO1_21","GPIO1_22","GPIO1_23","GPIO1_24","GPIO1_25","GPIO1_26","GPIO1_27","GPIO1_28","GPIO1_29","GPIO1_30","GPIO1_31","GPIO1_32","GPIO1_33","GPIO1_34","GPIO1_35","GPIO1_36","GPIO1_37","GPIO1_38","GPIO1_39","GPIO1_40","GPIO1_41","GPIO1_42","GPIO1_43","GPIO1_44","GPIO1_45","GPIO1_46","GPIO1_47","GPIO1_48","GPIO1_49","GPIO1_50","GPIO1_51","GPIO1_52","GPIO1_53","GPIO1_54","GPIO1_55","GPIO1_56","GPIO1_57","GPIO1_58","GPIO1_59","GPIO1_60","GPIO1_61","GPIO1_62","GPIO1_63","GPIO1_64","GPIO1_65","GPIO1_66","GPIO1_67";
};
&dsp0 {
memory-region = <&dsp_common_memory>;
status = "okay";
};
&spi1 {
pinctrl-names = "default";
pinctrl-0 = <&spi1_pins>;
status = "okay";
};
&qspi {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&qspi_pins>;
cdns,rclk-en;
flash0: flash@0 {
compatible = "s70fl01gs", "jedec,spi-nor";
reg = <0>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <4>;
spi-max-frequency = <50000000>;
#address-cells = <1>;
#size-cells = <1>;
cdns,read-delay = <5>;
cdns,tshsl-ns = <500>;
cdns,tsd2d-ns = <500>;
cdns,tchsh-ns = <119>;
cdns,tslch-ns = <119>;
/* first sector is reserve for QSPI preboot */
partition@0 {
label = "qspi_flash_0";
reg = <0x00040000 0x03FC0000>;
};
};
flash1: flash@1 {
compatible = "s70fl01gs", "jedec,spi-nor";
reg = <1>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <4>;
spi-max-frequency = <50000000>;
#address-cells = <1>;
#size-cells = <1>;
cdns,read-delay = <5>;
cdns,tshsl-ns = <500>;
cdns,tsd2d-ns = <500>;
cdns,tchsh-ns = <119>;
cdns,tslch-ns = <119>;
partition@0 {
label = "qspi_flash_1";
reg = <0x00000000 0x04000000>;
};
};
};
// Defined in keystone-k2g-netcp.dtsi
&qmss {
status = "okay";
};
// Defined in keystone-k2g-netcp.dtsi
&knav_dmas {
status = "okay";
};
// Defined in keystone-k2g-netcp.dtsi
&mdio {
pinctrl-names = "default";
pinctrl-0 = <&mdio_pins>;
status = "okay";
ethphy0: ethernet-phy@1 {
reg = <1>;
};
};
// Defined in keystone-k2g-netcp.dtsi
&gbe0 {
phy-handle = <ðphy0>;
phy-mode = "mii";
status = "okay";
link-interface = <8>;
};
// Defined in keystone-k2g-netcp.dtsi
&netcp {
pinctrl-names = "default";
pinctrl-0 = <&emac_pins>;
status = "okay";
};
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins>;
status = "okay";
clock-frequency = <400000>;
lm75: lm75@48{
compatible = "national,lm75";
reg = <0x48>;
#thermal-sensor-cells = <0>;
};
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
status = "okay";
clock-frequency = <400000>;
eeprom@50 {
compatible = "atmel,24c1024";
reg = <0x50>;
};
};
Uboot 2019.01:
https://git.ti.com/cgit/processor-sdk/processor-sdk-u-boot/log/?h=processor-sdk-u-boot-2019.01
Our patch applied on top of source code:
diff --git a/arch/arm/mach-keystone/ddr3.c b/arch/arm/mach-keystone/ddr3.c
--- a/arch/arm/mach-keystone/ddr3.c
+++ b/arch/arm/mach-keystone/ddr3.c
@@ -15,7 +15,7 @@
#include <asm/ti-common/ti-edma3.h>
#define DDR3_EDMA_BLK_SIZE_SHIFT 10
-#define DDR3_EDMA_BLK_SIZE (1 << DDR3_EDMA_BLK_SIZE_SHIFT)
+#define DDR3_EDMA_BLK_SIZE (1 << DDR3_EDMA_BLK_SIZE_SHIFT) // 1024
#define DDR3_EDMA_BCNT 0x8000
#define DDR3_EDMA_CCNT 1
#define DDR3_EDMA_XF_SIZE (DDR3_EDMA_BLK_SIZE * DDR3_EDMA_BCNT)
@@ -158,10 +158,7 @@
puts("\nClear entire DDR3 memory to enable ECC\n");
/* save the SES MPAX regs */
- if (cpu_is_k2g())
- msmc_get_ses_mpax(K2G_MSMC_SEGMENT_ARM, 0, mpax);
- else
- msmc_get_ses_mpax(K2HKLE_MSMC_SEGMENT_ARM, 0, mpax);
+ msmc_get_ses_mpax(K2G_MSMC_SEGMENT_ARM, 0, mpax);
/* setup edma slot 1 configuration */
slot.opt = EDMA3_SLOPT_TRANS_COMP_INT_ENB |
@@ -186,53 +183,30 @@
edma_channel.trigger_slot_word = EDMA3_TWORD(dst);
qedma3_start(KS2_EDMA0_BASE, &edma_channel);
- /* DDR3 size in segments (4KB seg size) */
- seg_num = ddr3_size << (30 - KS2_MSMC_SEG_SIZE_SHIFT);
-
- for (seg = 0; seg < seg_num; seg += KS2_MSMC_MAP_SEG_NUM) {
- /* map 2GB 36-bit DDR address to 32-bit DDR address in EMIF
- access slave interface so that edma driver can access */
- if (cpu_is_k2g()) {
- msmc_map_ses_segment(K2G_MSMC_SEGMENT_ARM, 0,
- base >> KS2_MSMC_SEG_SIZE_SHIFT,
- KS2_MSMC_DST_SEG_BASE + seg,
- MPAX_SEG_2G);
- } else {
- msmc_map_ses_segment(K2HKLE_MSMC_SEGMENT_ARM, 0,
- base >> KS2_MSMC_SEG_SIZE_SHIFT,
- KS2_MSMC_DST_SEG_BASE + seg,
- MPAX_SEG_2G);
- }
-
- if ((seg_num - seg) > KS2_MSMC_MAP_SEG_NUM)
- edma_blks = KS2_MSMC_MAP_SEG_NUM <<
- (KS2_MSMC_SEG_SIZE_SHIFT
- - DDR3_EDMA_BLK_SIZE_SHIFT);
- else
- edma_blks = (seg_num - seg) << (KS2_MSMC_SEG_SIZE_SHIFT
- - DDR3_EDMA_BLK_SIZE_SHIFT);
-
- /* Use edma driver to scrub 2GB DDR memory */
- for (dst = base, blks = 0; blks < edma_blks;
- blks += DDR3_EDMA_BCNT, dst += DDR3_EDMA_XF_SIZE) {
- edma3_set_src_addr(KS2_EDMA0_BASE,
- edma_channel.slot, (u32)edma_src);
- edma3_set_dest_addr(KS2_EDMA0_BASE,
- edma_channel.slot, (u32)dst);
-
- while (edma3_check_for_transfer(KS2_EDMA0_BASE,
- &edma_channel))
- udelay(10);
- }
+ /* map 512Mib 36-bit DDR address to 32-bit DDR address in EMIF
+ access slave interface so that edma driver can access */
+ msmc_map_ses_segment(K2G_MSMC_SEGMENT_ARM, 0,
+ base >> KS2_MSMC_SEG_SIZE_SHIFT,
+ KS2_MSMC_DST_SEG_BASE,
+ MPAX_SEG_512M);
+
+ /* Use edma driver to scrub 512MiB DDR memory */
+ for (dst = base; dst < (base + ddr3_size); dst += DDR3_EDMA_XF_SIZE)
+ {
+ edma3_set_src_addr(KS2_EDMA0_BASE,
+ edma_channel.slot, (u32)edma_src);
+ edma3_set_dest_addr(KS2_EDMA0_BASE,
+ edma_channel.slot, (u32)dst);
+
+ while (edma3_check_for_transfer(KS2_EDMA0_BASE,
+ &edma_channel))
+ udelay(10);
}
qedma3_stop(KS2_EDMA0_BASE, &edma_channel);
/* restore the SES MPAX regs */
- if (cpu_is_k2g())
- msmc_set_ses_mpax(K2G_MSMC_SEGMENT_ARM, 0, mpax);
- else
- msmc_set_ses_mpax(K2HKLE_MSMC_SEGMENT_ARM, 0, mpax);
+ msmc_set_ses_mpax(K2G_MSMC_SEGMENT_ARM, 0, mpax);
}
static void ddr3_ecc_init_range(u32 base)
diff --git a/arch/arm/mach-keystone/include/mach/mux-k2g.h b/arm/mach-keystone/include/mach/mux-k2g.h
--- a/arch/arm/mach-keystone/include/mach/mux-k2g.h
+++ b/arch/arm/mach-keystone/include/mach/mux-k2g.h
@@ -22,7 +22,13 @@
* 3:0 - muxmode (available modes 0:5)
*/
-#define PIN_IEN (1 << 18) /* pin input enabled */
+/*
+ * According to 66AK2G1x TRM
+ * section 5.1.4.149 for PAD Config register value.
+ * bit 18 "This bit must not be modified"
+ * => setting PIN_IEN from (1 << 18) to (0 << 18)
+ * */
+#define PIN_IEN (0 << 18) /* pin input enabled */
#define PIN_PDIS (1 << 16) /* pull up/down disabled */
#define PIN_PTU (1 << 17) /* pull up */
#define PIN_PTD (0 << 17) /* pull down */
diff --git a/arch/arm/mach-keystone/Kconfig b/arch/arm/mach-keystone/Kconfig
--- a/arch/arm/mach-keystone/Kconfig
+++ b/arch/arm/mach-keystone/Kconfig
@@ -37,6 +37,15 @@
imply DM_I2C
imply SOC_TI
imply TI_KEYSTONE_SERDES
+
+config TARGET_TMA
+ bool "Honeywell TMA"
+ select BOARD_LATE_INIT
+ select SPL_BOARD_INIT if SPL
+ select CMD_DDR3
+ imply DM_I2C
+ imply SOC_TI
+ imply TI_KEYSTONE_SERDES
endchoice
@@ -44,5 +53,7 @@
default "keystone"
source "board/ti/ks2_evm/Kconfig"
+source "board/honeywell/tma/Kconfig"
endif
+
diff --git a/board/honeywell/tma/board.c b/board/honeywell/tma/board.c
--- a/board/honeywell/tma/board.c
+++ b/board/honeywell/tma/board.c
@@ -0,0 +1,253 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Keystone : Board initialization
+ *
+ * (C) Copyright 2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ */
+
+#include "../tma/board.h"
+#include "../tma/tma_utils.h"
+
+#include <common.h>
+#include <spl.h>
+#include <exports.h>
+#include <fdt_support.h>
+#include <asm/arch/ddr3.h>
+#include <asm/arch/psc_defs.h>
+#include <asm/arch/clock.h>
+#include <asm/ti-common/ti-aemif.h>
+#include <asm/ti-common/keystone_net.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern void board_gpmc_init(void);
+
+#if defined(CONFIG_TI_AEMIF)
+static struct aemif_config aemif_configs[] = {
+ { /* CS0 */
+ .mode = AEMIF_MODE_NAND,
+ .wr_setup = 0xf,
+ .wr_strobe = 0x3f,
+ .wr_hold = 7,
+ .rd_setup = 0xf,
+ .rd_strobe = 0x3f,
+ .rd_hold = 7,
+ .turn_around = 3,
+ .width = AEMIF_WIDTH_8,
+ },
+};
+#endif
+
+int dram_init(void)
+{
+ u32 ddr3_size;
+
+ ddr3_size = ddr3_init();
+
+ gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
+ CONFIG_MAX_RAM_BANK_SIZE);
+#if defined(CONFIG_TI_AEMIF)
+ //if (!board_is_k2g_ice())
+ aemif_init(ARRAY_SIZE(aemif_configs), aemif_configs);
+#endif
+
+ if (ddr3_size)
+ ddr3_init_ecc(KS2_DDR3A_EMIF_CTRL_BASE, ddr3_size);
+ else
+ ddr3_init_ecc(KS2_DDR3A_EMIF_CTRL_BASE,
+ gd->ram_size);
+
+ return 0;
+}
+
+struct image_header *spl_get_load_buffer(ssize_t offset, size_t size)
+{
+ return (struct image_header *)(CONFIG_SYS_TEXT_BASE);
+}
+
+const reg_print_t pll_print[] =
+{
+ { "BOOTCFG_MAIN_PLL_CTL0", (void*)0x2620350},
+ { "BOOTCFG_MAIN_PLL_CTL1", (void*)0x2620354},
+ { 0, 0},
+};
+
+int board_init(void)
+{
+ print_reg(pll_print);
+
+ board_gpmc_init();
+
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ return 0;
+}
+
+#ifdef CONFIG_SPL_BUILD
+void spl_board_init(void)
+{
+ spl_init_keystone_plls();
+ preloader_console_init();
+}
+
+u32 spl_boot_device(void)
+{
+#if defined(CONFIG_SPL_SPI_LOAD)
+ return BOOT_DEVICE_SPI;
+#else
+ puts("Unknown boot device\n");
+ hang();
+#endif
+}
+#endif
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ int lpae;
+ char *env;
+ char *endp;
+ int nbanks;
+ u64 size[2];
+ u64 start[2];
+ u32 ddr3a_size;
+
+ env = env_get("mem_lpae");
+ lpae = env && simple_strtol(env, NULL, 0);
+
+ ddr3a_size = 0;
+ if (lpae) {
+ ddr3a_size = ddr3_get_size();
+ if ((ddr3a_size != 8) && (ddr3a_size != 4))
+ ddr3a_size = 0;
+ }
+
+ nbanks = 1;
+ start[0] = bd->bi_dram[0].start;
+ size[0] = bd->bi_dram[0].size;
+
+ /* adjust memory start address for LPAE */
+ if (lpae) {
+ start[0] -= CONFIG_SYS_SDRAM_BASE;
+ start[0] += CONFIG_SYS_LPAE_SDRAM_BASE;
+ }
+
+ if ((size[0] == 0x80000000) && (ddr3a_size != 0)) {
+ size[1] = ((u64)ddr3a_size - 2) << 30;
+ start[1] = 0x880000000;
+ nbanks++;
+ }
+
+ /* reserve memory at start of bank */
+ env = env_get("mem_reserve_head");
+ if (env) {
+ start[0] += ustrtoul(env, &endp, 0);
+ size[0] -= ustrtoul(env, &endp, 0);
+ }
+
+ env = env_get("mem_reserve");
+ if (env)
+ size[0] -= ustrtoul(env, &endp, 0);
+
+ fdt_fixup_memory_banks(blob, start, size, nbanks);
+
+ return 0;
+}
+
+void ft_board_setup_ex(void *blob, bd_t *bd)
+{
+ int lpae;
+ u64 size;
+ char *env;
+ u64 *reserve_start;
+ int unitrd_fixup = 0;
+
+ env = env_get("mem_lpae");
+ lpae = env && simple_strtol(env, NULL, 0);
+ env = env_get("uinitrd_fixup");
+ unitrd_fixup = env && simple_strtol(env, NULL, 0);
+
+ /* Fix up the initrd */
+ if (lpae && unitrd_fixup) {
+ int nodeoffset;
+ int err;
+ u64 *prop1, *prop2;
+ u64 initrd_start, initrd_end;
+
+ nodeoffset = fdt_path_offset(blob, "/chosen");
+ if (nodeoffset >= 0) {
+ prop1 = (u64 *)fdt_getprop(blob, nodeoffset,
+ "linux,initrd-start", NULL);
+ prop2 = (u64 *)fdt_getprop(blob, nodeoffset,
+ "linux,initrd-end", NULL);
+ if (prop1 && prop2) {
+ initrd_start = __be64_to_cpu(*prop1);
+ initrd_start -= CONFIG_SYS_SDRAM_BASE;
+ initrd_start += CONFIG_SYS_LPAE_SDRAM_BASE;
+ initrd_start = __cpu_to_be64(initrd_start);
+ initrd_end = __be64_to_cpu(*prop2);
+ initrd_end -= CONFIG_SYS_SDRAM_BASE;
+ initrd_end += CONFIG_SYS_LPAE_SDRAM_BASE;
+ initrd_end = __cpu_to_be64(initrd_end);
+
+ err = fdt_delprop(blob, nodeoffset,
+ "linux,initrd-start");
+ if (err < 0)
+ puts("error deleting initrd-start\n");
+
+ err = fdt_delprop(blob, nodeoffset,
+ "linux,initrd-end");
+ if (err < 0)
+ puts("error deleting initrd-end\n");
+
+ err = fdt_setprop(blob, nodeoffset,
+ "linux,initrd-start",
+ &initrd_start,
+ sizeof(initrd_start));
+ if (err < 0)
+ puts("error adding initrd-start\n");
+
+ err = fdt_setprop(blob, nodeoffset,
+ "linux,initrd-end",
+ &initrd_end,
+ sizeof(initrd_end));
+ if (err < 0)
+ puts("error adding linux,initrd-end\n");
+ }
+ }
+ }
+
+ if (lpae) {
+ /*
+ * the initrd and other reserved memory areas are
+ * embedded in in the DTB itslef. fix up these addresses
+ * to 36 bit format
+ */
+ reserve_start = (u64 *)((char *)blob +
+ fdt_off_mem_rsvmap(blob));
+ while (1) {
+ *reserve_start = __cpu_to_be64(*reserve_start);
+ size = __cpu_to_be64(*(reserve_start + 1));
+ if (size) {
+ *reserve_start -= CONFIG_SYS_SDRAM_BASE;
+ *reserve_start +=
+ CONFIG_SYS_LPAE_SDRAM_BASE;
+ *reserve_start =
+ __cpu_to_be64(*reserve_start);
+ } else {
+ break;
+ }
+ reserve_start += 2;
+ }
+ }
+
+ ddr3_check_ecc_int(KS2_DDR3A_EMIF_CTRL_BASE);
+}
+#endif /* CONFIG_OF_BOARD_SETUP */
+
+#if defined(CONFIG_DTB_RESELECT)
+int __weak embedded_dtb_select(void)
+{
+ return 0;
+}
+#endif
diff --git a/board/honeywell/tma/board.h b/board/honeywell/tma/board.h
--- a/board/honeywell/tma/board.h
+++ b/board/honeywell/tma/board.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * K2HK EVM : Board common header
+ *
+ * (C) Copyright 2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ */
+
+#ifndef _TMA_BOARD
+#define _TMA_BOARD
+
+#include <asm/ti-common/keystone_net.h>
+
+
+
+void spl_init_keystone_plls(void);
+
+#endif
diff --git a/board/honeywell/tma/board_tma.c b/board/honeywell/tma/board_tma.c
--- a/board/honeywell/tma/board_tma.c
+++ b/board/honeywell/tma/board_tma.c
@@ -0,0 +1,365 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * K2G EVM : Board initialization
+ *
+ * (C) Copyright 2015
+ * Texas Instruments Incorporated, <www.ti.com>
+ */
+#include <common.h>
+#include <asm/arch/clock.h>
+#include <asm/ti-common/keystone_net.h>
+#include <asm/arch/psc_defs.h>
+#include <asm/arch/mmc_host_def.h>
+#include <fdtdec.h>
+#include <i2c.h>
+#include <remoteproc.h>
+#include "mux_tma.h"
+
+#define K2G_GP_AUDIO_CODEC_ADDRESS 0x1B
+
+const unsigned int sysclk_array[MAX_SYSCLK] = {
+ 19200000,
+ 24000000,
+ 25000000,
+ 26000000,
+};
+
+unsigned int get_external_clk(u32 clk)
+{
+ unsigned int clk_freq;
+
+ u8 sysclk_index = get_sysclk_index();
+
+ switch (clk) {
+ case sys_clk:
+ clk_freq = sysclk_array[sysclk_index];
+ break;
+ case pa_clk:
+ clk_freq = sysclk_array[sysclk_index];
+ break;
+ case tetris_clk:
+ clk_freq = sysclk_array[sysclk_index];
+ break;
+ case ddr3a_clk:
+ clk_freq = sysclk_array[sysclk_index];
+ break;
+ case uart_clk:
+ clk_freq = sysclk_array[sysclk_index];
+ break;
+ default:
+ clk_freq = 0;
+ break;
+ }
+
+ return clk_freq;
+}
+
+int speeds[DEVSPEED_NUMSPDS] = {
+ SPD400,
+ SPD600,
+ SPD800,
+ SPD900,
+ SPD1000,
+ SPD900,
+ SPD800,
+ SPD600,
+ SPD400,
+ SPD200,
+};
+
+static int dev_speeds[DEVSPEED_NUMSPDS] = {
+ SPD600,
+ SPD800,
+ SPD900,
+ SPD1000,
+ SPD900,
+ SPD800,
+ SPD600,
+ SPD400,
+};
+
+static struct pll_init_data main_pll_config[MAX_SYSCLK][NUM_SPDS] = {
+ [SYSCLK_19MHz] = {
+ [SPD400] = {MAIN_PLL, 125, 3, 2},
+ [SPD600] = {MAIN_PLL, 125, 2, 2},
+ [SPD800] = {MAIN_PLL, 250, 3, 2},
+ [SPD900] = {MAIN_PLL, 187, 2, 2},
+ [SPD1000] = {MAIN_PLL, 104, 1, 2},
+ },
+ [SYSCLK_24MHz] = {
+ [SPD400] = {MAIN_PLL, 100, 3, 2},
+ [SPD600] = {MAIN_PLL, 300, 6, 2},
+ [SPD800] = {MAIN_PLL, 200, 3, 2},
+ [SPD900] = {MAIN_PLL, 75, 1, 2},
+ [SPD1000] = {MAIN_PLL, 250, 3, 2},
+ },
+ [SYSCLK_25MHz] = {
+ [SPD400] = {MAIN_PLL, 32, 1, 2},
+ [SPD600] = {MAIN_PLL, 48, 1, 2},
+ [SPD800] = {MAIN_PLL, 64, 1, 2},
+ [SPD900] = {MAIN_PLL, 72, 1, 2},
+ [SPD1000] = {MAIN_PLL, 80, 1, 2},
+ },
+ [SYSCLK_26MHz] = {
+ [SPD400] = {MAIN_PLL, 400, 13, 2},
+ [SPD600] = {MAIN_PLL, 230, 5, 2},
+ [SPD800] = {MAIN_PLL, 123, 2, 2},
+ [SPD900] = {MAIN_PLL, 69, 1, 2},
+ [SPD1000] = {MAIN_PLL, 384, 5, 2},
+ },
+};
+
+static struct pll_init_data tetris_pll_config[MAX_SYSCLK][NUM_SPDS] = {
+ [SYSCLK_19MHz] = {
+ [SPD200] = {TETRIS_PLL, 625, 6, 10},
+ [SPD400] = {TETRIS_PLL, 125, 1, 6},
+ [SPD600] = {TETRIS_PLL, 125, 1, 4},
+ [SPD800] = {TETRIS_PLL, 333, 2, 4},
+ [SPD900] = {TETRIS_PLL, 187, 2, 2},
+ [SPD1000] = {TETRIS_PLL, 104, 1, 2},
+ },
+ [SYSCLK_24MHz] = {
+ [SPD200] = {TETRIS_PLL, 250, 3, 10},
+ [SPD400] = {TETRIS_PLL, 100, 1, 6},
+ [SPD600] = {TETRIS_PLL, 100, 1, 4},
+ [SPD800] = {TETRIS_PLL, 400, 3, 4},
+ [SPD900] = {TETRIS_PLL, 75, 1, 2},
+ [SPD1000] = {TETRIS_PLL, 250, 3, 2},
+ },
+ [SYSCLK_25MHz] = {
+ [SPD200] = {TETRIS_PLL, 80, 1, 10},
+ [SPD400] = {TETRIS_PLL, 96, 1, 6},
+ [SPD600] = {TETRIS_PLL, 96, 1, 4},
+ [SPD800] = {TETRIS_PLL, 128, 1, 4},
+ [SPD900] = {TETRIS_PLL, 72, 1, 2},
+ [SPD1000] = {TETRIS_PLL, 80, 1, 2},
+ },
+ [SYSCLK_26MHz] = {
+ [SPD200] = {TETRIS_PLL, 307, 4, 10},
+ [SPD400] = {TETRIS_PLL, 369, 4, 6},
+ [SPD600] = {TETRIS_PLL, 369, 4, 4},
+ [SPD800] = {TETRIS_PLL, 123, 1, 4},
+ [SPD900] = {TETRIS_PLL, 69, 1, 2},
+ [SPD1000] = {TETRIS_PLL, 384, 5, 2},
+ },
+};
+
+static struct pll_init_data uart_pll_config[MAX_SYSCLK] = {
+ [SYSCLK_19MHz] = {UART_PLL, 160, 1, 8},
+ [SYSCLK_24MHz] = {UART_PLL, 128, 1, 8},
+ [SYSCLK_25MHz] = {UART_PLL, 768, 5, 10},
+ [SYSCLK_26MHz] = {UART_PLL, 384, 13, 2},
+};
+
+static struct pll_init_data nss_pll_config[MAX_SYSCLK] = {
+ [SYSCLK_19MHz] = {NSS_PLL, 625, 6, 2},
+ [SYSCLK_24MHz] = {NSS_PLL, 250, 3, 2},
+ [SYSCLK_25MHz] = {NSS_PLL, 80, 1, 2},
+ [SYSCLK_26MHz] = {NSS_PLL, 1000, 13, 2},
+};
+
+
+static struct pll_init_data ddr3_pll_config_1066[MAX_SYSCLK] = {
+ [SYSCLK_19MHz] = {DDR3A_PLL, 194, 1, 14},
+ [SYSCLK_24MHz] = {DDR3A_PLL, 156, 1, 14},
+ [SYSCLK_25MHz] = {DDR3A_PLL, 149, 1, 14},
+ [SYSCLK_26MHz] = {DDR3A_PLL, 144, 1, 14},
+};
+
+struct pll_init_data *get_pll_init_data(int pll)
+{
+ int speed = SPD1000;
+ u8 sysclk_index = get_sysclk_index();
+
+ struct pll_init_data *data = NULL;
+
+ switch (pll) {
+ case MAIN_PLL:
+ data = &main_pll_config[sysclk_index][speed];
+ break;
+ case TETRIS_PLL:
+ data = &tetris_pll_config[sysclk_index][speed];
+ break;
+ case NSS_PLL:
+ data = &nss_pll_config[sysclk_index];
+ break;
+ case UART_PLL:
+ data = &uart_pll_config[sysclk_index];
+ break;
+ case DDR3_PLL:
+ data = &ddr3_pll_config_1066[sysclk_index];
+ break;
+ default:
+ data = NULL;
+ }
+
+ return data;
+}
+
+s16 divn_val[16] = {
+ -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
+};
+
+#if defined(CONFIG_MMC)
+int board_mmc_init(bd_t *bis)
+{
+ if (psc_enable_module(KS2_LPSC_MMC)) {
+ printf("%s module enabled failed\n", __func__);
+ return -1;
+ }
+
+ omap_mmc_init(0, 0, 0, -1, -1);
+
+ omap_mmc_init(1, 0, 0, -1, -1);
+ return 0;
+}
+#endif
+
+#if defined(CONFIG_MULTI_DTB_FIT)
+int board_fit_config_name_match(const char *name)
+{
+ if (!strcmp(name, "tma")) {
+ return 0;
+ }
+ else {
+ printf("%s %d name = %s. return -1\n", __FILE__, __LINE__, name);
+ return -1;
+ }
+}
+#endif
+
+#if defined(CONFIG_DTB_RESELECT)
+/*
+static int k2g_alt_board_detect(void)
+{
+#ifndef CONFIG_DM_I2C
+ int rc;
+
+ rc = i2c_set_bus_num(1);
+ if (rc)
+ return rc;
+
+ rc = i2c_probe(K2G_GP_AUDIO_CODEC_ADDRESS);
+ if (rc)
+ return rc;
+#else
+ struct udevice *bus, *dev;
+ int rc;
+
+ rc = uclass_get_device_by_seq(UCLASS_I2C, 1, &bus);
+ if (rc)
+ return rc;
+ rc = dm_i2c_probe(bus, K2G_GP_AUDIO_CODEC_ADDRESS, 0, &dev);
+ if (rc)
+ return rc;
+#endif
+ ti_i2c_eeprom_am_set("66AK2GGP", "1.0X");
+
+ return 0;
+}
+*/
+static void k2g_reset_mux_config(void)
+{
+ /* Unlock the reset mux register */
+ clrbits_le32(KS2_RSTMUX8, RSTMUX_LOCK8_MASK);
+
+ /* Configure BOOTCFG_RSTMUX8 for WDT event to cause a device reset */
+ clrsetbits_le32(KS2_RSTMUX8, RSTMUX_OMODE8_MASK,
+ RSTMUX_OMODE8_DEV_RESET << RSTMUX_OMODE8_SHIFT);
+
+ /* lock the reset mux register to prevent any spurious writes. */
+ setbits_le32(KS2_RSTMUX8, RSTMUX_LOCK8_MASK);
+}
+
+int embedded_dtb_select(void)
+{
+ int rc;
+ /*
+ rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
+ CONFIG_EEPROM_CHIP_ADDRESS);
+ if (rc) {
+ rc = k2g_alt_board_detect();
+ if (rc) {
+ printf("Unable to do board detection\n");
+ return -1;
+ }
+ }
+ */
+
+ fdtdec_setup();
+
+ k2g_mux_config();
+
+ k2g_reset_mux_config();
+
+
+ /* deassert FLASH_HOLD */
+ clrbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_DIR_OFFSET,
+ BIT(9));
+ setbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_SETDATA_OFFSET,
+ BIT(9));
+
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_TI_I2C_BOARD_DETECT)
+ int rc;
+
+ rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
+ CONFIG_EEPROM_CHIP_ADDRESS);
+ if (rc)
+ printf("ti_i2c_eeprom_init failed %d\n", rc);
+
+ board_ti_set_ethaddr(1);
+#endif
+
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+
+ env_set("board_name", "tma\0");
+#endif
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f(void)
+{
+ init_plls();
+
+ k2g_mux_config();
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_SPL_BUILD
+void spl_init_keystone_plls(void)
+{
+ init_plls();
+}
+#endif
+
+#ifdef CONFIG_TI_SECURE_DEVICE
+void board_pmmc_image_process(ulong pmmc_image, size_t pmmc_size)
+{
+ int id = env_get_ulong("dev_pmmc", 10, 0);
+ int ret;
+
+ if (!rproc_is_initialized())
+ rproc_init();
+
+ ret = rproc_load(id, pmmc_image, pmmc_size);
+ printf("Load Remote Processor %d with data@addr=0x%08lx %u bytes:%s\n",
+ id, pmmc_image, pmmc_size, ret ? " Failed!" : " Success!");
+
+ if (!ret)
+ rproc_start(id);
+}
+
+U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_PMMC, board_pmmc_image_process);
+#endif
diff --git a/board/honeywell/tma/ddr3_tma.c b/board/honeywell/tma/ddr3_tma.c
--- a/board/honeywell/tma/ddr3_tma.c
+++ b/board/honeywell/tma/ddr3_tma.c
@@ -0,0 +1,111 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * K2G: DDR3 initialization
+ *
+ * (C) Copyright 2015
+ * Texas Instruments Incorporated, <www.ti.com>
+ */
+
+#include <common.h>
+#include <asm/arch/ddr3.h>
+#include <asm/arch/hardware.h>
+#include "../tma/board.h"
+#include "tma_utils.h"
+
+
+static struct ddr3_phy_config tma_acu_ddr3phy = {
+ .pllcr = 0x000DC000ul,
+ .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK),
+ .pgcr1_val = ((1 << 2) | (2 << 7) | (1 << 23)),
+ .ptr0 = 0x42C21590ul,
+ .ptr1 = 0xD05612C0ul,
+ .ptr2 = 0,
+ .ptr3 = 0x0904111Dul,
+ .ptr4 = 0x0859A072ul,
+ .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK),
+ .dcr_val = ((1 << 10)),
+ .dtpr0 = 0x6D147744ul,
+ .dtpr1 = 0x32845A80ul,
+ .dtpr2 = 0x50023600ul,
+ .mr0 = 0x00001830ul,
+ .mr1 = 0x00000006ul,
+ //.mr2 = 0x00000000ul,
+ .mr2 = 0x00000088ul,
+ .dtcr = 0x710035C7ul,
+ .pgcr2 = 0x00F05159ul,
+ .zq0cr1 = 0x0001005Dul,
+ .zq1cr1 = 0x0001005Bul,
+ .zq2cr1 = 0x0001005Bul,
+ .pir_v1 = 0x00000033ul,
+ .datx8_2_mask = 0,
+ .datx8_2_val = 0,
+ .datx8_3_mask = 0,
+ .datx8_3_val = 0,
+ .datx8_4_mask = 0,
+ .datx8_4_val = ((1 << 0)),
+ .datx8_5_mask = DXEN_MASK,
+ .datx8_5_val = 0,
+ .datx8_6_mask = DXEN_MASK,
+ .datx8_6_val = 0,
+ .datx8_7_mask = DXEN_MASK,
+ .datx8_7_val = 0,
+ .datx8_8_mask = DXEN_MASK,
+ .datx8_8_val = 0,
+ .pir_v2 = 0x00000F81ul,
+};
+
+
+static struct ddr3_emif_config tma_acu_ddr3 = {
+ //.sdcfg = 0x62006662ul,
+ .sdcfg = 0x62005662ul,
+ .sdtim1 = 0x0E4C6843ul,
+ //.sdtim2 = 0x00001CC6ul,
+ .sdtim2 = 0x00001CE7ul,
+ .sdtim3 = 0x323DFF32ul,
+ .sdtim4 = 0x533F08AFul,
+ .zqcfg = 0x70073200ul,
+ .sdrfc = 0x00001044ul,
+};
+
+
+const reg_print_t ddr_print[] =
+{
+ { "EMIF_SDCFG", (volatile void *)0x21010008},
+ { "EMIF_SDTIM1", (volatile void *)0x21010018},
+ { "EMIF_SDTIM2", (volatile void *)0x2101001C},
+ { "EMIF_SDTIM3", (volatile void *)0x21010020},
+ { "EMIF_SDTIM4", (volatile void *)0x21010028},
+ { "EMIF_ZQ_CONFIG", (volatile void *)0x210100C8},
+ { "EMIF_SDRFC", (volatile void *)0x21010010},
+
+ { "DDR_PHY_PGSR0", (volatile void *)0x02329010},
+ { "DDR_PHY_PGSR1", (volatile void *)0x02329014},
+ { "DDR_PHY_PLLCR", (volatile void *)0x02329018},
+ { "DDR_PHY_PTR0", (volatile void *)0x0232901C},
+ { "DDR_PHY_PTR1", (volatile void *)0x02329020},
+ { "DDR_PHY_PTR2", (volatile void *)0x02329024},
+ { "DDR_PHY_PTR3", (volatile void *)0x02329028},
+ { "DDR_PHY_PTR4", (volatile void *)0x0232902C},
+ { 0, 0},
+};
+
+
+
+
+u32 ddr3_init(void)
+{
+ /* Reset DDR3 PHY after PLL enabled */
+ ddr3_reset_ddrphy();
+ ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &tma_acu_ddr3phy);
+ ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &tma_acu_ddr3);
+
+ print_reg(ddr_print);
+
+ return 0;
+}
+
+inline int ddr3_get_size(void)
+{
+ /* Has not effect when returning 2. */
+ return 2;
+}
diff --git a/board/honeywell/tma/env_manager.c b/board/honeywell/tma/env_manager.c
--- a/board/honeywell/tma/env_manager.c
+++ b/board/honeywell/tma/env_manager.c
@@ -0,0 +1,50 @@
+
+#include <common.h>
+#include <command.h>
+#include <environment.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define INITENV
+
+static env_t *env_ptr = (env_t *)CONFIG_ENV_ADDR;
+
+static int env_flash_init(void)
+{
+ if (crc32(0, env_ptr->data, ENV_SIZE) == env_ptr->crc) {
+ gd->env_addr = (ulong)&(env_ptr->data);
+ gd->env_valid = ENV_VALID;
+ return 0;
+ }
+
+ gd->env_addr = (ulong)&default_environment[0];
+ gd->env_valid = ENV_INVALID;
+ return 0;
+}
+
+static int env_flash_save(void)
+{
+ env_t env_out;
+ int rc = 0;
+ rc = env_export( &env_out );
+ if (rc) {
+ printf("%s-Export environment variable failed\n", __FUNCTION__);
+ }
+
+ write_buff( (flash_info_t *)NULL, (uchar *)&env_out, (ulong)CONFIG_ENV_ADDR, sizeof(env_out) );
+ return 0;
+}
+
+static int env_flash_load(void)
+{
+ return env_import((char *)CONFIG_ENV_ADDR, 1);
+}
+
+
+U_BOOT_ENV_LOCATION(norflash) = {
+ .location = ENVL_NORFLASH,
+ ENV_NAME("norflash")
+ .load = env_flash_load,
+ .save = env_flash_save,
+ .init = env_flash_init,
+};
diff --git a/board/honeywell/tma/gpmc_norflash.c b/board/honeywell/tma/gpmc_norflash.c
--- a/board/honeywell/tma/gpmc_norflash.c
+++ b/board/honeywell/tma/gpmc_norflash.c
@@ -0,0 +1,499 @@
+
+
+#include <common.h>
+
+
+
+#include <os.h>
+#include <configs/tma_config.h>
+#include "../tma/board.h"
+
+#include "../tma/tma_utils.h"
+
+/* Memory configuration */
+#define CONFIG_SYS_GPMC_0_BASE (0x30000000)
+#define CONFIG_FLASH_BASE CONFIG_SYS_GPMC_0_BASE
+#define CONFIG_FLASH_SIZE (128 << 20) /* 128 MiB */
+#define CONFIG_FLASH_0 CONFIG_SYS_GPMC_0_BASE
+#define CONFIG_FLASH_1 (CONFIG_SYS_GPMC_0_BASE + CONFIG_FLASH_SIZE)
+#define CONFIG_FLASH_SECTOR_SIZE (CONFIG_FLASH_SIZE / CONFIG_SYS_MAX_FLASH_SECT)
+
+
+#define CONFIG_FLASH_SIZE_SECTOR (128 << 10) /* 128 KiB */
+#define CONFIG_FLASH_ID (0x5A5A5A5A)
+#define FLASH_WRITE_BUF_SIZE (256)
+#define FLASH_WRITE_BUF_WC(x) (x - 1)
+
+
+
+#define GPMC_REG_BASE (void*)(0x21818000)
+#define GPMC_REG_CONFIG (void*)(GPMC_REG_BASE + 0x50)
+#define GPMC_REG_STATUS (void*)(GPMC_REG_BASE + 0x54)
+
+#define GPMC_REG_CONFIG1_(i) (void*)(GPMC_REG_BASE + 0x60 + i*0x30)
+#define GPMC_REG_CONFIG2_(i) (void*)(GPMC_REG_BASE + 0x64 + i*0x30)
+#define GPMC_REG_CONFIG3_(i) (void*)(GPMC_REG_BASE + 0x68 + i*0x30)
+#define GPMC_REG_CONFIG4_(i) (void*)(GPMC_REG_BASE + 0x6C + i*0x30)
+#define GPMC_REG_CONFIG5_(i) (void*)(GPMC_REG_BASE + 0x70 + i*0x30)
+#define GPMC_REG_CONFIG6_(i) (void*)(GPMC_REG_BASE + 0x74 + i*0x30)
+#define GPMC_REG_CONFIG7_(i) (void*)(GPMC_REG_BASE + 0x78 + i*0x30)
+
+
+
+inline void* GPMC_REG_CONFIG1(u32 i)
+{
+ return (void*)(GPMC_REG_BASE + 0x60 + i*0x30);
+}
+
+inline void* GPMC_REG_CONFIG2(u32 i)
+{
+ return (void*)(GPMC_REG_BASE + 0x64 + i*0x30);
+}
+
+inline void* GPMC_REG_CONFIG3(u32 i)
+{
+ return (void*)(GPMC_REG_BASE + 0x68 + i*0x30);
+}
+
+inline void* GPMC_REG_CONFIG4(u32 i)
+{
+ return (void*)(GPMC_REG_BASE + 0x6C + i*0x30);
+}
+
+inline void* GPMC_REG_CONFIG5(u32 i)
+{
+ return (void*)(GPMC_REG_BASE + 0x70 + i*0x30);
+}
+
+inline void* GPMC_REG_CONFIG6(u32 i)
+{
+ return (void*)(GPMC_REG_BASE + 0x74 + i*0x30);
+}
+
+inline void* GPMC_REG_CONFIG7(u32 i)
+{
+ return (void*)(GPMC_REG_BASE + 0x78 + i*0x30);
+}
+
+
+
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* FLASH chips info */
+
+const reg_print_t gpmc_print[] =
+{
+ { "GPMC_CONFIG1_0", GPMC_REG_CONFIG1_(0)},
+ { "GPMC_CONFIG2_0", GPMC_REG_CONFIG2_(0)},
+ { "GPMC_CONFIG3_0", GPMC_REG_CONFIG3_(0)},
+ { "GPMC_CONFIG4_0", GPMC_REG_CONFIG4_(0)},
+ { "GPMC_CONFIG5_0", GPMC_REG_CONFIG5_(0)},
+ { "GPMC_CONFIG7_0", GPMC_REG_CONFIG7_(0)},
+ { "GPMC_CONFIG1_1", GPMC_REG_CONFIG1_(1)},
+ { "GPMC_CONFIG2_1", GPMC_REG_CONFIG2_(1)},
+ { "GPMC_CONFIG3_1", GPMC_REG_CONFIG3_(1)},
+ { "GPMC_CONFIG4_1", GPMC_REG_CONFIG4_(1)},
+ { "GPMC_CONFIG5_1", GPMC_REG_CONFIG5_(1)},
+ { "GPMC_CONFIG7_1", GPMC_REG_CONFIG7_(1)},
+ { 0, 0},
+};
+
+
+static void gpmc_init_instance(u32 instance)
+{
+ /* Disable CS */
+ __raw_writel(0, GPMC_REG_CONFIG7(instance));
+
+ u32 GPMC_CONFIG1 =
+ /* TIMEPARAGRANULARITY */ 1 << 4 | /*1h (R/W) = x2 latencies*/
+ /* DEVICESIZE */ 1 << 12| /*1h (R/W) = 16 bit*/
+ /*ATTACHEDDEVICEPAGELENGTH*/ 0 << 23; /* 0 -4 words */
+ __raw_writel(GPMC_CONFIG1, GPMC_REG_CONFIG1(instance));
+
+ u32 GPMC_CONFIG2 =
+ /* CSRDOFFTIME */ 0x18 << 8 | /* CS i de-assertion time from start cycle time for read accesses GPMC_FCLK cycle */ // 0x12
+ /* CSWROFFTIME */ 0xA << 16; /* CS i deassertion time from start cycle time for write accesses GPMC_FCLK cycle */
+ __raw_writel(GPMC_CONFIG2, GPMC_REG_CONFIG2(instance));
+
+ /* GPMC_CONFIG3_0 left to reset value */
+
+ u32 GPMC_CONFIG4 =
+ /* OEONTIME */ 0xC << 0 | /* nOE assertion time from start cycle time */
+ /* OEAADMUX_ONTIME */ 0x1 << 4 | /* nOE assertion time for the first address phase in an AAD-mux */
+ /* OEEXTRADELAY */ 0x0 << 7 |
+ /* OEOFFTIME */ 0x18 << 8 | /* nOE deassertion time from start cycle time */ //0x12
+ /* OEAADMUX_OFFTIME */ 0x3 << 13 | /* nOE deassertion time for the first address phase in an AADmultiplexed access */
+ /* WEONTIME */ 0x4 << 16 | /* nWE assertion time from start cycle time */
+ /* WEOFFTIME */ 0xA << 24; /* nWE deassertion time from start cycle time */
+ __raw_writel(GPMC_CONFIG4, GPMC_REG_CONFIG4(instance));
+
+
+ u32 GPMC_CONFIG5 =
+ /* RDCYCLETIME */ 0x19 << 0 | /* Total read cycle time */
+ /* WRCYCLETIME */ 0xA << 8 | /* Total write cycle time */
+ /* RDACCESSTIME */ 0x17 << 16 | /* Delay between start cycle time and first data valid */
+ /* PAGEBURSTACCESSTIME */ 0x5 << 24; /* Delay between successive words in a multiple access */
+ __raw_writel(GPMC_CONFIG5, GPMC_REG_CONFIG5(instance));
+
+
+
+ u32 GPMC_CONFIG7 =
+ /* MASKADDRESS */ 0x8 << 8 | /*Chip-select size of 128MB*/
+ /* CSVALID */ 0x1 << 6; /* Re-enable CS */
+
+ if ( instance == 0 )
+ {
+ GPMC_CONFIG7 |= /*BASEADDRESS*/ ((CONFIG_FLASH_0 >> 24) & 0x3F) << 0;
+ }
+
+ if ( instance == 1 )
+ {
+ GPMC_CONFIG7 |= /*BASEADDRESS*/ ((CONFIG_FLASH_1 >> 24) & 0x3F) << 0;
+ }
+ __raw_writel(GPMC_CONFIG7, GPMC_REG_CONFIG7(instance));
+}
+
+
+void board_gpmc_init(void)
+{
+ u32 GPMC_CONFIG =
+ /* WAIT1PINPOLARITY */ 1 << 9 |
+ /* WAIT0PINPOLARITY */ 0 << 8 |
+ /* WRITEPROTECT */ 0 << 4;
+ __raw_writel(GPMC_CONFIG, GPMC_REG_CONFIG);
+
+ gpmc_init_instance(0);
+ gpmc_init_instance(1);
+
+ /* Makse sure un-used GPMC instance are disabled */
+ __raw_writel(0, GPMC_REG_CONFIG7(2));
+ __raw_writel(0, GPMC_REG_CONFIG7(3));
+
+ /* print registers */
+ print_reg(gpmc_print);
+}
+
+
+
+unsigned long flash_init(void)
+{
+ u32 idx = 1;
+
+ flash_info[0].size = CONFIG_FLASH_SIZE;
+ flash_info[0].flash_id = CONFIG_FLASH_ID;
+ flash_info[0].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+ flash_info[0].start[0] = CONFIG_FLASH_0;
+
+ flash_info[1].size = CONFIG_FLASH_SIZE;
+ flash_info[1].flash_id = CONFIG_FLASH_ID;
+ flash_info[1].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+ flash_info[1].start[0] = CONFIG_FLASH_1;
+
+ for ( idx = 1; idx < flash_info[0].sector_count; idx++)
+ {
+ flash_info[0].start[idx] = flash_info[0].start[idx - 1] + CONFIG_FLASH_SECTOR_SIZE;
+ /* Sectors non-protected. */
+ flash_info[0].protect[idx] = 0;
+
+ flash_info[1].start[idx] = flash_info[1].start[idx - 1] + CONFIG_FLASH_SECTOR_SIZE;
+ /* Sectors non-protected. */
+ flash_info[1].protect[idx] = 0;
+ }
+
+ return CONFIG_FLASH_SIZE;
+}
+
+static u32 addr_to_sector( u16* add )
+{
+ // sector from 0 - CONFIG_SYS_MAX_FLASH_SECT
+ return ( ((u32)add & (CONFIG_FLASH_SIZE - 1)) / CONFIG_FLASH_SECTOR_SIZE );
+}
+
+static u16* addr_to_flash_base_addr( u16* add )
+{
+ return (u16*)( ((u32)add & CONFIG_FLASH_SIZE) ? CONFIG_FLASH_1 : CONFIG_FLASH_0 );
+}
+
+#if 0
+static u16 read_from_flash( u16* base_add, u32 offset )
+{
+ u16 value = *(base_add + offset);
+ //printf("Read 0x%x from 0x%x\n", value, (u32)(base_add + offset) );
+
+ return value;
+}
+#endif
+
+static void write_to_flash_addr( u16* addr, u16 data )
+{
+ *addr = data;
+ __asm__ __volatile__("dsb" ::: "memory");
+}
+
+static void write_to_flash( u16* base_add, u32 offset, u16 data )
+{
+ *(base_add + offset) = data;
+ __asm__ __volatile__("dsb" ::: "memory");
+}
+
+static u16 flash_get_status( u16* base_add )
+{
+ *(base_add + 0x555) = 0x70;
+ /* Make sure command is written before reading the memory */
+ __asm__ __volatile__("dsb" ::: "memory");
+
+ return *(volatile u16*)base_add;
+}
+
+static void wait_flash_not_busy(u16* base_add)
+{
+ /* Bit 7 is "Device Ready bit" */
+ u16 flash_status = flash_get_status(base_add);
+ while ( !( flash_status & (1 << 7)) )
+ {
+ udelay(1);
+ flash_status = flash_get_status(base_add);
+ }
+}
+
+static void flash_enter_unlock_bypass( u16* base_add )
+{
+ wait_flash_not_busy(base_add);
+
+ /* Enter unlock bypass mode */
+ write_to_flash( base_add, 0x555, 0xAA);
+ write_to_flash( base_add, 0x2AA, 0x55);
+ write_to_flash( base_add, 0x555, 0x20);
+}
+
+static void flash_exit_unlock_bypass( u16* base_add )
+{
+ wait_flash_not_busy(base_add);
+
+ /* Exit unlock bypass mode */
+ write_to_flash( base_add, 0x0, 0x90);
+ write_to_flash( base_add, 0x0, 0x0);
+}
+
+
+
+static void flash_erase_sectors( u16* start_add, u32 cnt )
+{
+ u16* base_add = addr_to_flash_base_addr(start_add);
+
+ u32 sector = addr_to_sector(start_add);
+ u32 last_sector = addr_to_sector(start_add + cnt - 1);
+
+ printf("Erasing from sector #%d to #%d\n", sector, last_sector);
+
+ u32 idx = 0;
+ u32 sector_cnt = last_sector - sector + 1;
+ while( sector <= last_sector)
+ {
+ // 555 AA - 2AA 55 - 555 80 - 555 AA - 2AA 55 - SA 30
+ write_to_flash( base_add, 0x555, 0xAA);
+ write_to_flash( base_add, 0x2AA, 0x55);
+ write_to_flash( base_add, 0x555, 0x80);
+ write_to_flash( base_add, 0x555, 0xAA);
+ write_to_flash( base_add, 0x2AA, 0x55);
+
+ write_to_flash( base_add, (CONFIG_FLASH_SECTOR_SIZE * sector) >> 1 , 0x30);
+
+ wait_flash_not_busy(base_add);
+ sector++;
+ idx++;
+
+ printf("\r%d/%d", idx, sector_cnt);
+ }
+ printf("\n");
+}
+
+
+int write_buff( flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+ if ( addr % 2 )
+ {
+ printf("Add (0x%x) needs to be a aligned on 16bits of 2.\n", (u32)addr);
+ return ERR_ALIGN;
+ }
+
+ if ( cnt > 0 && cnt % 2 )
+ {
+ printf("Nb of Byte (%ld) needs to be a multiple of 2.\n", cnt);
+ return ERR_ALIGN;
+ }
+
+ u16* flash_base_addr = addr_to_flash_base_addr((u16*)addr);
+ u16* addr_dst = flash_base_addr + ((addr ^ (ulong)flash_base_addr) >> 1); // (>> 1) divide by 2 to match 16bits address space of NORFlash;
+ u16* addr_src = (u16*)src;
+
+ printf("From 0x%x to 0x%x Bytes %ld)\n", (u32)src, (u32)addr, cnt);
+
+ flash_erase_sectors( (u16*)addr, cnt / 2);
+ flash_enter_unlock_bypass(flash_base_addr);
+
+ u32 idx = 0;
+ u32 total_xf = (cnt / 2);
+ u32 print_status_cnt = total_xf / 100;
+
+ printf("Sector(s) erased. Writing to FLASH\n");
+ while ( idx < total_xf )
+ {
+ wait_flash_not_busy(flash_base_addr);
+
+ int wc = FLASH_WRITE_BUF_WC(FLASH_WRITE_BUF_SIZE); //set to max value 256B
+ if ( (total_xf - idx) < FLASH_WRITE_BUF_SIZE )
+ {
+ wc = FLASH_WRITE_BUF_WC(total_xf - idx);
+ }
+
+ u16* addr_start = addr_dst;
+ // issue write to buffer command
+ write_to_flash_addr( addr_start, 0x25);
+
+ // set transfert count.
+ write_to_flash_addr( addr_start, wc);
+
+ u32 eol = idx + wc + 1;
+ while ( idx < eol )
+ {
+ // write value.
+ write_to_flash_addr( addr_dst, *addr_src);
+
+ addr_dst++;
+ addr_src++;
+
+ idx++;
+ }
+ // issue write command
+ write_to_flash_addr( addr_start, 0x29);
+
+ if ( print_status_cnt < idx )
+ {
+ printf("\r%d/%d", idx, total_xf);
+ print_status_cnt = idx + total_xf / 100;
+ }
+ }
+ printf("\r%d/%d\n", idx, total_xf);
+
+ flash_exit_unlock_bypass(flash_base_addr);
+
+ printf("Write completed. Last addr written (0x%x)\n", (u32)addr_dst);
+
+ return ERR_OK;
+}
+
+
+#ifdef FLASH_TEST_TOOL
+static int test_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ if ( argc >= 4 )
+ {
+ u16* add = 0;
+ u16* base_add = (argv[1][0] == '0') ? (u16*)CONFIG_FLASH_0 : (u16*)CONFIG_FLASH_1;
+ char command = argv[2][0];
+ u32 offset = (u32)simple_strtoul(argv[3], NULL, 16);
+ u16 flash_status = 0;
+
+ printf("Base Add 0x%x, Offset 0x%x.\n", (u32)base_add, offset );
+
+ switch( command )
+ {
+ case 'r':
+ read_from_flash(base_add, offset);
+ break;
+
+ case 'w':
+ if ( argc == 5 )
+ {
+ u16 val_w = (u16)simple_strtoul(argv[4], NULL, 16);
+ printf("Writting to 0x%x = 0x%x\n", (u32)add, val_w);
+
+ write_to_flash(base_add, offset, val_w);
+ }
+ else
+ {
+ printf("\nMissing data to write\n");
+ }
+ break;
+
+ case 'p':
+ if ( argc == 5 )
+ {
+ write_to_flash(base_add, 0x555, 0xAA);
+ write_to_flash(base_add, 0x2AA, 0x55);
+ write_to_flash(base_add, 0x555, 0xA0);
+
+ u16 val_w16 = (u16)simple_strtoul(argv[4], NULL, 16);
+ printf("Programming x16 0x%x = 0x%x\n", (u32)add, (u32)val_w16);
+
+ write_to_flash( base_add, offset, val_w16);
+
+ read_from_flash( base_add, offset );
+ }
+ else
+ {
+ printf("\nMissing data to write\n");
+ }
+ break;
+
+ case 's':
+ flash_status = flash_get_status( base_add );
+ printf("Status reg x16 0x%x.\n", flash_status);
+
+ break;
+
+
+ case 'e':
+
+ flash_erase_sectors( base_add + offset, 1 );
+
+ printf("Erase sector %d\n", offset);
+ break;
+
+
+ case 'u':
+
+ if ( argc == 5 )
+ {
+ ulong val_w = (ulong)simple_strtoul(argv[4], NULL, 16);
+
+ flash_enter_unlock_bypass(base_add);
+
+ printf("unlock programming x16 0x%x = 0x%lx\n", offset, val_w);
+ write_to_flash( base_add, 0x0, 0xA0);
+ write_to_flash( base_add, offset, val_w);
+
+ flash_exit_unlock_bypass(base_add);
+
+ read_from_flash( base_add, offset );
+ }
+ else
+ {
+ printf("\nMissing data to write\n");
+ }
+ break;
+ }
+ }
+ else
+ {
+ printf("\nMissing command add argc = %d\noptions are \n", argc);
+
+ printf("flash_id (0/1) r(read) offset\n");
+ printf("flash_id (0/1) w(write) offset val\n");
+ printf("flash_id (0/1) s(status register) offset\n");
+ printf("flash_id (0/1) p(write program) offset val \n");
+ printf("flash_id (0/1) u(unlock) offset val \n");
+ printf("flash_id (0/1) e(erase sector #1) offset\n");
+ }
+
+ return 0;
+}
+
+
+U_BOOT_CMD(
+ flash_test, 5, 1, test_cmd,
+ "test",
+ "command "
+);
+
+#endif
diff --git a/board/honeywell/tma/Kconfig b/board/honeywell/tma/Kconfig
--- a/board/honeywell/tma/Kconfig
+++ b/board/honeywell/tma/Kconfig
@@ -0,0 +1,16 @@
+
+
+if TARGET_TMA
+
+config SYS_BOARD
+ default "tma"
+
+config SYS_VENDOR
+ default "honeywell"
+
+config SYS_CONFIG_NAME
+ default "tma_config"
+
+endif
+
+source "board/ti/common/Kconfig"
diff --git a/board/honeywell/tma/Makefile b/board/honeywell/tma/Makefile
--- a/board/honeywell/tma/Makefile
+++ b/board/honeywell/tma/Makefile
@@ -0,0 +1,14 @@
+#
+# KS2-EVM: board Makefile
+# (C) Copyright 2012-2015
+# Texas Instruments Incorporated, <www.ti.com>
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += board.o
+obj-$(CONFIG_TARGET_TMA) += board_tma.o
+obj-$(CONFIG_TARGET_TMA) += ddr3_tma.o
+obj-$(CONFIG_TARGET_TMA) += gpmc_norflash.o
+obj-$(CONFIG_TARGET_TMA) += tma_utils.o
+obj-$(CONFIG_TARGET_TMA) += env_manager.o
+obj-$(CONFIG_TARGET_TMA) += post_tests.o
diff --git a/board/honeywell/tma/mux_tma.h b/board/honeywell/tma/mux_tma.h
--- a/board/honeywell/tma/mux_tma.h
+++ b/board/honeywell/tma/mux_tma.h
@@ -0,0 +1,299 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * K2G EVM: Pinmux configuration
+ *
+ * (C) Copyright 2015
+ * Texas Instruments Incorporated, <www.ti.com>
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/mux-k2g.h>
+#include <asm/arch/hardware.h>
+#include "../tma/board.h"
+
+
+/*
+ * See 66AK2G1x TRM
+ * section 5.1.4.149 for PAD Config register value.
+ * register add start at 0x0262_1000.
+ */
+
+struct pin_cfg tma_acu_pin_cfg[] = {
+ /* GPMC */
+ { 0, MODE(0) }, /* GPMC_AD0 */
+ { 1, MODE(0) }, /* GPMC_AD1 */
+ { 2, MODE(0) }, /* GPMC_AD2 */
+ { 3, MODE(0) }, /* GPMC_AD3 */
+ { 4, MODE(0) }, /* GPMC_AD4 */
+ { 5, MODE(0) }, /* GPMC_AD5 */
+ { 6, MODE(0) }, /* GPMC_AD6 */
+ { 7, MODE(0) }, /* GPMC_AD7 */
+ { 8, MODE(0) }, /* GPMC_AD8 */
+ { 9, MODE(0) }, /* GPMC_AD9 */
+ { 10, MODE(0) }, /* GPMC_AD10 */
+ { 11, MODE(0) }, /* GPMC_AD11 */
+ { 12, MODE(0) }, /* GPMC_AD12 */
+ { 13, MODE(0) }, /* GPMC_AD13 */
+ { 14, MODE(0) }, /* GPMC_AD14 */
+ { 15, MODE(0) }, /* GPMC_AD15 */
+ { 16, MODE(3) }, /* GPMC_CLK -> Unused */
+ { 17, MODE(3) }, /* GPMC_ADVN_ALE -> Unused */
+ { 18, MODE(0) }, /* GPMC_OEN_REN */
+ { 19, MODE(0) }, /* GPMC_WEN */
+ { 20, MODE(3) }, /* GPMC_BEN0_CLE -> Unused*/
+ { 21, MODE(3) }, /* GPMC_BEN1 -> Unused */
+ { 22, MODE(0) }, /* GPMC_WAIT0 */
+ { 23, MODE(0) }, /* GPMC_WAIT1 */
+ { 24, MODE(0) }, /* GPMC_WPN */
+ { 25, MODE(3) }, /* GPMC_DIR -> Unused */
+ { 26, MODE(0) }, /* GPMC_CSN0 */
+ { 27, MODE(0) }, /* GPMC_CSN1 */
+ { 28, MODE(3) }, /* GPMC_CSN2 -> Unused */
+ { 29, MODE(3) }, /* GPMC_CSN3 -> Unused */
+ { 30, MODE(1) }, /* GPMC_A24 */
+ { 31, MODE(1) }, /* GPMC_A23 */
+ { 32, MODE(1) }, /* GPMC_A22 */
+ { 33, MODE(1) }, /* GPMC_A21 */
+ { 34, MODE(1) }, /* GPMC_A20 */
+ { 35, MODE(1) }, /* GPMC_A19 */
+ { 36, MODE(1) }, /* GPMC_A18 */
+ { 37, MODE(1) }, /* GPMC_A17 */
+ { 38, MODE(1) }, /* GPMC_A16 */
+ { 39, MODE(1) }, /* GPMC_A15 */
+ { 40, MODE(1) }, /* GPMC_A14 */
+ { 41, MODE(1) }, /* GPMC_A13 */
+ { 42, MODE(1) }, /* GPMC_A12 */
+ { 43, MODE(1) }, /* GPMC_A11 */
+ { 44, MODE(1) }, /* GPMC_A10 */
+ { 45, MODE(1) }, /* GPMC_A9 */
+ { 46, MODE(1) }, /* GPMC_A8 */
+ { 47, MODE(1) }, /* GPMC_A7 */
+ { 48, MODE(1) }, /* GPMC_A6 */
+ { 49, MODE(1) }, /* GPMC_A5 */
+ { 50, MODE(1) }, /* GPMC_A4 */
+ { 51, MODE(1) }, /* GPMC_A3 */
+ { 52, MODE(1) }, /* GPMC_A2 */
+ { 53, MODE(1) }, /* GPMC_A1 */
+ { 54, MODE(1) }, /* GPMC_A25 */
+ { 55, MODE(1) }, /* GPMC_A26 */
+ { 56, MODE(3) }, /* GPMC_A27 -> Unused */
+ { 57, MODE(3) }, /* GPMC_A0 -> Unused */
+
+ /* GPIOs */
+ { 67, MODE(3) }, /* SPARE_OUT_PROCESSOR */
+ { 68, MODE(3) }, /* 24V_EN_PROCESSOR */
+ { 69, MODE(3) }, /* 12V_REF_EN_PROCESSOR */
+ { 70, MODE(3) }, /* PWR_OK_PROCESSOR */
+ { 71, MODE(3) }, /* SPARE_IN_PROCESSOR */
+ { 140, MODE(3) }, /* GPIO0_109 - DISCRETE_SPARE_2*/
+ { 141, MODE(3) }, /* GPIO0_110 - SHED_LOAD_N */
+ { 181, MODE(3) }, /* GPIO1_06 - TSM-105-01-S-DV #1*/
+ { 182, MODE(3) }, /* GPIO1_07 - TSM-105-01-S-DV #3*/
+ { 183, MODE(3) }, /* GPIO1_08 - TSM-105-01-S-DV #5*/
+ { 184, MODE(3) }, /* GPIO1_09 - TSM-105-01-S-DV #7*/
+ { 185, MODE(3) }, /* GPIO1_10 - TSM-105-01-S-DV #9*/
+ { 192, MODE(3) }, /* GPIO1_17 - EEPROM_WP */
+ { 217, MODE(3) }, /* GPIO1_42 - TX_MUTE_FF_CLR */
+ { 218, MODE(3) }, /* GPIO1_42 - TX_MUTE_PROC_IN */
+ { 219, MODE(3) }, /* GPIO1_43 - PROCESSOR_TX_MUTE */
+ { 220, MODE(3) }, /* GPIO1_44 - TX_MUTE_TRAN_DET */
+
+
+ /* A429 - GPIO Interrupts. */
+ { 73, MODE(3) }, /* GPIO0_73 - A429_IRS_BIT_HI */
+ { 74, MODE(3) }, /* GPIO0_74 - A429_IRS_BIT_LO */
+ { 142, MODE(3) }, /* GPIO0_111 - A429_AUX_DRVR_SPD_SEL */
+ { 143, MODE(3) }, /* GPIO0_112 - A429_IRS_DRVR_SPD_SEL */
+ { 145, MODE(3) }, /* GPIO0_114 - A429_MB1_1 */
+ { 146, MODE(3) }, /* GPIO0_115 - A429_MB1_2 */
+ { 147, MODE(3) }, /* GPIO0_116 - A429_MB1_3 */
+ { 148, MODE(3) }, /* GPIO0_117 - A429_MB2_1 */
+ { 149, MODE(3) }, /* GPIO0_118 - A429_MB2_2 */
+ { 150, MODE(3) }, /* GPIO0_119 - A429_MB2_3 */
+ { 151, MODE(3) }, /* GPIO0_120 - A429_RX1_INT */
+ { 152, MODE(3) }, /* GPIO0_121 - A429_RX2_INT */
+ { 153, MODE(3) }, /* GPIO0_122 - A429_RX1_FLAG_H */
+ { 154, MODE(3) }, /* GPIO0_123 - A429_RX2_FLAG_H */
+ { 199, MODE(3) }, /* GPIO1_24 - A429_AUX_BIT_HI*/
+ { 200, MODE(3) }, /* GPIO1_25 - A429_AUX_BIT_LO*/
+
+
+ /* EMAC - Check buffer class and PIN_PDIS ?*/
+ { 72, BUFFER_CLASS_D | PIN_PDIS | MODE(0) }, /* MII_RX_CLK */
+ { 77, BUFFER_CLASS_D | PIN_PDIS | MODE(0) }, /* MII_RXD3 */
+ { 78, BUFFER_CLASS_D | PIN_PDIS | MODE(0) }, /* MII_RXD2 */
+ { 79, BUFFER_CLASS_D | PIN_PDIS | MODE(0) }, /* MII_RXD1 */
+ { 80, BUFFER_CLASS_D | PIN_PDIS | MODE(0) }, /* MII_RXD0 */
+ { 81, BUFFER_CLASS_D | PIN_PDIS | MODE(0) }, /* MII_RX_DV */
+ { 82, MODE(0) }, /* MII_RX_ER */
+ { 83, MODE(0) }, /* MII_CD */
+ { 84, MODE(0) }, /* MII_CRS */
+ { 85, BUFFER_CLASS_D | PIN_PDIS | MODE(0) }, /* MII_TX_CLK */
+ { 91, BUFFER_CLASS_D | PIN_PDIS | MODE(0) }, /* MII_TXD3 */
+ { 92, BUFFER_CLASS_D | PIN_PDIS | MODE(0) }, /* MII_TXD2 */
+ { 93, BUFFER_CLASS_D | PIN_PDIS | MODE(0) }, /* MII_TXD1 */
+ { 94, BUFFER_CLASS_D | PIN_PDIS | MODE(0) }, /* MII_TXD0 */
+ { 95, BUFFER_CLASS_D | PIN_PDIS | MODE(0) }, /* MII_TX_EN */
+
+ /* MDIO */
+ { 98, BUFFER_CLASS_B | PIN_PDIS | MODE(0) }, /* ETH_PHY_MDIO (mode MDIO_DATA) */
+ { 99, BUFFER_CLASS_B | PIN_PDIS | MODE(0) }, /* ETH_PHY_MDC (mode MDIO_CLK) */
+
+ /* SPI0 A429 */
+ { 100, MODE(0) }, /* SOC_SPI0_SCS0 - A429_CS_L*/
+ { 102, MODE(0) }, /* SOC_SPI0_CLK - A429_SPI_CLK*/
+ { 103, MODE(0) }, /* SOC_SPI0_SOMI - A429_SPI_DATA_OUT*/
+ { 104, MODE(0) }, /* SOC_SPI0_SIMO - A429_SPI_DATA_IN*/
+
+ /* SPI1 PWR */
+ { 66, MODE(3) }, /* PWR_CND_SPI_INT */
+ { 105, MODE(0) }, /* SOC_SPI1_SCS0 - PWR_CND_CS_L*/
+ { 107, MODE(0) }, /* SOC_SPI1_CLK - PWR_CND_SPI_CLK */
+ { 108, MODE(0) }, /* SOC_SPI1_SOMI - PWR_CND_SPI_DATA_OUT*/
+ { 109, MODE(0) }, /* SOC_SPI1_SIMO - PWR_CND_SPI_DATA_IN*/
+
+
+ /* SPI2 ACCELMTR_CS_L */
+ { 110, MODE(0) }, /* SOC_SPI2_SCS0 - ACCELMTR_CS_L*/
+ { 112, MODE(0) }, /* SOC_SPI2_CLK - ACCELMTR_SPI_CLK */
+ { 113, MODE(0) }, /* SOC_SPI2_SOMI - ACCELMTR_SPI_DATA_OUT*/
+ { 114, MODE(0) }, /* SOC_SPI2_SIMO - ACCELMTR_SPI_DATA_IN*/
+
+ /* UART0 */
+ { 115, MODE(0) }, /* SOC_UART0_RXD */
+ { 116, MODE(0) }, /* SOC_UART0_TXD */
+ { 117, MODE(0) }, /* SOC_UART0_CTSn */
+ { 118, MODE(0) }, /* SOC_UART0_RTSn */
+
+ /* UART1 */
+ { 119, MODE(0) }, /* SOC_UART1_RXD */
+ { 120, MODE(0) }, /* SOC_UART1_TXD */
+ { 121, MODE(0) }, /* SOC_UART1_CTSn */
+ { 122, MODE(0) }, /* SOC_UART1_RTSn */
+
+ /* UART2 */
+ { 123, MODE(3) }, /* SOC_UART2_RXD -> Unused */
+ { 124, MODE(3) }, /* SOC_UART2_TXD -> Unused */
+ { 125, MODE(3) }, /* UART2_CTSn -> Unused */
+ { 126, MODE(3) }, /* UART2_RTSn -> Unused */
+
+ /* DCAN */
+ /* Keeping CAN0 PAD to default. Setting it too early caused issue with peripheral */
+ /*{ 127, MODE(0) }, SOC_DCAN0_TX */
+ /*{ 128, MODE(0) }, SOC_DCAN0_RX */
+ { 137, MODE(1) }, /* SOC_DCAN1_TX */
+ { 138, MODE(1) }, /* SOC_DCAN1_RX */
+
+ /* QSPI */
+ { 129, MODE(0) }, /* SOC_QSPI_CLK */
+ { 130, MODE(0) }, /* SOC_QSPI_RTCLK */
+ { 131, MODE(0) }, /* SOC_QSPI_D0 */
+ { 132, MODE(0) }, /* SOC_QSPI_D1 */
+ { 133, MODE(0) }, /* SOC_QSPI_D2 */
+ { 134, MODE(0) }, /* SOC_QSPI_D3 */
+ { 135, MODE(0) }, /* SOC_QSPI_CSN0 */
+ { 136, MODE(0) }, /* SOC_QSPI_CSN1 */
+
+ /* I2C */
+ /* No PAD registers - Single mode is I2C*/
+
+ /* unused */
+ { 58, MODE(3) }, /* unused */
+ { 59, MODE(3) }, /* unused */
+ { 60, MODE(3) }, /* unused */
+ { 61, MODE(3) }, /* unused */
+ { 62, MODE(3) }, /* unused */
+ { 63, MODE(3) }, /* unused */
+ { 64, MODE(3) }, /* unused */
+ { 65, MODE(3) }, /* unused */
+ { 75, MODE(3) }, /* unused */
+ { 76, MODE(3) }, /* unused */
+ { 86, MODE(3) }, /* unused */
+ { 87, MODE(3) }, /* GPIO0_87 - unused */
+ { 88, MODE(3) }, /* unused */
+ { 89, MODE(3) }, /* unused */
+ { 90, MODE(3) }, /* unused */
+ { 96, MODE(3) }, /* unused */
+ { 97, MODE(3) }, /* unused */
+ { 101, MODE(3) }, /* unused */
+ { 106, MODE(3) }, /* GPIO0_100 - unused */
+ { 111, MODE(3) }, /* unused */
+ { 139, MODE(3) }, /* unused */
+ { 144, MODE(3) }, /* unused */
+ { 155, MODE(3) }, /* unused */
+ { 156, MODE(3) }, /* unused */
+ { 157, MODE(3) }, /* unused */
+ { 158, MODE(3) }, /* unused */
+ { 159, MODE(3) }, /* unused */
+ { 160, MODE(3) }, /* unused */
+ { 161, MODE(3) }, /* unused */
+ { 162, MODE(3) }, /* unused */
+ { 163, MODE(3) }, /* unused */
+ { 164, MODE(3) }, /* unused */
+ { 165, MODE(3) }, /* unused */
+ { 166, MODE(3) }, /* unused */
+ { 167, MODE(3) }, /* unused */
+ { 168, MODE(3) }, /* unused */
+ { 169, MODE(3) }, /* unused */
+ { 170, MODE(3) }, /* unused */
+ { 171, MODE(3) }, /* unused */
+ { 172, MODE(3) }, /* unused */
+ { 173, MODE(3) }, /* unused */
+ { 174, MODE(3) }, /* unused */
+ { 175, MODE(3) }, /* unused */
+ { 176, MODE(3) }, /* unused */
+ { 177, MODE(3) }, /* unused */
+ { 178, MODE(3) }, /* unused */
+ { 179, MODE(3) }, /* unused */
+ { 180, MODE(3) }, /* unused */
+ { 186, MODE(3) }, /* unused */
+ { 187, MODE(3) }, /* unused */
+ { 188, MODE(3) }, /* unused */
+ { 189, MODE(3) }, /* unused */
+ { 190, MODE(3) }, /* unused */
+ { 191, MODE(3) }, /* unused */
+ { 193, MODE(3) }, /* unused */
+ { 194, MODE(3) }, /* unused */
+ { 195, MODE(3) }, /* unused */
+ { 196, MODE(3) }, /* unused */
+ { 197, MODE(3) }, /* unused */
+ { 198, MODE(3) }, /* unused */
+ { 201, MODE(3) }, /* unused */
+ { 202, MODE(3) }, /* unused */
+ { 203, MODE(3) }, /* unused */
+ { 204, MODE(3) }, /* unused */
+ { 205, MODE(3) }, /* unused */
+ { 206, MODE(3) }, /* unused */
+ { 207, MODE(3) }, /* unused */
+ { 208, MODE(3) }, /* unused */
+ { 209, MODE(3) }, /* unused */
+ { 210, MODE(3) }, /* unused */
+ { 211, MODE(3) }, /* unused */
+ { 212, MODE(3) }, /* unused */
+ { 213, MODE(3) }, /* unused */
+ { 214, MODE(3) }, /* unused */
+ { 215, MODE(3) }, /* unused */
+ { 216, MODE(3) }, /* unused */
+ { 221, MODE(3) }, /* unused */
+ { 222, MODE(3) }, /* unused */
+
+ /* Single mode pin (can only be set to mode 0) */
+ { 229, MODE(0) }, /* NMIz */
+ { 230, MODE(0) }, /* LRESETz */
+ { 231, MODE(0) }, /* LRESETNMIENz */
+ { 235, MODE(0) }, /* RESETSTATn */
+ { 236, MODE(0) }, /* BOOTCOMPLETE - TP31*/
+ { 237, MODE(0) }, /* SYSCLKOUT - TP30*/
+ { 238, MODE(0) }, /* PLL_LOCK - TP29*/
+ { 258, MODE(0) }, /* USB0DRVVBUS */
+ { 259, MODE(0) }, /* USB1DRVVBUS */
+
+ /* PAD not defined from [232,234] and [239,257]*/
+ { MAX_PIN_N, }
+};
+
+void k2g_mux_config(void)
+{
+ configure_pin_mux(tma_acu_pin_cfg);
+}
diff --git a/board/honeywell/tma/post_tests.c b/board/honeywell/tma/post_tests.c
--- a/board/honeywell/tma/post_tests.c
+++ b/board/honeywell/tma/post_tests.c
@@ -0,0 +1,67 @@
+
+#include <common.h>
+#include <post.h>
+
+static ulong post_word = 0;
+static const char* post_mem_status = "NA";
+
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
+{
+ *phys_offset = 0;
+ *vstart = CONFIG_SYS_SDRAM_BASE;
+ *size = gd->ram_size;
+
+ printf("Memory Test. Start addr 0x%x size ", *vstart);
+ print_size(*size, "\n");
+ return 0;
+}
+
+ulong post_word_load(void)
+{
+ return post_word;
+}
+
+void post_word_store(ulong value)
+{
+ post_word = value;
+}
+
+
+void show_post_progress(unsigned int test_num, int before, int result)
+{
+ /* result after POST test */
+ if ( before == POST_AFTER )
+ {
+ /* Should always be true */
+ if ( test_num < post_list_size )
+ {
+ if ( CONFIG_SYS_POST_MEM_REGIONS == post_list[test_num].testid )
+ {
+ post_mem_status = (result == POST_PASSED) ? "Passed" : "Failed";
+ }
+ else
+ {
+ printf("Unexpected Post test [%s]. Status [%d]\n", post_list[test_num].name, result);
+ }
+ }
+ }
+
+}
+
+static int save_post_test_status(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ env_set("mem_post_status", post_mem_status);
+ printf("mem_post_status [%s]\n", post_mem_status);
+ return 0;
+}
+
+
+
+U_BOOT_CMD(
+ get_post_test_status, 1, 1, save_post_test_status,
+ "Call to get TMA post test status in env variable(s)",
+ "no parameters."
+);
diff --git a/board/honeywell/tma/tma_utils.c b/board/honeywell/tma/tma_utils.c
--- a/board/honeywell/tma/tma_utils.c
+++ b/board/honeywell/tma/tma_utils.c
@@ -0,0 +1,27 @@
+/*
+ * utils.c
+ *
+ * Created on: Oct. 15, 2021
+ * Author: user
+ */
+
+
+#include <common.h>
+#include "tma_utils.h"
+
+
+void print_reg(const reg_print_t *reg)
+{
+ // Set to 1 to print register values.
+#if 0
+ u32 idx = 0;
+
+ printf("\n");
+ while( reg[idx].name != 0 )
+ {
+ printf("%s add(0x%x) = 0x%x\n", reg[idx].name, (u32)reg[idx].add, *(u32*)(reg[idx].add));
+ idx++;
+ }
+ printf("\n");
+#endif
+}
diff --git a/board/honeywell/tma/tma_utils.h b/board/honeywell/tma/tma_utils.h
--- a/board/honeywell/tma/tma_utils.h
+++ b/board/honeywell/tma/tma_utils.h
@@ -0,0 +1,10 @@
+
+
+
+typedef struct
+{
+ const char* name;
+ volatile void *add;
+}reg_print_t;
+
+void print_reg(const reg_print_t *reg);
diff --git a/common/memsize.c b/common/memsize.c
--- a/common/memsize.c
+++ b/common/memsize.c
@@ -82,6 +82,7 @@
* and *base is saved after *(base+size) modification
* in first loop
*/
+ printf("DDR3 get_ram_size() return lower than expected value %d < %d\n", size, maxsize);
return (size);
}
}
diff --git a/drivers/net/phy/natsemi.c b/drivers/net/phy/natsemi.c
--- a/drivers/net/phy/natsemi.c
+++ b/drivers/net/phy/natsemi.c
@@ -15,6 +15,7 @@
#define DP83630_PHY_PTP_CLKOUT_EN (1<<15)
#define DP83630_PHY_RBR_REG 0x17
+#if 0
static int dp83630_config(struct phy_device *phydev)
{
int ptp_coc_reg;
@@ -42,6 +43,7 @@
.startup = &genphy_startup,
.shutdown = &genphy_shutdown,
};
+#endif
/* DP83865 Link and Auto-Neg Status Register */
@@ -61,6 +63,7 @@
return 0;
}
+#if 0
static int dp83865_parse_status(struct phy_device *phydev)
{
int mii_reg;
@@ -112,6 +115,7 @@
.startup = &dp83865_startup,
.shutdown = &genphy_shutdown,
};
+#endif
/* NatSemi DP83848 */
static int dp83848_parse_status(struct phy_device *phydev)
@@ -158,8 +162,10 @@
int phy_natsemi_init(void)
{
+#if 0
phy_register(&DP83630_driver);
phy_register(&DP83865_driver);
+#endif
phy_register(&DP83848_driver);
return 0;
diff --git a/drivers/net/ti/keystone_net.c b/drivers/net/ti/keystone_net.c
--- a/drivers/net/ti/keystone_net.c
+++ b/drivers/net/ti/keystone_net.c
@@ -26,7 +26,7 @@
DECLARE_GLOBAL_DATA_PTR;
-#ifdef KEYSTONE2_EMAC_GIG_ENABLE
+#if 0
#define emac_gigabit_enable(x) keystone2_eth_gigabit_enable(x)
#else
#define emac_gigabit_enable(x) /* no gigabit to enable */
@@ -387,13 +387,6 @@
{
struct ks2_eth_priv *priv = dev_get_priv(dev);
-#ifdef CONFIG_SOC_K2G
- keystone_rgmii_config(priv->phydev);
-#else
- keystone_sgmii_config(priv->phydev, priv->slave_port - 1,
- priv->sgmii_link_type);
-#endif
-
udelay(10000);
/* On chip switch configuration */
@@ -538,8 +531,11 @@
priv->emac_open = false;
/* These clock enables has to be moved to common location */
+ //Note KS2_ETHERNET_CFG register is by default set to MII ( value 0)
+#if 0
if (cpu_is_k2g())
writel(KS2_ETHERNET_RGMII, KS2_ETHERNET_CFG);
+#endif
/* By default, select PA PLL clock as PA clock source */
#ifndef CONFIG_SOC_K2G
@@ -719,8 +715,10 @@
priv->mdio_base = (void *)fdtdec_get_addr(fdt, mdio, "reg");
}
- if (priv->link_type == LINK_TYPE_SGMII_MAC_TO_PHY_MODE) {
- priv->phy_if = PHY_INTERFACE_MODE_SGMII;
+ if (priv->link_type == LINK_TYPE_SGMII_MAC_TO_PHY_MODE)
+ {
+ //priv->phy_if = PHY_INTERFACE_MODE_SGMII;
+ priv->phy_if = PHY_INTERFACE_MODE_MII;
pdata->phy_interface = priv->phy_if;
priv->sgmii_link_type = SGMII_LINK_MAC_PHY;
priv->has_mdio = true;
@@ -741,6 +739,12 @@
pdata->phy_interface = priv->phy_if;
priv->has_mdio = true;
}
+ else if (priv->link_type == LINK_TYPE_10G_MAC_TO_PHY_MODE)
+ {
+ priv->phy_if = PHY_INTERFACE_MODE_MII;
+ pdata->phy_interface = priv->phy_if;
+ priv->has_mdio = true;
+ }
return 0;
}
diff --git a/env/env.c b/env/env.c
--- a/env/env.c
+++ b/env/env.c
@@ -57,7 +57,7 @@
ENVL_FAT,
#endif
#ifdef CONFIG_ENV_IS_IN_FLASH
- ENVL_FLASH,
+ ENVL_NORFLASH,
#endif
#ifdef CONFIG_ENV_IS_IN_MMC
ENVL_MMC,
diff --git a/include/asm-generic/global_data.h b/include/asm-generic/global_data.h
--- a/include/asm-generic/global_data.h
+++ b/include/asm-generic/global_data.h
@@ -82,7 +82,7 @@
const void *multi_dtb_fit; /* uncompressed multi-dtb FIT image */
#endif
struct jt_funcs *jt; /* jump table */
- char env_buf[32]; /* buffer for env_get() before reloc. */
+ char env_buf[128]; /* buffer for env_get() before reloc. */
#ifdef CONFIG_TRACE
void *trace_buff; /* The trace buffer */
#endif
diff --git a/include/configs/tma_config.h b/include/configs/tma_config.h
--- a/include/configs/tma_config.h
+++ b/include/configs/tma_config.h
@@ -0,0 +1,269 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuration header file for TI's k2g-evm
+ *
+ * (C) Copyright 2015
+ * Texas Instruments Incorporated, <www.ti.com>
+ */
+
+#ifndef __CONFIG_TMA_H
+#define __CONFIG_TMA_H
+
+
+/* Platform type */
+#define CONFIG_SOC_K2G
+
+#define BOOT_MONITOR \
+ "boot_monitor_loadadd=0x80000000\0" \
+ "boot_monitor_fit_entry=mon-0\0" \
+ "install_boot_monitor=" \
+ "imxtract ${fit_loadaddr} ${boot_monitor_fit_entry} ${boot_monitor_loadadd};" \
+ "mon_install ${boot_monitor_loadadd};\0" \
+
+#define BOOT_POWER_MGNT \
+ "power_mgnt_loadadd=0x80010000\0" \
+ "power_mgnt_fit_entry=pmmc-0\0" \
+ "install_power_mgnt=" \
+ "imxtract ${fit_loadaddr} ${power_mgnt_fit_entry} ${power_mgnt_loadadd};" \
+ "rproc init; rproc load 0 ${power_mgnt_loadadd} 0x8354; rproc start 0;\0" \
+
+
+#define DUAL_BOOT_CMDS \
+ "fitA=0x30700000\0" \
+ "fitB=0x34300000\0" \
+ "set_ubootFlag=if itest *0x0C01FFFC -eq 0x31; then setenv uBootFlag primary; elif itest *0x0C01FFFC -eq 0x32; then setenv uBootFlag secondary; else setenv uBootFlag na; fi;\0" \
+ "bootcmd_fit=run set_ubootFlag; run args_all; saveenv; run install_boot_monitor;run install_power_mgnt;bootm ${fit_loadaddr}\0" \
+ "checkPrimaryImage=if iminfo ${fitA}; then setenv OPIMAGEVALID1 TRUE; else setenv OPIMAGEVALID1 FALSE; fi\0" \
+ "checkSecondaryImage=if iminfo ${fitB}; then setenv OPIMAGEVALID2 TRUE; else setenv OPIMAGEVALID2 FALSE; fi\0" \
+ "dual_boot_cmd=" \
+ "get_post_test_status; run checkPrimaryImage; run checkSecondaryImage; " \
+ "if test \"$OPIMAGEVALID1\" = \"TRUE\"; then " \
+ "echo \"Loading Primary FIT\" ; setenv imageFlag primary; setenv fit_loadaddr ${fitA}; run bootcmd_fit; " \
+ "elif test \"$OPIMAGEVALID2\" = \"TRUE\"; then " \
+ "echo \"Loading Secondary FIT\" ; setenv imageFlag secondary; setenv fit_loadaddr ${fitB}; run bootcmd_fit; " \
+ "else " \
+ "echo \"Primary and Secondary FIT both invalid for use. Halt!!\"; " \
+ "fi; \0" \
+
+/* U-Boot general configuration */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ DEFAULT_LINUX_BOOT_ENV \
+ "mem_lpae=1\0" \
+ "ipaddr=192.168.1.3\0" \
+ "gatewayip=192.168.1.1\0" \
+ "netmask=255.255.255.0\0" \
+ "serverip=192.168.1.4\0" \
+ BOOT_MONITOR \
+ BOOT_POWER_MGNT \
+ DUAL_BOOT_CMDS \
+ "args_all=setenv bootargs console=ttyS0,115200n8\0" \
+
+#define CONFIG_BOOTCOMMAND \
+ "run dual_boot_cmd"
+
+
+
+/* SPL SPI Loader Configuration */
+#define CONFIG_SPL_TEXT_BASE 0x0c0a0000
+
+
+/* Network */
+#define CONFIG_KSNET_NETCP_V1_5
+#define CONFIG_KSNET_CPSW_NUM_PORTS 2
+#define CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE
+#define PHY_ANEG_TIMEOUT 10000 /* PHY needs longer aneg time */
+
+#define CONFIG_SYS_FLASH_BASE (0x30000000)
+#define CONFIG_ENV_OFFSET (0x00600000)
+#define CONFIG_ENV_SIZE (256 << 10) /* 256 KiB */
+
+#define CONFIG_SF_DEFAULT_BUS 1
+#define CONFIG_SF_DEFAULT_CS 0
+
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_CADENCE_QSPI
+#define CONFIG_CQSPI_REF_CLK 384000000
+#endif
+
+#define SPI_MTD_PARTS KEYSTONE_SPI1_MTD_PARTS
+
+/* Memory configuration */
+#define CONFIG_SYS_MAX_FLASH_SECT (1024)
+#define CONFIG_SYS_MAX_FLASH_BANKS 2
+
+/* enable POST RAM tests */
+#define CONFIG_POST (CONFIG_SYS_POST_MEM_REGIONS)
+/* This is do define own reporting functions
+ * extern ulong post_word_load(void);
+ * extern void post_word_store(ulong value);
+ * */
+#define CONFIG_POST_EXTERNAL_WORD_FUNCS (1)
+
+/* *****************************************************************
+ * Following are configuration from include/configs/ti_armv7_keystone2.h.
+ * placed here to be able to modify CONFIG_EXTRA_ENV_SETTINGS
+ * *****************************************************************/
+#define CONFIG_SOC_KEYSTONE
+
+/* U-Boot Build Configuration */
+#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is a 2nd stage loader */
+
+/* SoC Configuration */
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_SPL_TARGET "u-boot-spi.gph"
+#define CONFIG_SYS_DCACHE_OFF
+
+/* Memory Configuration */
+#define CONFIG_SYS_LPAE_SDRAM_BASE 0x800000000
+#define CONFIG_MAX_RAM_BANK_SIZE (2 << 28) /* 512 MB */
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SPL_TEXT_BASE - \
+ GENERATED_GBL_DATA_SIZE)
+
+#ifdef CONFIG_SYS_MALLOC_F_LEN
+#define SPL_MALLOC_F_SIZE CONFIG_SYS_MALLOC_F_LEN
+#else
+#define SPL_MALLOC_F_SIZE 0
+#endif
+
+/* SPL SPI Loader Configuration */
+#define CONFIG_SPL_PAD_TO 65536
+#define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_PAD_TO - 8)
+#define CONFIG_SPL_BSS_START_ADDR (CONFIG_SPL_TEXT_BASE + \
+ CONFIG_SPL_MAX_SIZE)
+#define CONFIG_SPL_BSS_MAX_SIZE (32 * 1024)
+#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
+ CONFIG_SPL_BSS_MAX_SIZE)
+#define CONFIG_SYS_SPL_MALLOC_SIZE (32 * 1024)
+#define KEYSTONE_SPL_STACK_SIZE (8 * 1024)
+#define CONFIG_SPL_STACK (CONFIG_SYS_SPL_MALLOC_START + \
+ CONFIG_SYS_SPL_MALLOC_SIZE + \
+ SPL_MALLOC_F_SIZE + \
+ KEYSTONE_SPL_STACK_SIZE - 4)
+#define CONFIG_SYS_SPI_U_BOOT_OFFS CONFIG_SPL_PAD_TO
+
+/* SRAM scratch space entries */
+#define SRAM_SCRATCH_SPACE_ADDR CONFIG_SPL_STACK + 0x8
+
+#define TI_SRAM_SCRATCH_BOARD_EEPROM_START (SRAM_SCRATCH_SPACE_ADDR)
+#define TI_SRAM_SCRATCH_BOARD_EEPROM_END (SRAM_SCRATCH_SPACE_ADDR + 0x200)
+#define KEYSTONE_SRAM_SCRATCH_SPACE_END (TI_SRAM_SCRATCH_BOARD_EEPROM_END)
+
+/* UART Configuration */
+#define CONFIG_SYS_NS16550_MEM32
+#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_DM_SERIAL)
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE -4
+#endif
+#define CONFIG_SYS_NS16550_COM1 KS2_UART0_BASE
+#define CONFIG_SYS_NS16550_COM2 KS2_UART1_BASE
+
+#ifndef CONFIG_SOC_K2G
+#define CONFIG_SYS_NS16550_CLK ks_clk_get_rate(KS2_CLK1_6)
+#else
+#define CONFIG_SYS_NS16550_CLK ks_clk_get_rate(uart_pll_clk) / 2
+#endif
+
+/* SPI Configuration */
+#define CONFIG_SYS_SPI_CLK ks_clk_get_rate(KS2_CLK1_6)
+#define CONFIG_SF_DEFAULT_SPEED 30000000
+#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
+#define CONFIG_SYS_SPI0
+#define CONFIG_SYS_SPI_BASE KS2_SPI0_BASE
+#define CONFIG_SYS_SPI0_NUM_CS 4
+#define CONFIG_SYS_SPI1
+#define CONFIG_SYS_SPI1_BASE KS2_SPI1_BASE
+#define CONFIG_SYS_SPI1_NUM_CS 4
+#define CONFIG_SYS_SPI2
+#define CONFIG_SYS_SPI2_BASE KS2_SPI2_BASE
+#define CONFIG_SYS_SPI2_NUM_CS 4
+#ifdef CONFIG_SPL_BUILD
+#undef CONFIG_DM_SPI
+#undef CONFIG_DM_SPI_FLASH
+#endif
+
+/* Network Configuration */
+#define CONFIG_BOOTP_DEFAULT
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_NET_RETRY_COUNT 32
+#define CONFIG_SYS_SGMII_REFCLK_MHZ 312
+#define CONFIG_SYS_SGMII_LINERATE_MHZ 1250
+#define CONFIG_SYS_SGMII_RATESCALE 2
+
+/* Keyston Navigator Configuration */
+#define CONFIG_TI_KSNAV
+#define CONFIG_KSNAV_QM_BASE_ADDRESS KS2_QM_BASE_ADDRESS
+#define CONFIG_KSNAV_QM_CONF_BASE KS2_QM_CONF_BASE
+#define CONFIG_KSNAV_QM_DESC_SETUP_BASE KS2_QM_DESC_SETUP_BASE
+#define CONFIG_KSNAV_QM_STATUS_RAM_BASE KS2_QM_STATUS_RAM_BASE
+#define CONFIG_KSNAV_QM_INTD_CONF_BASE KS2_QM_INTD_CONF_BASE
+#define CONFIG_KSNAV_QM_PDSP1_CMD_BASE KS2_QM_PDSP1_CMD_BASE
+#define CONFIG_KSNAV_QM_PDSP1_CTRL_BASE KS2_QM_PDSP1_CTRL_BASE
+#define CONFIG_KSNAV_QM_PDSP1_IRAM_BASE KS2_QM_PDSP1_IRAM_BASE
+#define CONFIG_KSNAV_QM_MANAGER_QUEUES_BASE KS2_QM_MANAGER_QUEUES_BASE
+#define CONFIG_KSNAV_QM_MANAGER_Q_PROXY_BASE KS2_QM_MANAGER_Q_PROXY_BASE
+#define CONFIG_KSNAV_QM_QUEUE_STATUS_BASE KS2_QM_QUEUE_STATUS_BASE
+#define CONFIG_KSNAV_QM_LINK_RAM_BASE KS2_QM_LINK_RAM_BASE
+#define CONFIG_KSNAV_QM_REGION_NUM KS2_QM_REGION_NUM
+#define CONFIG_KSNAV_QM_QPOOL_NUM KS2_QM_QPOOL_NUM
+
+/* NETCP pktdma */
+#define CONFIG_KSNAV_PKTDMA_NETCP
+#define CONFIG_KSNAV_NETCP_PDMA_CTRL_BASE KS2_NETCP_PDMA_CTRL_BASE
+#define CONFIG_KSNAV_NETCP_PDMA_TX_BASE KS2_NETCP_PDMA_TX_BASE
+#define CONFIG_KSNAV_NETCP_PDMA_TX_CH_NUM KS2_NETCP_PDMA_TX_CH_NUM
+#define CONFIG_KSNAV_NETCP_PDMA_RX_BASE KS2_NETCP_PDMA_RX_BASE
+#define CONFIG_KSNAV_NETCP_PDMA_RX_CH_NUM KS2_NETCP_PDMA_RX_CH_NUM
+#define CONFIG_KSNAV_NETCP_PDMA_SCHED_BASE KS2_NETCP_PDMA_SCHED_BASE
+#define CONFIG_KSNAV_NETCP_PDMA_RX_FLOW_BASE KS2_NETCP_PDMA_RX_FLOW_BASE
+#define CONFIG_KSNAV_NETCP_PDMA_RX_FLOW_NUM KS2_NETCP_PDMA_RX_FLOW_NUM
+#define CONFIG_KSNAV_NETCP_PDMA_RX_FREE_QUEUE KS2_NETCP_PDMA_RX_FREE_QUEUE
+#define CONFIG_KSNAV_NETCP_PDMA_RX_RCV_QUEUE KS2_NETCP_PDMA_RX_RCV_QUEUE
+#define CONFIG_KSNAV_NETCP_PDMA_TX_SND_QUEUE KS2_NETCP_PDMA_TX_SND_QUEUE
+
+/* Keystone net */
+#define CONFIG_KSNET_MAC_ID_BASE KS2_MAC_ID_BASE_ADDR
+#define CONFIG_KSNET_NETCP_BASE KS2_NETCP_BASE
+#define CONFIG_KSNET_SERDES_SGMII_BASE KS2_SGMII_SERDES_BASE
+#define CONFIG_KSNET_SERDES_SGMII2_BASE KS2_SGMII_SERDES2_BASE
+#define CONFIG_KSNET_SERDES_LANES_PER_SGMII KS2_LANES_PER_SGMII_SERDES
+
+#define CONFIG_AEMIF_CNTRL_BASE KS2_AEMIF_CNTRL_BASE
+
+/* I2C Configuration */
+#define CONFIG_SYS_DAVINCI_I2C_SPEED 100000
+#define CONFIG_SYS_DAVINCI_I2C_SLAVE 0x10 /* SMBus host address */
+#define CONFIG_SYS_DAVINCI_I2C_SPEED1 100000
+#define CONFIG_SYS_DAVINCI_I2C_SLAVE1 0x10 /* SMBus host address */
+#define CONFIG_SYS_DAVINCI_I2C_SPEED2 100000
+#define CONFIG_SYS_DAVINCI_I2C_SLAVE2 0x10 /* SMBus host address */
+
+/* EEPROM definitions */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
+#define CONFIG_ENV_EEPROM_IS_ON_I2C
+
+
+/* U-Boot general configuration */
+#define CONFIG_MX_CYCLIC
+#define CONFIG_TIMESTAMP
+
+/* EDMA3 */
+#define CONFIG_TI_EDMA3
+
+/* Now for the remaining common defines */
+#include <configs/ti_armv7_common.h>
+
+/* we may include files below only after all above definitions */
+#include <asm/arch/hardware.h>
+#include <asm/arch/clock.h>
+#ifndef CONFIG_SOC_K2G
+#define CONFIG_SYS_HZ_CLOCK ks_clk_get_rate(KS2_CLK1_6)
+#else
+#define CONFIG_SYS_HZ_CLOCK get_external_clk(sys_clk)
+#endif
+
+
+#endif /* __CONFIG_TMA_H */
diff --git a/include/environment.h b/include/environment.h
--- a/include/environment.h
+++ b/include/environment.h
@@ -191,6 +191,7 @@
ENVL_EXT4,
ENVL_FAT,
ENVL_FLASH,
+ ENVL_NORFLASH,
ENVL_MMC,
ENVL_NAND,
ENVL_NVRAM,
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -1241,9 +1241,15 @@
# if CONFIG_IS_ENABLED(OF_PRIOR_STAGE)
gd->fdt_blob = (void *)prior_stage_fdt_address;
# else
- gd->fdt_blob = map_sysmem
- (env_get_ulong("fdtcontroladdr", 16,
+ /* capability after import(load) from persistent storage. */
+ if ( gd->flags & GD_FLG_ENV_READY )
+ {
+ printf("%s %s %d\n", __FILE__, __FUNCTION__, __LINE__);
+ gd->fdt_blob = map_sysmem
+ (env_get_ulong("fdtcontroladdr", 16,
(unsigned long)map_to_sysmem(gd->fdt_blob)), 0);
+ }
+
# endif
# endif
diff --git a/post/tests.c b/post/tests.c
--- a/post/tests.c
+++ b/post/tests.c
@@ -291,7 +291,7 @@
"Memory regions test",
"mem_regions",
"This test checks regularly placed regions of the RAM.",
- POST_ROM | POST_SLOWTEST | POST_PREREL,
+ POST_ROM | POST_SLOWTEST | POST_PREREL | POST_POWERON | POST_CRITICAL,
&memory_regions_post_test,
NULL,
NULL,
defconfig:
CONFIG_ARM=y CONFIG_ARCH_KEYSTONE=y CONFIG_SYS_TEXT_BASE=0xC020000 CONFIG_TI_COMMON_CMD_OPTIONS=y CONFIG_TARGET_TMA=y CONFIG_DISTRO_DEFAULTS=y CONFIG_NR_DRAM_BANKS=3 CONFIG_OF_BOARD_SETUP=y # CONFIG_USE_BOOTCOMMAND is not set CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_VERSION_VARIABLE=y CONFIG_BOARD_EARLY_INIT_F=y # CONFIG_CMD_FLASH is not set # CONFIG_CMD_GPIO is not set # CONFIG_CMD_GPT is not set # CONFIG_CMD_MMC is not set CONFIG_CMD_REMOTEPROC=y # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_EXT4_WRITE is not set CONFIG_MTDIDS_DEFAULT="nand0=davinci_nand.0" CONFIG_MTDPARTS_DEFAULT="mtdparts=davinci_nand.0:1024k(bootloader)ro,512k(params)ro,-(ubifs)" CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="tma" CONFIG_DTB_RESELECT=y CONFIG_MULTI_DTB_FIT=y CONFIG_ENV_IS_IN_FLASH=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_DM=y CONFIG_BLK=y CONFIG_SYS_I2C_DAVINCI=y # CONFIG_MMC is not set CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_NAND=y CONFIG_NAND_DAVINCI=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y CONFIG_PHY_NATSEMI=y CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_DRIVER_TI_KEYSTONE_NET=y CONFIG_PHY=y CONFIG_NOP_PHY=y CONFIG_REMOTEPROC_TI_POWER=y CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_DAVINCI_SPI=y # CONFIG_EFI_LOADER is not set
