• State
  • Locked Locked
  • Replies 3 replies
  • Subscribers 100 subscribers
  • Views 61 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

AM3356: DDR2 timing parameter calculation

Prashant Patil
Prodigy 115 points
Part Number: AM3356

Tool/software:

Hello Team,

Hardware board : Custom board based on beaglebone reference.

SoC Used        : AM3356
Uboot version  : U-Boot SPL 2021.04
Linux kernel version : 5.4.188

SDRAM Used         : W972GG6JB-25I
SDRAM frequency  : 266 MHz

Some of our boards stuck at memory test during SPL-uboot and some are stuck at "starting kernel ..." That is reason we want to reconfirm SDRAM timings are correct.

Could you please share any utility to calculate DDR2 timings ?  


Please confirm the attached timings are correct ?6318.ddr_defs.h

#define W972GG6JB_25I_EMIF_SDCFG 0x40804EB2
#define W972GG6JB_25I_EMIF_SDREF 0x0000081a
#define W972GG6JB_25I_EMIF_TIM1 0x0666B3D1
#define W972GG6JB_25I_EMIF_TIM2 0x123D31CA
#define W972GG6JB_25I_EMIF_TIM3 0x0000033F

#define W972GG6JB_25I_RD_DQS 0x40
#define W972GG6JB_25I_WR_DQS 0x00

  • 0
    TI__Guru* 80260 points

    We don't have a utility for DDR2 timings, they would have to be calculated manually. 

    Those definitions have been around for many years, i wouldn't think they are incorrect.  What has changed?  Are these new board builds?

    Regards,

    James

  • 0 in reply to JJD
    Prodigy 115 points

    Are these new board builds? 

    > Yes its new design being manufactured for the first time. 

    Originally value of this macro from reference code was  "W972GG6JB_25I_RD_DQS"  0x12

    During testing at manufacturer site, we observed Checksum mismatch issue for linux kernel image and memtest failure over few boards.

    We tried to compare values of these registers with TRM and found "W972GG6JB_25I_RD_DQS"  to be  0x40. Post this change all those boards are seems to be working fine. We just want to confirm with you that whether rest of register values in attached file are correct . Could you please confirm this ?

  • 0 in reply to Prashant Patil
    TI__Guru* 80260 points

    What is the origin of this file? RD_DQS = 0x40 and WR_DQS = 0x0 should be correct.  I'm not sure why you originally had RD_DQS=0x12. 

    Do you have a DDR datasheet?

    Regards,

    James