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DRA829V-Q1: DRA829VMT0CALFRQ1

Mathias Sixtander
Prodigy 10 points
Part Number: DRA829V-Q1
Other Parts Discussed in Thread: DRA829, DRA821

Tool/software:

Hi,

We have seen leakage problems for VSYS_MCUIO_3V3 (U22) and VSYS_IO_3V3 (U6). Both rails are supplied by VSYS_3V3 and each rail is controlled by a load switch (see attached schematic).  

During disabling PMIC_EN we can see that the Voltage on VSYS_IO_3V3 only goes down to ~1,76V and the VSYS_MCUIO_3V3 goes down to ~1,5V (see attached pictures 1&2).

We have already verified that the two load switches U6 and U22 are fully disabled via the control signals (low state confirmed). 

For the VSYS_MCUIO_3V3 we have found that when VOUT_LDOVINT (PMICA and PMICB) are disable (LP_STANDBY_SEL=1) the leakage goes down to ~0.8V. 

We have removed all peripherals connected to the VSYS_IO_3V3 and we could only see that the voltage increased when different loads (peripherals) were disconnected from the rail.

Our conclusion is now that the leakage source comes from the MPU (DRA829VMT0CALFRQ1) only. 

The power up and down sequence are affected by this leakage and will not fulfil the power down/ up timing diagrams of the DRA829 datasheet.

We have not seen any negative impact affecting the performance from our testing but would like to get this confirmed by you because the power up and  down sequence are not fulfilled

according to the DRA829 datasheet. 

Could this affect the performance in any way if the power rails (VSYS_MCUIO_3V3 and VSYS_IO_3V3) doesn't turn off completely? 

Thanks for your support!

Best regards

/Mathias Sixtander

Picture1: Leakage on VSYS_MCUIO_3V3

Picture2: Leakage on VSYS_IO_3V3

  • 0
    TI__Guru 52162 points

    Hello Mathias,

    We sometimes see the SoC vddshv* supply rails "dragged up" when one or more of the corresponding IOs are being pulled/driven by external circuitry that may still be powered.  E.g., if a bootmode pin is pulled to the "wrong" external 3.3V supply that is still powered when the SoC's 3.3V rail is unpowered. 

    Can you check that?

    Regards,

    Kyle

  • 0 in reply to kcastille
    Prodigy 10 points

    Hi Kyle, 

    Thanks for the information! Yes, we will try to check this.

    Regards

    /Mathias

  • 0 in reply to Mathias Sixtander
    TI__Expert 6245 points

    Additionally, there is an update coming to all TDA4x, DRA829 & DRA821 DMs. The recommended power down sequencing will add a 2nd option for an immediate shutdown. This allows all SoC supplies to be disabled in any order after 1us delay following PORz signals being asserted low, Therefore, the SoC reliability will not be impacted by supplies being at various voltage levels after PORz signals have been asserted low.

  • 0
    Prodigy 10 points

    Hi Kyle,

    As you explained we could see that the SoC vddshv supply rails were "dragged up" when one of the bootmode pins was pulled to a 3.3V supply that was still powered when the SoC's 3.3V rail was unpowered. Thanks for the information about this issue. We now have another question.

    When doing a PMIC cycling we can see that the corresponding IOs are following the vddshv voltage. Can you confirm that the IOs are pulled low when vddshv goes low during a PMIC cycle? Unfortunately we have signals connected between the DRA829 and a MCU that needs to be in high impedance state during the loss of SoC vddshv.

    Regards

    /Mathias