Tool/software:
Hello,
On our custom board we will be using the internal reference clock (core_refclk) to the 4 lane SERDES.
The internal reference clock is input-muxed; we will be using the MAIN_PLL2_HSDIV4_CLKOUT (100 MHz) input to that mux. We are familiar with how to configure this (see https://software-dl.ti.com/jacinto7/esd/processor-sdk-linux-am69/latest/exports/docs/linux/Foundational_Components/Kernel/Kernel_Drivers/SERDES/SERDES.html).
We also need to source out the PCIe reference clock from the SERDES to our PCIe endpoint (I believe this is called the "ACSPCIe buffer clock," as referred to in Table 12-201 of the AM69 TRM). However, that is not covered in the documentation that I linked above. After doing some digging and attempting to compare to the J784S4EVM, we think that the following constants can be used in the device tree to source out the PCIe reference clock from the SERDES (from https://git.ti.com/cgit/ti-linux-kernel/ti-linux-kernel/tree/include/dt-bindings/phy/phy-cadence.h?id=db88712931433e92a5f73cec57c82c5c7ebee593#n13):
/* Torrent */
#define CDNS_TORRENT_REFCLK_DRIVER 0
#define CDNS_TORRENT_DERIVED_REFCLK 1
#define CDNS_TORRENT_RECEIVED_REFCLK 2Assuming that is correct, my question is, which of these values is the correct one to enable ACSPCIe with the 100MHz clock from MAIN_PLL2_HSDIV4_CLKOUT (which is my SERDES internal reference clock)? And if you wanted to provide a brief description of what all three of these values mean, perhaps that could be helpful to others.
Thank you very much, and best regards,
Dave
