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AM67: DRC warning on AM67x EVM and Beagle AI

Part Number: AM67
Other Parts Discussed in Thread: BEAGLEY-AI

Tool/software:

Dear Champ, 

Customer feedbacks the current AM67x EVM and Beagle AI layout and PCBA contains DRC waring and worry to cause assembly quality issue. 

What's the recommendation to customer on this DRC warning ? Just nore and remove it? 

Referring to the PCB layout files in these two CRBs, they had common issue of Via in Pad at the MPU opposite layer and DDR region.

The impacted components were de-coupling capacitors and this result would cause passive parts be dropped easily after assembly.

In general, this abnormal condition would cause DRC warning or error in Allegro as default.

However, SPRR495B and BeagleY-AI did not  show these messages. So it may be cancelled by manually. Is this correct? 

Please note the minimum dimension of these passive parts were down to 0201 package.

SPRR495B 

MPU portion

DRAM portion

Beagle AI:

MPU portion

DRAM portion

BR, Rich

  • DRC rules are setup per the board fabrication and board assembly capabilities.  Different fabrication/assembly suppliers have different capabilities - thus cannot have DRC rules for everyone.  Recommend working with your suppliers to determine their capabilities and set accordingly.  Via-In-Pad is a perfect example. Both our board fabrication and board assembly can support designs with Via-in-Pad, thus our design rules (DRC) do not flag this as a error.

  • Is there any additional process be done at factory side?

    If via in pad without additional process for assistance, no EMS companies can accept this condition for production.

  • I'm sorry I don't understand your question.  Are you asking if via-in-pad is required? A PCB can be design without via-in-pad.  The connection to the capacitor will have slightly higher inductance - making it slightly less effective.  The capacitors in the BGA area will have to be re-placed (due to increased space required without via-in-pad).  It is possible some capacitors can be moved to topside - and the shorter via travel length to internal power plane can help reduce loop inductance.  Lots of things to considered - but certainly a design can be created without via-in-pad.

  • Regarding the pros and cons of via in pad, the link below is a good material for reference.

    What Is Via in Pad

    Theoretically, to minimize unnecessary loading effect can improve SI / PI performance. But its side effect shall be taken carefully.

    On PCB manufacturing point of view, additional process (like via filled) takes additional charge and this is an optional requirement and lots of ODM / OEM skip this process as default.

  • I understand each design has it own set up PCB requirements.  Any additional questions?

  • That's all, thanks.