Tool/software:
Hi experts,
I would like to confirm the description in the C6713B datasheet.
power-supply sequencing
TI DSPs do not require specific power sequencing between the core supply and the I/O supply. However, systems should be designed to ensure that neither supply is powered up for extended periods of time (>1 second) if the other supply is below the proper operating voltage.
system-level design considerations
System-level design considerations, such as bus contention, may require supply sequencing to be implemented. In this case, the core supply should be powered up prior to (and powered down after), the I/O buffers. This is to ensure that the I/O buffers receive valid inputs from the core before the output buffers are powered up, thus, preventing bus contention with other chips on the board.
Q:Could you please tell me the specific conditions, situations, and uses of "when it is necessary to implement a power supply sequence"?
① From the above "TI DSPs do not require specific power sequencing between the core supply and the I/O supply", I understand that "There is no problem if there is no time difference of more than 1 second between the rise of the core voltage and the I/O voltage."
② However, from the above "system-level design considerations", there is a contradiction in the interpretation of ①.
Best regards,
O.H
