TDA4APE-Q1: Lowest possible power mode With a DDR

Hello Mahmoud,

Mahmoud Shaker said:

To have MCU1 active with its CPSW switch for ethernet communication.

Quoting the TRM Block diagram:

The CPSW switch is part of the main domain & hence we cannot turn off the main domain if CPSW switch functionality is needed.

Mahmoud Shaker said:

We have very strict power requirements to go as low as 1-1.5W in the SoC, however, we still have to keep a DDR active for code and data holding.

This cannot be achieved when you are having the main domain On.

Mahmoud Shaker said:

• To switch off any other processors, accelerators or peripherals either by SW or externally by shutting down the power rail.
• The total power consumption of the SoC shall not exceed a total of 1.5W

It will be possible to keep the Processors in WFI. The power consumption will not be as low as 1.5W.

- Keerthy

Thanks for your reply 
I have some  questions 

1-InCase of MCU only mode , what is the available memories to be used and what is its size ?

2-Is it possible that after the soc initialization done in Normal mode , then by manipulating bucks/PMIC shutdown the other cores but keep the DDR accessible ?

3-if we put the all the cores into WFI except for the MCU (To use only the DDR) what is the estimated power consumption ?

Hi,

I am looping in our hardware experts.

Best Regards,

Keerthy 

Hello all, 
any updated regarding the questions ?

1-InCase of MCU only mode , what is the available memories to be used and what is its size ?

2-Is it possible that after the soc initialization done in Normal mode , then by manipulating bucks/PMIC shutdown the other cores but keep the DDR accessible ?

3-if we put the all the cores into WFI except for the MCU (To use only the DDR) what is the estimated power consumption ?

Mohamed,

There is a 1MB RAM on the MCU domain.
MCU_MSRAM_1MB0_RAM at 0x00_41C0_0000

You can power-down many of the power domains in the MAIN domain (e.g. PD_C71x_0, PD12) but there is much logic that cannot be powered down and you need it in order to communicate across the SoC to the DDR.

Kevin

Hello Kevin 

This is not a Complete answer.

• 1MB is not enough for the code the needed to be during the low power mode so DDR is a Must.
• As this needs to be implemented ASAP , What is exactly need to still be powered on to access the DDR while powering down the rest of the Main Domain to reach the lowest power possible ?
• What is the estimated power consumption in this case ?

Waiting for you response.

Best regards,

There is a power estimate tool online; I have run it using the MCU-only use case and then added-in the CORE and CPU domain voltages as well as 30% loading on the 4 LPDDRs. This leads to a much higher than desired power:

Kevin

Thanks this is much clear now 
I see that the estimation is done for 3 DDRs , If the SW disabled 2 DDRs and Kept only 1 powered on 

• As long as the DDRs connected to Different PHYs This is feasible , Correct ?
•  Does TDA4APE-Q1 have multi PHYs for DDRs ?
• In case 2 DDRs disabled we can subtract (30% *1067 *2) from the total power , correct ?

Best regards ,

Reducing to a single DDR gives:

Mohamed Elsemellawy said:

• As long as the DDRs connected to Different PHYs This is feasible , Correct ?
•  Does TDA4APE-Q1 have multi PHYs for DDRs ?

What about these questions ?

Mohamed,

The device has two PHYs, each of which is connected to its own DDR memory. You cannot switch on the fly from using 1 DDRSS to using 2 DDRSS so if you are planning to use only 1 DDRSS in this mode, you must go through a full MCU_PORz if you want to use 2 DDRSS.

Kevin