• State Resolved
  • +1 person also asked this people also asked this
  • Replies 2 replies
  • Subscribers 100 subscribers
  • Views 153 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

[FAQ] AM625 / AM623 / AM62A / AM62D-Q1 / AM62P / AM62L / AM64x / AM243x Design Recommendations / Custom board hardware design – Queries related to Discrete power Architecture

Kallikuppa Sreenivasa
Guru**** 171664 points
Part Number: AM625
Other Parts Discussed in Thread: AM62P, AM62L

Tool/software:

HI TI experts,

We are considering implementing power architecture using discrete DC/DC and LDO.

Do you have some recommendations or recommendation for the below:

1. Power sequencing 

2. Current consumption

3. Supply Slew rate 

4. Process cold reset input control - delay after supply ramp, slew rate and IO level 

5. Power architecture when VDD_CORE is 0.75V and 0.85V 

6. Power architecture when partial IO mode is implemented 

  • +1
    TI__Guru**** 171664 points

    HI Board designers, 

    1. Power sequencing 

    The recommendation is to follow the Power Supply Sequencing section of the processor-specific data sheet. 

    2. Current consumption

    AM625

    AM62x Maximum Current Ratings

    https://www.ti.com/lit/pdf/sprada6

    AM62A

    AM62Ax Maximum Current Ratings

    https://www.ti.com/lit/pdf/sprada7

    AM62D

    AM62P

    AM62L

    AM62L Maximum Current Ratings

    https://www.ti.com/lit/pdf/spradr4

    3. Supply Slew rate 

    Follow the Power Supply Slew Rate Requirement section of the processor-specific data sheet. 

    4. Process cold reset input - delay after supply ramp, slew rate and IO level 

    A delay specified in the data sheet after all the supplies ramp for clock to start-up and settle is required to be provided before the Power Good output from the discrete DC/DC connects to the MCU_PORz (PORz for AM62L) input.

    This is a cold reset input and has internal hysteresis. A slow ramp input could glitch the internal reset. Minimize the slew rate or use a fast rise time discrete push pull output buffer with hysteresis. 

    5. Power architecture when VDD_CORE is 0.75V and 0.85V 

    When the core voltage is 0.75V, 0.75V is required to be available before the 0.85V (VDDR_CORE)  supply ramps.

    When the core voltage is 0.86V, VDD_CORE and VDDR_CORE is recommended to be connected to the same supply source.

    6. Power architecture when partial IO mode is implemented 

    An always ON VDD_CANUART and VDDSHV_CANUART supplies are required to be generated and must be available before  the other supplies ramp.

    Regards,

    Sreenivasa

  • 0 in reply to Kallikuppa Sreenivasa
    TI__Guru**** 171664 points

    HI Board designers, 

    Inputs on power supply sizing:

    Using Maximum Current Ratings application note vs Power Estimation Tool PET 

    The max current app note is representing the current draw for a group of rails. Please note that it is not expected for this current to necessarily be replicated in the power estimation tool. The PET will tend to show more average use case power while the max current app note is intended to be used for power supply sizing as it will allow for the max transient on these groups with some margin. The PET should not be used for power supply sizing.

    Regards,

    Sreenivasa