• State Resolved
  • Locked Locked
  • Replies 1 reply
  • Subscribers 98 subscribers
  • Views 134 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

[FAQ] AM62L: DDR4 guidelines for impedance values

Kallikuppa Sreenivasa
Guru**** 179019 points
Part Number: AM62L

Tool/software:

Customer Query:

In our design we are using the DDR4 interface. In your DDR4 guidelines you have mentioned 40 ohms for single-ended and 80ohms for the differential pair. Is it mandatory to follow these impedance values or shall we continue with 50ohm single ended and 100 ohms differential ?

As per our stack-up for 8 layer board with 4mil trace width we are getting 58ohm single ended that's why we have raised this query.

  • 0
    TI__Guru**** 179019 points

    Hi team, 

    The below answer assumes customer is using x1 16-bit DDR4 memory.

    Then higher impedance is okay.

    In lightly loaded signals, such as point-to-point signaling; 50 to 60 ohm single-ended and 80 to 100 ohm differential are common.

    Keep in mind tolerance of manufacture may add or subtract 10% to the actual impedance.

    It is easier to lower trace impedance by using wider traces than make traces thinner as they sometimes become too thin for manufacture. Dielectric thickness in the stack-up (distance from reference plane) is the other way to change impedance.

    Additional inputs

    If there are multiple DRAMs and the command/address hit multiple loads, then it may be required to use lower impedance - 35 to 45 ohm single-ended and 70 to 100 ohm differential.

    Regards,

    Sreenivasa