PROCESSOR-SDK-AM62X: AM62X main domain timeout register

Hi Chetana,

I am routing your query to our UART hardware expert for comments.

Hello Chetana,

Thank you.

Can you please share the calculations and configurations.

Regards,

Sreenivasa

Hi Sreenivasa,

for 9600 baud rate, time for 1 bit will be 1/9600 = 1.04166e-4, for 39(TIMEOUT VALUE) bits it should be 4.01ms timeout?

Hello Chetana,

Thank you.

Please add details of the section in the TRM you are referring, how are you measuring the timeout and also the software development environment being used.

Regards,

Sreenivasa

Hi Sreenivasa,

I am referring to 

I am measuring timeout with picoscope between 2 messages. TI SDK linux with customization for timeout register. for 9600 baudrate I have kept TIMEOUT  value as 39. so as per 9600 baudrate, 39 baud cycles should give delimiter of 4.01ms, but I am getting 3.5ms.

Hello Chetana,

Thank you.

Can you please try a few additional baud rates and let me know what you observe.

2400, 4800 and 19200

Regards,

Sreenivasa

couldnt test 2400, but for 4800 its 39 baud cycles and we are getting 6.8ms instead of 8ms

Hello Chetana,

Thank you.,

Let me check internally and update.

Regards,

Sreenivasa

Hello Chetana,

I am assigning to the software expert to support.

Regards,

Sreenivasa

Hello Chetana,

You’re encountering a known issue with the AM62x processor’s UART timeout behavior.

Specifically, the actual observed timeout is addressed in the AM62x Processor Silicon Revision 1.0 Errata, documented as issue i2310. 

Issue i2310: Erroneous Clear/Trigger of Timeout Interrupt

https://www.ti.com/lit/er/sprz487f/sprz487f.pdf?ts=1747204587297&ref_url=https%253A%252F%252Fwww.google.com%252F

Description:
The UART module may erroneously clear or trigger the timeout interrupt when reading the Receiver Holding Register (RHR), Modem Status Register (MSR), or Line Status Register (LSR). 

Workaround:
To mitigate this issue, implement the following steps:
1. Set a High Timeout Value:
Configure the TIMEOUTH and TIMEOUTL registers to a high value to prevent premature timeout interrupts.
2. Enable Periodic Timeout Mode:
Set bit 6 of the EFR2 register to 1 to switch the timeout behavior to periodic mode.
3. Clear the Interrupt:
Read the Interrupt Identification Register (IIR) to clear any pending timeout interrupts.
4. Restore Original Timeout Mode:
Reset bit 6 of the EFR2 register to 0 to revert to the original timeout behavior.

Regards,

Anil.

Hi Swargam,

we are already following the workaround mentioned by you and not hitting the loop, but still timeout value is getting affetected with minor error 

Hello Chethan ,

How did you implement the workaround ? Can you please share the details ?

Are you implementing this feature on the A53 core or any other core(DM or M4F) ?

If you are doing this feature on the A53 core, please mention which OS you are using ?

Regards,

Anil.

Hi Swargam,

We have implemented in same way as you have mentioned. we are evaluating it A53 core, with Linux OS.

Thanks

Hello Chethan ,

If you share what the code changes you made, this is helpful to review the code changes.

I am routing your query to a Linux expert to comment on your issue.

Regards,

Anil.