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DRA821U-Q1: DRA821U-Q1: Inquiry Regarding DRA821 SerDes Configuration for PCIe and Ethernet (USXGMII/RGMII)

Part Number: DRA821U-Q1
Other Parts Discussed in Thread: DRA821

Tool/software:

Dear DRA821 TEAM

Hello, this is regarding the DRA821 SoC.

I am planning to configure the SerDes lanes on the DRA821 as follows:

  • Lane 0 and Lane 1: PCIe Gen3 (2 lanes)

  • Lane 2: USXGMII (10G) or HSGMII(2.5G)

  • Lane 3: RGMII

In this configuration, I would like to know if:

  1. Lane 2 (USXGMII) and Lane 3 (RGMII) can both be used as native Ethernet interfaces.

  2. It is possible to use USXGMII as ETH1 and RGMII as ETH2 independently, with both interfaces functioning simultaneously.

Could you please confirm whether this configuration is supported?

Thank you very much in advance for your support.

Best regards