AM6422: DDR4: CA lines not in phase with CS

Hi Christian, same questions as on the other post.  Let's start with ensuring you are using the best configuration for your design and device.

-Send ddr configuration file and part number.

Regards,

James

Hi James.

Part number and config posted on the other post

regards,

Christian

Hi Christian, have you tried the suggestion from the other post?

James

Hi James.

Same question as in other post: Why should a CL change affect this timing? I would expect that it´s just shifted by full CLK cycle(s). But the relative delay from CS to CLK shouldn't be affected?

BR,

Christian

Hi Christian,

Ok, agree.  Are the two different scope shots from two different boards, or two different boots of the same board?  I'm wondering if this is a training issue.  I think the register dump requested from the other post would be helpful here.

Also, just wanted to confirm if all of the requirements from the layout guidelines here: https://www.ti.com/lit/pdf/spracu1 were considered during design.

Regards,

James

Hi James.

I´ll forward your question to our partner, who did the measurements. But it is definitely the same board and I assume also the same boot.

Our Firmware guys currently implementing the register dump code. Is expected beginning next week.

We tried to followed the guidelines as good as possible. Especially the propagation delay in the ADR_CTRL group (Table 3-6) is according to the guidelines

Regards,

Christian

Ok, sounds like the design is good.  We will wait the register dump.  As mentioned on other thread, let me see if i can get some waveforms from our EVM

Regards,

James

Hi James.

Register dump posted in the other thread.

regards, Christian

Thanks Christian, i didn't have time to look at it today, will check tomorrow.

James

Hi James.

Thanks a lot, that works!

The attached pictures were taken with a "low" bandwidth scope, but the effect is clearly visible.

Just to be sure: This setting just affecting the CS signal, no other signals, right?

initial value 0x03900390

optimized value: 0x3900200

best regards,

Christian

Ok, thanks for the confirmation.  Yes, this will only affect CS0

regards,

james