Original question:
Tool/software:
Hi,
For our project we need BT656 output (I found the patch set that implements this on the forum already) with interlaced mode.
I understand this is not currently supported, but would it be possible to get some support in implementing this?
Either implementation at TI, or some support/pointers on what needs to be modified in the driver to be able to support interlaced mode.
Regards,
Bas Vermeulen
Hi,
In general, for BT.656 mode, you need 2 pixel clock cycles to send out 1 pixel, and hence the resolution is limited. Each pixel clock transfers 1byte data and 2 pixel data is interleaved into 4 bytes in the UYVY format:
In case of 8-bit mode, lines D2 to D9 are utilized, while in 10bit mode lines D0 to D9 are utilized.
Would recommend going through relevant TRM sections for further info.
Hi Divyansh,
Unfortunately there is still problem with the interlaced mode. We have half of the picture of the frame buffer shown on the screen:
This pattern is result of the command:
rwmem 0x30208000=0x2
Bottom part of the pattern is missing.
Hi Divyansh,
I put the values of the registers in the kernel tidss driver and I get this picture when starting kmstest:
I have this output from kmstest on the console:
# kmstest
[ 50.645920] tidss 30200000.dss: tidss_crtc_mode_valid: mode_status 0
Connector 0/@40: DPI-1
[ 50.675869] csc->m[CSS_CbR] ffffffda fld_val 7da0000
Crtc 0/@38: 720x487i@119.88 27.000 720/20/20/98/+ 487/13/10/15[ 50.681597] Writing 8 at 810042
/+ 120 (119.88) 0x15 0x48
Plane 0/@31: 0,0-720x487
Fb 49[ 50.690270] Writing c at 7da0019
720x487-XR24
[ 50.699032] Writing 10 at 7007b5
[ 50.703535] Writing 5c at 7a20070
[ 50.706852] Writing 60 at 7ee
[ 50.709823] Writing 64 at 0
[ 50.712609] Writing 68 at 8000000
[ 50.715929] Writing 6c at 40004000
press enter to exit
I hope this is useful.
Regards,
Nikolay NIkolov
Hi Nikolov,
Can you please also try using the following 3 timing parameters:
In case the 'Input Parameters' are set incorrectly, please use this web-page https://tomverbeure.github.io/video_timings_calculator as per your use case and then experiment with those parameters.
Also, earlier Bas mentioned you have 525 lines, which is standard for NTSC: 720x480. What happens when you use 480 instead of 487?
Hi,
I don't think VIDL (VideoLite) pipeline is involved. Check out the following:
Only registers you may need to modify are DSS_VID_xxx and not the DSS_VIDL1_xxx registers.
Hi Divyansh,
I managed to make interlaced mode working with this patch which is in development state and needs to be reworked:
diff --git a/drivers/gpu/drm/drm_probe_helper.c b/drivers/gpu/drm/drm_probe_helper.c
index c90afb5d0898..aa2921277cbe 100644
--- a/drivers/gpu/drm/drm_probe_helper.c
+++ b/drivers/gpu/drm/drm_probe_helper.c
@@ -71,8 +71,10 @@ drm_mode_validate_flag(const struct drm_display_mode *mode,
int flags)
{
if ((mode->flags & DRM_MODE_FLAG_INTERLACE) &&
- !(flags & DRM_MODE_FLAG_INTERLACE))
+ !(flags & DRM_MODE_FLAG_INTERLACE)) {
+ pr_warn("Interlace not supported, mode flags 0x%x, flags 0x%x\n", mode->flags, flags);
return MODE_NO_INTERLACE;
+ }
if ((mode->flags & DRM_MODE_FLAG_DBLSCAN) &&
!(flags & DRM_MODE_FLAG_DBLSCAN))
diff --git a/drivers/gpu/drm/tidss/tidss_crtc.c b/drivers/gpu/drm/tidss/tidss_crtc.c
index 14691f346f11..dc48dcddc397 100644
--- a/drivers/gpu/drm/tidss/tidss_crtc.c
+++ b/drivers/gpu/drm/tidss/tidss_crtc.c
@@ -109,11 +109,12 @@ static int tidss_crtc_atomic_check(struct drm_crtc *crtc,
ok = dispc_vp_mode_valid(dispc, hw_videoport, mode);
if (ok != MODE_OK) {
- dev_dbg(ddev->dev, "%s: bad mode: %ux%u pclk %u kHz\n",
+ dev_warn(ddev->dev, "%s: bad mode: %ux%u pclk %u kHz\n",
__func__, mode->hdisplay, mode->vdisplay, mode->clock);
return -EINVAL;
}
+ //drm_mode_set_crtcinfo(&crtc_state->adjusted_mode, mode->flags & DRM_MODE_FLAG_INTERLACE ? CRTC_INTERLACE_HALVE_V : 0);
drm_mode_set_crtcinfo(&crtc_state->adjusted_mode, 0);
return dispc_vp_bus_check(dispc, hw_videoport, crtc_state);
}
@@ -393,7 +394,7 @@ enum drm_mode_status tidss_crtc_mode_valid(struct drm_crtc *crtc,
ok = dispc_vp_mode_valid(dispc, hw_videoport, mode);
if (ok != MODE_OK) {
- dev_dbg(ddev->dev, "%s: bad mode: %ux%u pclk %u kHz\n",
+ dev_warn(ddev->dev, "%s: bad mode: %ux%u pclk %u kHz\n",
__func__, mode->hdisplay, mode->vdisplay, mode->clock);
return -EINVAL;
}
+ //drm_mode_set_crtcinfo(&crtc_state->adjusted_mode, mode->flags & DRM_MODE_FLAG_INTERLACE ? CRTC_INTERLACE_HALVE_V : 0);
drm_mode_set_crtcinfo(&crtc_state->adjusted_mode, 0);
return dispc_vp_bus_check(dispc, hw_videoport, crtc_state);
}
@@ -393,7 +394,7 @@ enum drm_mode_status tidss_crtc_mode_valid(struct drm_crtc *crtc,
struct drm_device *ddev = crtc->dev;
struct tidss_device *tidss = to_tidss(ddev);
- return dispc_vp_mode_valid(tidss->dispc, tcrtc->hw_videoport, mode);
+ return dispc_vp_mode_valid(tidss->dispc, tcrtc->hw_videoport, mode);
}
static const struct drm_crtc_helper_funcs tidss_crtc_helper_funcs = {
diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/tidss_dispc.c
index 317ff8f420a6..8211da90e7b5 100644
--- a/drivers/gpu/drm/tidss/tidss_dispc.c
+++ b/drivers/gpu/drm/tidss/tidss_dispc.c
@@ -1399,8 +1399,10 @@ enum drm_mode_status dispc_vp_mode_valid(struct dispc_device *dispc,
return MODE_BAD;
/* TODO: add interlace support */
- if (mode->flags & DRM_MODE_FLAG_INTERLACE)
- return MODE_NO_INTERLACE;
+ if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
+ //dev_warn(dispc->dev, "%s: No interlace support in tidss but continue as we need it\n", __func__);
+ //return MODE_NO_INTERLACE;
+ }
/*
* Enforce the output width is divisible by 2. Actually this
@@ -2294,10 +2296,11 @@ void dispc_plane_setup(struct dispc_device *dispc, u32 hw_plane,
dispc_plane_set_pixel_format(dispc, hw_plane, fourcc);
+ //dev_warn(dispc->dev, "hw_plane=%d, lite=%d, dma_addr=0x%llx, fourcc=0x%x, fb_width %d, cpp %d, yinc %d, xinc %d\n", hw_plane, lite, dma_addr, fourcc, fb_width, cpp, scale.yinc, scale.xinc);
dispc_vid_write(dispc, hw_plane, DISPC_VID_BA_0, dma_addr & 0xffffffff);
dispc_vid_write(dispc, hw_plane, DISPC_VID_BA_EXT_0, (u64)dma_addr >> 32);
- dispc_vid_write(dispc, hw_plane, DISPC_VID_BA_1, dma_addr & 0xffffffff);
- dispc_vid_write(dispc, hw_plane, DISPC_VID_BA_EXT_1, (u64)dma_addr >> 32);
+ dispc_vid_write(dispc, hw_plane, DISPC_VID_BA_1, (dma_addr + fb_width*cpp) & 0xffffffff);
+ dispc_vid_write(dispc, hw_plane, DISPC_VID_BA_EXT_1, (u64)(dma_addr + fb_width*cpp) >> 32);
dispc_vid_write(dispc, hw_plane, DISPC_VID_PICTURE_SIZE,
(scale.in_w - 1) | ((scale.in_h - 1) << 16));
@@ -2310,10 +2313,13 @@ void dispc_plane_setup(struct dispc_device *dispc, u32 hw_plane,
dispc_vid_write(dispc, hw_plane, DISPC_VID_PIXEL_INC,
pixinc(scale.xinc, cpp));
+ //dispc_vid_write(dispc, hw_plane, DISPC_VID_ROW_INC,
+ // pixinc(1 + (scale.yinc * fb_width -
+ // scale.xinc * scale.in_w),
+ // cpp));
+ //dev_warn(dispc->dev, "inc one row with %d\n", pixinc(fb_width+1, cpp));
dispc_vid_write(dispc, hw_plane, DISPC_VID_ROW_INC,
- pixinc(1 + (scale.yinc * fb_width -
- scale.xinc * scale.in_w),
- cpp));
+ pixinc(fb_width+1, cpp));
if (state->fb->format->num_planes == 2) {
u16 cpp_uv = state->fb->format->cpp[1];
diff --git a/drivers/gpu/drm/tidss/tidss_encoder.c b/drivers/gpu/drm/tidss/tidss_encoder.c
index 17a86bed8054..4af343d4f16a 100644
--- a/drivers/gpu/drm/tidss/tidss_encoder.c
+++ b/drivers/gpu/drm/tidss/tidss_encoder.c
@@ -116,6 +116,8 @@ int tidss_encoder_create(struct tidss_device *tidss,
return PTR_ERR(connector);
}
+ connector->interlace_allowed = true;
+
ret = drm_connector_attach_encoder(connector, enc);
if (ret) {
dev_err(tidss->dev, "attaching encoder to connector failed\n");
diff --git a/drivers/gpu/drm/tidss/tidss_kms.c b/drivers/gpu/drm/tidss/tidss_kms.c
index a0e494c806a9..831f8165cded 100644
--- a/drivers/gpu/drm/tidss/tidss_kms.c
+++ b/drivers/gpu/drm/tidss/tidss_kms.c
@@ -175,6 +175,8 @@ static int tidss_dispc_modeset_init(struct tidss_device *tidss)
}
}
+ dev_warn(dev, "Bridge interlace_allowed %d\n", bridge->interlace_allowed);
+ bridge->interlace_allowed = true;
pipes[num_pipes].hw_videoport = i;
pipes[num_pipes].bridge = bridge;
pipes[num_pipes].enc_type = enc_type;
I am going to make this patch better as some things are just made to prove interlaced mode is possible to set. With this patch interlaced mode is hard coded and scaling is probably broken.
Now the picture from kmstest looks like this:
I can say for sure VIDL1 is used as I put debugs and also I can see the change in the VIDL1_ROW_INC register:
rwmem 0x3020221c
0x3020221c (+0x0) = 0x00000b41
I have some trouble with the first 4 pixels of the 1st line in the even field. The 4 pixels change constantly for some reason. The behavior of this pixels is really strange as some time these pixels are OK but the 4 pixels of the 1st line of the odd field are wrong. I still do not know what is the root cause of this behavior and why it is different every time.
Hi Divyansh Mittal ,
I am using gstreamer with the kmssink plugin to output to the display (which is working now).
I have set the rendering-rectangle parameter of the kmssink plugin (x = 97, y = 8, width = 528, height = 410). This kinda works (I see the video displayed in that area), but I see ghosting in the area below that.
(This is a picture of the screen, I hope the ghosting is visible)
Any idea what could cause this? It looks like some frames are repeated in the part not actively written.
Regards,
Bas Vermeulen