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AM620-Q1: MCU Rail Definition in Voltage/Power/Clock Domain

Evan Wang
Genius 12230 points

Part Number: AM620-Q1
Other Parts Discussed in Thread: SK-AM62-LP

Tool/software:

Hi Team,

1. We need your help to provide a table showing which voltage rail from AM6204-Q1 are still needed based on different mode.

The purpose is to evaluate the entire power consumption of AM6204-Q1 and the PMIC, but first, we need to know which rails still exist and which rails we can disable.

Hard to tell from DS/TRM/EVM that which rail belongs to Voltage/Power Domain and Clocks.

Please help to check and provide related info.

2. From the "sprr471c", it seems that TPS6521920WRHBRQ1 is the PMIC of AM620-Q1 series.

So I assume the default NVM setting on the PMIC can already fulfill the required operation from Partial I/O mode to Standby mode?

=> ex: When enter from Partial I/O mode to MCU_Only mode, the PMIC itself know which rail should be enabled or disabled so we don't need to further set the Reg.

Is that correct? 

Thank you.

  • 0
    TI__Guru**** 215090 points

    Hello Evan Wang, 

    Thank you for the query.

    I am reviewing the query.

    I may have to assign to the power expert to support.

    Regards,

    Sreenivasa

  • 0 in reply to Kallikuppa Sreenivasa
    TI__Mastermind 25856 points

    Hi,

    Thanks for reaching out. "Partial IO" is the only AM620-Q1 low power mode that requires turning-OFF external regulators. The remaining low power modes on this specific SoC family do not require to turn-OFF external supplies. 

    To get the lowest power consumption when supporting "Partial IO" LPM, the PMIC_LPM_EN0 drives the PMIC enable pin low which triggers an OFF request. Two external discrete LDOs are kept ON to supply the CANUART rails. 

    Let us know if there are any additional questions.  

    Thanks,

    Brenda

  • 0 in reply to Brenda Diaz
    TI__Genius 12230 points

    Hu Brenda,

    Thank you for the feedback.

    Brenda Diaz said:
    Two external discrete LDOs are kept ON to supply the CANUART rails. 

    1. If my understanding is correct that those LDOs refer to VPP_1V8 and VDD_CANUART, am I right? 

    2. If it's correct, I think we don't need to power the VPP_1V8 rail under partial I/O mode since it's mainly for OTP setting. Am I right?

    3. We use the TPS6521920WRHBRQ1 in the EVM called "SK-AM62-LP(sprr471c)", so this PMIC OPN can already cover all the required OTP setting for AM6204-Q1 no matter under which mode?(Partial I/O, deepsleep....etc)?

    Which means the default OTP setting on TPS6521920WRHBRQ1 already know which rails should be turn on/off under ACTIVE/STANDBT...etc follow by AM6204-Q1's command?

    4. Under the partial I/O mode, may we learn what's the current consumption of the VPP_1V8 and VDD_CANUART and VDDSHV_CANUART rails?

    Since we need to evaluate the total system quiescent.

    Looking forward to your reply.

    Thank you.

  • 0 in reply to Evan Wang
    TI__Mastermind 25856 points

    Please find the responses below and let us know if there are any additional questions. 

    1. No; For "Partial IO" low power mode, VDDSHV_CANUART and VDD_CANUART are the two rails that must stay ON. 
    2. VPP the eFuse ROM programming supply. An external LDO commonly used to supply the VPP rail and is enabled/disabled by one of the SoC digital pins. As noted in the datasheet, VPP must be disabled (OFF) during power-up.  Refer to section "VPP Specifications for One-Time Programmable (OTP) eFuses" in the spec for more information. 
    3. Yes, TPS6521920-Q1 comes pre-configured to meet the supply/sequence requirements of AM620-Q1. As mentioned in one of the previous messages, the PMIC is turned OFF when supporting "Partial IO" LPM. All the remaining low power modes in AM620-Q1 specifically do not require turning-OFF any supplies. 
    4. Partial IO power consumption is in the uW (<1mW).

    Thanks,

    Brenda