[FAQ] TDA4AEN-Q1: How to enable SGMII support on CPSW3G using native Linux Driver?

By default, SGMII is not included as supported feature in the CPSW driver and PHY selection. Additionally, the required device tree reference are not present in the TI SDK.

To enable or activate SGMII support for CPSW3G in the native Linux Driver, the following driver modifications and device configuration changes are required.

Driver changes: 

File: drivers/net/ethernet/ti/am65-cpsw-nuss.c

static const struct am65_cpsw_pdata am64x_cpswxg_pdata = {
	.quirks = AM64_CPSW_QUIRK_DMA_RX_TDOWN_IRQ | AM64_CPSW_QUIRK_CUT_THRU,
	.ale_dev_id = "am64-cpswxg",
	.fdqring_mode = K3_RINGACC_RING_MODE_RING,
+	.extra_modes = BIT(PHY_INTERFACE_MODE_SGMII),
};

File: drivers/phy/ti/phy-gmii-sel.c

struct phy_gmii_sel_soc_data phy_gmii_sel_soc_am654 = {
    .use_of_data = true,
    .regfields = phy_gmii_sel_fields_am654,
+   .extra_modes = BIT(PHY_INTERFACE_MODE_SGMII),
};

File: drivers/phy/ti/phy-j721e-wiz.c

case AM64_WIZ_10G:
    if (wiz->lane_phy_type[lane] == PHY_TYPE_PCIE)
    return regmap_field_write(wiz->p0_fullrt_div[lane], 0x1);
+    if (wiz->lane_phy_type[lane] == PHY_TYPE_SGMII)
+    return regmap_field_write(wiz->p0_fullrt_div[lane], 0x2);
    break;

Device Tree changes:

To enable CPSW3G MAC Port-1 in SGMII Mode, the following device tree configuration to be added.

&cpsw3g {
	status = "okay";
};

&cpsw3g_mdio {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&mdio_pins_default>;
	reset-post-delay-us = <12000>;

	cpsw3g_phy0: ethernet-phy@1 {
		reg = <1>;
	};
};

&cpsw_port1 {
	status = "okay";
	phy-mode = "sgmii";
	mac-address = [00 00 00 00 00 00];
	phys = <&phy_gmii_sel 1>,<&serdes1_sgmii_link>;
	phy-names ="portmode","serdes";
	phy-handle = <&cpsw3g_phy0>;	
};

&cpsw_port2 {
	status = "disabled";
};


&serdes_ln_ctrl {
	idle-states = <J722S_SERDES0_LANE0_USB>,
		      <J722S_SERDES1_LANE0_QSGMII_LANE1>;
};

&serdes1 {
	serdes1_sgmii_link: phy@0 {
		reg = <0>;
		cdns,num-lanes = <1>;
		#phy-cells = <0>;
		cdns,phy-type = <PHY_TYPE_SGMII>;
		resets = <&serdes_wiz1 1>;
	};
};

Make sure to update appropriate PHY & GPIOs specific configuration in device tree based on your board's pin configuration and hardware setup.