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PROCESSOR-SDK-J722S: j722s clock speed in Uboot 11.0

Vibha Pant
Intellectual 581 points

Part Number: PROCESSOR-SDK-J722S

Tool/software:

Hello Team

On comparing the Uboot logs for J722s and comparing Uboot 11.0 , 10.1 and 9.0

We observe that the core speed was reported as 1250 in earlier Uboots and in 11.0 is reported as 1400.

We wanted to confirm that the clock speed has been changed in the 11.0 Uboot.

Uboot versions compared

9.0 U-Boot SPL 2023.04-ti-gf9b966c67473 (Mar 19 2024 - 20:31:40 +0000)
SYSFW ABI: 3.1 (firmware rev 0x0009 '9.0.6--w2023.01-j722s (Kool Koa')

10.1  U-Boot SPL 2024.04-ti-ga970f6e51043 (Nov 13 2024 - 14:26:23 +0000)
SYSFW ABI: 4.0 (firmware rev 0x000a '10.1.6--v10.01.06 (Fiery Fox)')

 
11.0: U-Boot SPL 2025.01-00410-g70667128cb5b (Apr 04 2025 - 18:20:14 +0000)
SYSFW ABI: 4.0 (firmware rev 0x000b '11.0.9--v11.00.09+ (Fancy Rat)')

Regards

Vibha

  • 0
    TI__Guru**** 167140 points

    Hello Vibha,

    Are you reading the values using the k3conf?

    Can you share the output?

    Best regards, 

    Keerthy

  • 0 in reply to Keerthy J
    Intellectual 581 points

    Hello Keerthy,

    The core speed we reported has been calculated by code in startup.

    I will recheck with k3conf and report what I see.

    Regards

    Vibha

  • 0 in reply to Vibha Pant
    Intellectual 581 points

    Hello Keerthy,

    k3conf indicates that the following are different across uboot 10.1 and 11, which correlates to the difference in the core speeds we are reporting:

    In 11.0

    |-------------------------------------------------------------------------------------------------------------------------------------------------------------|
    | Device ID | Clock ID | Clock Name                                                                                   | Status              | Clock Frequency |
    |-------------------------------------------------------------------------------------------------------------------------------------------------------------|
    .....

    |   166     |     3    | DEV_A53SS0_COREPAC_ARM_CLK_CLK                                                                          | CLK_STATE_READY     | 1400000000      |
    |   135     |     0    | DEV_A53SS0_CORE_0_A53_CORE0_ARM_CLK_CLK                                                      | CLK_STATE_READY     | 1400000000      |
    |   136     |     0    | DEV_A53SS0_CORE_1_A53_CORE1_ARM_CLK_CLK                                                      | CLK_STATE_READY     | 1400000000      |
    |   137     |     0    | DEV_A53SS0_CORE_2_A53_CORE2_ARM_CLK_CLK                                                      | CLK_STATE_READY     | 1400000000      |
    |   138     |     0    | DEV_A53SS0_CORE_3_A53_CORE3_ARM_CLK_CLK                                                      | CLK_STATE_READY     | 1400000000      |
    ....

    |   265     |     2    | DEV_COMPUTE_CLUSTER0_CLKDIV_0_FUNC_CLKIN_CLK                                                 | CLK_STATE_READY     | 1400000000      |

    .....

    IN 10.1

    |-------------------------------------------------------------------------------------------------------------------------------------------------------------|
    | Device ID | Clock ID | Clock Name                                                                                   | Status              | Clock Frequency |
    |-------------------------------------------------------------------------------------------------------------------------------------------------------------|
    ....   |
    |   166     |     3    | DEV_A53SS0_COREPAC_ARM_CLK_CLK                                                               | CLK_STATE_READY     | 1250000000      |
    ....
    |   135     |     0    | DEV_A53SS0_CORE_0_A53_CORE0_ARM_CLK_CLK                                                      | CLK_STATE_READY     | 1250000000      |
    |   136     |     0    | DEV_A53SS0_CORE_1_A53_CORE1_ARM_CLK_CLK                                                      | CLK_STATE_READY     | 1250000000      |
    |   137     |     0    | DEV_A53SS0_CORE_2_A53_CORE2_ARM_CLK_CLK                                                      | CLK_STATE_READY     | 1250000000      |
    |   138     |     0    | DEV_A53SS0_CORE_3_A53_CORE3_ARM_CLK_CLK                                                      | CLK_STATE_READY     | 1250000000      |

    ....

    |   265     |     2    | DEV_COMPUTE_CLUSTER0_CLKDIV_0_FUNC_CLKIN_CLK                                                 | CLK_STATE_READY     | 1250000000      |

    ....

    Attached logs.

    j722s_71_10.1_k3conf_corespeed_05082025.logj722s_71_11.0_k3conf_corespeed_05082025.log

    Thanks and regards

    Vibha