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TDA4VH-Q1: An error occurred while exporting the model. TIDL version: 11.01.04.01

hongyao.jin
Expert 1230 points
Part Number: TDA4VH-Q1


Tool/software:

Hi,

We are using tidl to export the model, but the model export failed, the log is as follows.

The TIDL version is 11.01.04.01.

The compressed file named E2E.zip, which contains the model and export config, has been uploaded to tidrive.ext.ti.com/.../100ec4b5-b2a9-4e4b-9208-f38f41488a4b

Thanks

  • 0
    TI__Expert 5870 points

    Hi Hongyao,

    Could you reshare the link? It seems this link doesn't work. Also did you copy and paste the link from your browser or did you click share via link? It should have given an access code as well.

    In terms of the model export, is this on the device or on emulation? Please share your inputs and full log as well in the file you share. 

    Warm regards,

    Christina Kuruvilla

  • 0 in reply to Christina Kuruvilla
    TI__Expert 5015 points

    Hi Christina,

    I have shared the folder with you containing customer content. Please check.

    Regards,

    Adam

  • 0 in reply to Adam Hua
    TI__Expert 5870 points

    Hi Adam,

    Received! Thank you for resharing.

    Warm regards,

    Christina

  • 0
    TI__Expert 5015 points

    hello hongyao,

    I am able to reproduce your issue:

    [TIDL Import] [PARSER] ERROR: Could not find Input of Reshape layer, output name:/TopK_output_1, input name:/TopK_output_1_20_21 -- [tidl_import_common.cpp, 21649]
    [TIDL Import]  ERROR:  - Failed in function: tidl_optimizeNet -- [tidl_import_core.cpp, 3183]
    [TIDL Import]  FATAL ERROR: Network Optimization failed -- [tidl_import_main.cpp, 500]
    [TIDL Import] Aborting

    This reshape layer is likely to be introduced to link the second graph, which seems to be caused by some unsupported layers.

    The reducedmax and transpose is not supported

    and causes this issue when creating the second graph.

    I am able to import this model with the following modifications on your model. I deleted some nodes after sigmod and added outputs.

    To conclude, this should be an issue that TIDL does not parse the model correctly, however, you can work on with a work around that put some of the nodes to post-processing.

    Regards,

    Adam

  • 0 in reply to Adam Hua
    Expert 1230 points

    Hello Adam,

    As shown in the figure below,  The reducedmax and transpose is supported. Is there a problem or something?

    github.com/.../supported_ops_rts_versions.md

    Thanks.

  • 0 in reply to hongyao.jin
    TI__Expert 5015 points

    Hi Hongyao,

    This is a bug that the order of operators are not correctly parsed if reducemax goes after transpose.

    I am able to reproduce your issue with this simplified model:

    https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/791/sigmod_5F00_transpose_5F00_reducemax_5F00_model_5F00_16384_5F00_17_5F00_opset18.onnx

    Available execution providers :  ['TIDLExecutionProvider', 'TIDLCompilationProvider', 'CPUExecutionProvider']

Running 1 Models - ['sigmod_transpose_reducemax_opset18']


Running_Model :  sigmod_transpose_reducemax_opset18  


Running shape inference on model ../../../models/public/sigmod_transpose_reducemax_model_16384_17_opset18.onnx 

tidl_tools_path                                 = /home/ht/edgeai/edgeai-tidl-tools/tools/AM69A/tidl_tools 
artifacts_folder                                = ../../../model-artifacts//sigmod_transpose_reducemax_opset18/artifacts 
tidl_tensor_bits                                = 8 
debug_level                                     = 1 
num_tidl_subgraphs                              = 16 
num_tidl_subgraph_max_node                      = 0 
enable_rt_multi_subgraph_support                = 0 
tidl_denylist                                   = 
tidl_denylist_layer_name                        = 
tidl_denylist_layer_type                        = 
tidl_allowlist_layer_name                       = 
model_type                                      =  
tidl_calibration_accuracy_level                 = 7 
tidl_calibration_options:num_frames_calibration = 2 
tidl_calibration_options:bias_calibration_iterations = 5 
mixed_precision_factor = -1.000000 
model_group_id = 0 
power_of_2_quantization                         = 2 
ONNX QDQ Enabled                                = 0 
enable_high_resolution_optimization             = 0 
pre_batchnorm_fold                              = 1 
add_data_convert_ops                            = 3 
output_feature_16bit_names_list                 =  
m_params_16bit_names_list                       =  
m_single_core_layers_names_list                 =  
m_spatial_split_layers_names_list               =  
m_channel_split_layers_names_list               =  
Inference mode                                  = 0 
Number of cores                                 = 1 
reserved_compile_constraints_flag               = 1601 
partial_init_during_compile                     = 0 
packetize_mode                                  = 0 
enable_tfr_optimization                         = 0 
ti_internal_reserved_1                          = 

========================= [Model Compilation Started] =========================

Model compilation will perform the following stages:
1. Parsing
2. Graph Optimization
3. Quantization & Calibration
4. Memory Planning

============================== [Version Summary] ==============================

-------------------------------------------------------------------------------
|          TIDL Tools Version          |              11_01_06_00             |
-------------------------------------------------------------------------------
|         C7x Firmware Version         |              11_00_08_00             |
-------------------------------------------------------------------------------
|            Runtime Version           |                1.15.0                |
-------------------------------------------------------------------------------
|          Model Opset Version         |                  18                  |
-------------------------------------------------------------------------------

============================== [Parsing Started] ==============================

[TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options
[TIDL Import] [PARSER] SUPPORTED: Layers type supported by TIDL --- layer type - Sigmoid,  Node name - /hidden/Sigmoid -- [tidl_onnxRtImport_core.cpp, 652]
[TIDL Import] [PARSER] UNSUPPORTED: Layer 1 - op type ReduceMax, Unknown input dimension, not supported by TIDL -- [tidl_onnxRtImport_core.cpp, 582]
[TIDL Import] [PARSER] UNSUPPORTED: Layer 2 - op type Transpose, Unknown input dimension, not supported by TIDL -- [tidl_onnxRtImport_core.cpp, 582]

------------------------- Subgraph Information Summary -------------------------
-------------------------------------------------------------------------------
|          Core           |      No. of Nodes       |   Number of Subgraphs   |
-------------------------------------------------------------------------------
| C7x                     |                       1 |                       1 |
| CPU                     |                       2 |                       x |
-------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------------
|   Node    |  Node Name |                                   Reason                                    |
--------------------------------------------------------------------------------------------------------
| ReduceMax | /ReduceMax | Layer 1 - op type ReduceMax, Unknown input dimension, not supported by TIDL |
| Transpose | Transpose  | Layer 2 - op type Transpose, Unknown input dimension, not supported by TIDL |
--------------------------------------------------------------------------------------------------------
Running Runtimes GraphViz - /home/ht/edgeai/edgeai-tidl-tools/tools/AM69A/tidl_tools/tidl_graphVisualiser_runtimes.out ../../../model-artifacts//sigmod_transpose_reducemax_opset18/artifacts/allowedNode.txt ../../../model-artifacts//sigmod_transpose_reducemax_opset18/artifacts/tempDir/graphvizInfo.txt ../../../model-artifacts//sigmod_transpose_reducemax_opset18/artifacts/tempDir/runtimes_visualization.svg 
============================= [Parsing Completed] =============================

TIDL_createStateImportFunc Started:
Compute on node : TIDLExecutionProvider_TIDL_0_0
  0,         Sigmoid, 1, 1, input, /hidden/Sigmoid_output_0

Input tensor name -  input 
Output tensor name - /hidden/Sigmoid_output_0 
Process Process-1:
Traceback (most recent call last):
  File "/home/ht/.pyenv/versions/3.10.18/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap
    self.run()
  File "/home/ht/.pyenv/versions/3.10.18/lib/python3.10/multiprocessing/process.py", line 108, in run
    self._target(*self._args, **self._kwargs)
  File "/home/ht/edgeai/edgeai-tidl-tools/examples/osrt_python/ort/onnxrt_ep.py", line 385, in run_model
    height = input_details[0].shape[2]
IndexError: list index out of range
************ in TIDL_subgraphRtDelete ************ 
^CTraceback (most recent call last):
  File "/home/ht/edgeai/edgeai-tidl-tools/examples/osrt_python/ort/onnxrt_ep.py", line 579, in <module>
    nthreads = join_one(nthreads)
  File "/home/ht/edgeai/edgeai-tidl-tools/examples/osrt_python/ort/onnxrt_ep.py", line 546, in join_one
    sem.acquire()
KeyboardInterrupt

    Regards,

    Adam

  • 0 in reply to hongyao.jin
    TI__Expert 5015 points

    Hi Hongyao,

    And I also work out a workaround by change the operator order sigmod->transpose->reducemax to transpose->sigmod->reducemax. Could you help try this and modify your post processing accordingly?

    https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/791/transpose_5F00_sigmod_5F00_reducemax_5F00_model_5F00_16384_5F00_17_5F00_opset18.onnx

    import log:

    Available execution providers :  ['TIDLExecutionProvider', 'TIDLCompilationProvider', 'CPUExecutionProvider']

Running 1 Models - ['transpose_sigmod_reducemax_opset18']


Running_Model :  transpose_sigmod_reducemax_opset18  


Running shape inference on model ../../../models/public/transpose_sigmod_reducemax_model_16384_17_opset18.onnx 

tidl_tools_path                                 = /home/ht/edgeai/edgeai-tidl-tools/tools/AM69A/tidl_tools 
artifacts_folder                                = ../../../model-artifacts//transpose_sigmod_reducemax_opset18/artifacts 
tidl_tensor_bits                                = 8 
debug_level                                     = 1 
num_tidl_subgraphs                              = 16 
num_tidl_subgraph_max_node                      = 0 
enable_rt_multi_subgraph_support                = 0 
tidl_denylist                                   = 
tidl_denylist_layer_name                        = 
tidl_denylist_layer_type                        = 
tidl_allowlist_layer_name                       = 
model_type                                      =  
tidl_calibration_accuracy_level                 = 7 
tidl_calibration_options:num_frames_calibration = 2 
tidl_calibration_options:bias_calibration_iterations = 5 
mixed_precision_factor = -1.000000 
model_group_id = 0 
power_of_2_quantization                         = 2 
ONNX QDQ Enabled                                = 0 
enable_high_resolution_optimization             = 0 
pre_batchnorm_fold                              = 1 
add_data_convert_ops                            = 3 
output_feature_16bit_names_list                 =  
m_params_16bit_names_list                       =  
m_single_core_layers_names_list                 =  
m_spatial_split_layers_names_list               =  
m_channel_split_layers_names_list               =  
Inference mode                                  = 0 
Number of cores                                 = 1 
reserved_compile_constraints_flag               = 1601 
partial_init_during_compile                     = 0 
packetize_mode                                  = 0 
enable_tfr_optimization                         = 0 
ti_internal_reserved_1                          = 

========================= [Model Compilation Started] =========================

Model compilation will perform the following stages:
1. Parsing
2. Graph Optimization
3. Quantization & Calibration
4. Memory Planning

============================== [Version Summary] ==============================

-------------------------------------------------------------------------------
|          TIDL Tools Version          |              11_01_06_00             |
-------------------------------------------------------------------------------
|         C7x Firmware Version         |              11_00_08_00             |
-------------------------------------------------------------------------------
|            Runtime Version           |                1.15.0                |
-------------------------------------------------------------------------------
|          Model Opset Version         |                  18                  |
-------------------------------------------------------------------------------

============================== [Parsing Started] ==============================

[TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options
[TIDL Import] [PARSER] SUPPORTED: Layers type supported by TIDL --- layer type - Transpose,  Node name - /Transpose -- [tidl_onnxRtImport_core.cpp, 652]
[TIDL Import] [PARSER] SUPPORTED: Layers type supported by TIDL --- layer type - Sigmoid,  Node name - /hidden/Sigmoid -- [tidl_onnxRtImport_core.cpp, 652]
initializer name ortshared_7_1_1_0_token_8, target name ortshared_7_1_1_0_token_8 
initializer name ortshared_7_1_1_0_token_8, target name ortshared_7_1_1_0_token_8 
[TIDL Import] [PARSER] SUPPORTED: Layers type supported by TIDL --- layer type - ReduceMax,  Node name - /ReduceMax -- [tidl_onnxRtImport_core.cpp, 652]

------------------------- Subgraph Information Summary -------------------------
-------------------------------------------------------------------------------
|          Core           |      No. of Nodes       |   Number of Subgraphs   |
-------------------------------------------------------------------------------
| C7x                     |                       3 |                       1 |
| CPU                     |                       0 |                       x |
-------------------------------------------------------------------------------
Running Runtimes GraphViz - /home/ht/edgeai/edgeai-tidl-tools/tools/AM69A/tidl_tools/tidl_graphVisualiser_runtimes.out ../../../model-artifacts//transpose_sigmod_reducemax_opset18/artifacts/allowedNode.txt ../../../model-artifacts//transpose_sigmod_reducemax_opset18/artifacts/tempDir/graphvizInfo.txt ../../../model-artifacts//transpose_sigmod_reducemax_opset18/artifacts/tempDir/runtimes_visualization.svg 
============================= [Parsing Completed] =============================

TIDL_createStateImportFunc Started:
Compute on node : TIDLExecutionProvider_TIDL_0_0
  0,       Transpose, 1, 1, input, /Transpose_output_0
  1,         Sigmoid, 1, 1, /Transpose_output_0, /hidden/Sigmoid_output_0
  2,       ReduceMax, 2, 1, /hidden/Sigmoid_output_0, output

Input tensor name -  input 
Output tensor name - output 
In TIDL_onnxRtImportInit subgraph_name=subgraph_0
Layer 0, subgraph id subgraph_0, name=output
Layer 1, subgraph id subgraph_0, name=input
initializer name ortshared_7_1_1_0_token_8, target name ortshared_7_1_1_0_token_8 
initializer name ortshared_7_1_1_0_token_8, target name ortshared_7_1_1_0_token_8 
==================== [Optimization for subgraph_0 Started] ====================

In TIDL_runtimesOptimizeNet: LayerIndex = 5, dataIndex = 4 
----------------------------- Optimization Summary -----------------------------
------------------------------------------------------------------------------
|        Layer        | Nodes before optimization | Nodes after optimization |
------------------------------------------------------------------------------
| TIDL_BatchNormLayer |                         0 |                        1 |
| TIDL_ReduceLayer    |                         1 |                        1 |
| TIDL_SigmoidLayer   |                         1 |                        0 |
| TIDL_TransposeLayer |                         1 |                        1 |
------------------------------------------------------------------------------

Total nodes in subgraph: 7

=================== [Optimization for subgraph_0 Completed] ===================

In TIDL_runtimesPostProcessNet 
************ in TIDL_subgraphRtCreate ************ 
 The soft limit is 10240
The hard limit is 10240
MEM: Init ... !!!
MEM: Init ... Done !!!
 0.0s:  VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO
 0.3s:  VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR
 0.4s:  VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING
 0.96s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP_C7-2
 0.1088s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 
 0.1104s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 
 0.1119s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 
 0.1129s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 
 0.1144s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 
 0.1156s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 
 0.1169s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 
 0.1180s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 
 0.1191s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 
 0.1203s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 
 0.1213s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 
 0.1225s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 
 0.1238s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-2 
 0.1248s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-2_PRI_2 
 0.1261s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-2_PRI_3 
 0.1272s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-2_PRI_4 
 0.1286s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-2_PRI_5 
 0.1299s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-2_PRI_6 
 0.1313s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-2_PRI_7 
 0.1325s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-2_PRI_8 
 0.1339s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-3 
 0.1351s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-3_PRI_2 
 0.1366s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-3_PRI_3 
 0.1381s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-3_PRI_4 
 0.1394s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-3_PRI_5 
 0.1410s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-3_PRI_6 
 0.1425s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-3_PRI_7 
 0.1438s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-3_PRI_8 
 0.1452s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-4 
 0.1466s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-4_PRI_2 
 0.1482s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-4_PRI_3 
 0.1495s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-4_PRI_4 
 0.1507s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-4_PRI_5 
 0.1519s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-4_PRI_6 
 0.1533s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-4_PRI_7 
 0.1546s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-4_PRI_8 
 0.1564s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 
 0.1577s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 
 0.1591s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 
 0.1608s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 
 0.1621s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 
 0.1632s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 
 0.1647s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 
 0.1658s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 
 0.1671s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 
 0.1686s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 
 0.1698s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 
 0.1709s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 
 0.1722s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 
 0.1736s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 
 0.1747s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE9 
 0.1760s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE10 
 0.1772s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE11 
 0.1785s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE12 
 0.1798s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 
 0.1808s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 
 0.1820s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 
 0.1839s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 
 0.1851s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 
 0.1862s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 
 0.1877s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 
 0.1887s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 
 0.1898s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC1_FC 
 0.1916s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 
 0.1928s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 
 0.1940s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 
 0.1954s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 
 0.1971s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 
 0.1985s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU4-0 
 0.1999s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC2_NF 
 0.2010s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC2_LDC1 
 0.2022s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC2_MSC1 
 0.2036s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC2_MSC2 
 0.2048s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC2_VISS1 
 0.2059s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC2_FC 
 0.2078s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU4-1 
 0.2082s:  VX_ZONE_INFO: [tivxInit:152] Initialization Done !!!
 0.2087s:  VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO
************ TIDL_subgraphRtCreate done ************ 
 ============= [Quantization & Calibration for subgraph_0 Started] =============

*******   In TIDL_subgraphRtInvoke  ******** 
             Layer,      Layer Cycles,  kernelOnlyCycles,    coreLoopCycles,  LayerSetupCycles,   dmaPipeupCycles, dmaPipeDownCycles,    PrefetchCycles,copyKerCoeffCycles, LayerDeinitCycles,   LastBlockCycles,    paddingTrigger,       paddingWait,   LayerWithoutPad,   LayerHandleCopy,      BackupCycles,     RestoreCycles,Multic7xContextCopyCycles,
                 1,                 0,                 0,                 0,                 0,                 0,                 0,                 0,                 0,                 0,                 0,                 0,                 0,                 0,                 0,                 0,                 0,                 0,
                 2,                 0,                 0,                 0,                 0,                 0,                 0,                 0,                 0,                 0,                 0,                 0,                 0,                 0,                 0,                 0,                 0,                 0,
                 3,                 0,                 0,                 0,                 0,                 0,                 0,                 0,                 0,                 0,                 0,                 0,                 0,                 0,                 0,                 0,                 0,                 0,
                 4,                 0,                 0,                 0,                 0,                 0,                 0,                 0,                 0,                 0,                 0,                 0,                 0,                 0,                 0,                 0,                 0,                 0,
                 5,                 0,                 0,                 0,                 0,                 0,                 0,                 0,                 0,                 0,                 0,                 0,                 0,                 0,                 0,                 0,                 0,                 0,
 Sum of Layer Cycles 0 
Sub Graph Stats 78.000000 3643.000000 164.000000 
*******  TIDL_subgraphRtInvoke done  ******** 
*******   In TIDL_subgraphRtInvoke  ******** 
             Layer,      Layer Cycles,  kernelOnlyCycles,    coreLoopCycles,  LayerSetupCycles,   dmaPipeupCycles, dmaPipeDownCycles,    PrefetchCycles,copyKerCoeffCycles, LayerDeinitCycles,   LastBlockCycles,    paddingTrigger,       paddingWait,   LayerWithoutPad,   LayerHandleCopy,      BackupCycles,     RestoreCycles,Multic7xContextCopyCycles,
                 1,                 0,                 0,                 0,                 0,                 0,                 0,                 0,                 0,                 0,                 0,                 0,                 0,                 0,                 0,                 0,                 0,                 0,
                 2,                 0,                 0,                 0,                 0,                 0,                 0,                 0,                 0,                 0,                 0,                 0,                 0,                 0,                 0,                 0,                 0,                 0,
                 3,                 0,                 0,                 0,                 0,                 0,                 0,                 0,                 0,                 0,                 0,                 0,                 0,                 0,                 0,                 0,                 0,                 0,
                 4,                 0,                 0,                 0,                 0,                 0,                 0,                 0,                 0,                 0,                 0,                 0,                 0,                 0,                 0,                 0,                 0,                 0,
                 5,                 0,                 0,                 0,                 0,                 0,                 0,                 0,                 0,                 0,                 0,                 0,                 0,                 0,                 0,                 0,                 0,                 0,
 Sum of Layer Cycles 0 
Sub Graph Stats 43.000000 3103.000000 102.000000 
*******  TIDL_subgraphRtInvoke done  ******** 
In TIDL_runtimesPostProcessNet 

-------- Running Calibration in Float Mode to Collect Tensor Statistics --------
[=============================================================================] 100 %

------------------ Fixed-point Calibration Iteration [1 / 5]: ------------------
[=============================================================================] 100 %

------------------ Fixed-point Calibration Iteration [2 / 5]: ------------------
[=============================================================================] 100 %

------------------ Fixed-point Calibration Iteration [3 / 5]: ------------------
[=============================================================================] 100 %

------------------ Fixed-point Calibration Iteration [4 / 5]: ------------------
[=============================================================================] 100 %

------------------ Fixed-point Calibration Iteration [5 / 5]: ------------------
[=============================================================================] 100 %

==================== [Quantization & Calibration Completed] ====================

========================== [Memory Planning Started] ==========================


------------------------- Network Compiler Traces ------------------------------
Successful Memory Allocation
Successful Workload Creation

========================= [Memory Planning Completed] =========================

Rerunning network compiler...
========================== [Memory Planning Started] ==========================


------------------------- Network Compiler Traces ------------------------------
Successful Memory Allocation
Successful Workload Creation

========================= [Memory Planning Completed] =========================

======================== Subgraph Compiled Successfully ========================




Saving output tensor to  ../../../output_binaries/

 
Completed_Model :     1, Name : transpose_sigmod_reducemax_opset18                , Total time :    2696.68, Offload Time :       3.37 , DDR RW MBs : 0, Output Image File : py_out_transpose_sigmod_reducemax_opset18_ADE_val_00001801.jpg, Output Bin File : py_out_transpose_sigmod_reducemax_opset18_ADE_val_00001801.bin
 
 
************ in TIDL_subgraphRtDelete ************ 
 MEM: Deinit ... !!!
MEM: Alloc's: 26 alloc's of 300822465 bytes 
MEM: Free's : 26 free's  of 300822465 bytes 
MEM: Open's : 0 allocs  of 0 bytes 
MEM: Deinit ... Done !!!

    Regards,

    Adam