Other Parts Discussed in Thread: UNIFLASH
Tool/software:
Hello Team,
we are using OSPI NOR Boot mode for SK-AM62-LP board.
we are want run our application in Stand alone mode in R5 Core.
Can you please let us know the memory handling between SBL and Application because we are using SBL in OSPI NOR boot mode. we want what should be the address of vector table for application and also when SBL boots to which DDR address the application will be copied and also to which TCM memory the vector table will be copied.
As per TI document, we got to know that for SK-AM62-LP board, we need to generate hs_fs image.
we tried converting application elf to rprc image and then rprc image to hs_fs image.
Can you please let us know the steps to convert to these images.
we have the default SBL cfg file with following images for OSPI NOR mode
# First point to sbl_uart_uniflash_stage1 binary, which initialises DDR and receives sbl_uart_uniflash_stage2 binary
--flash-writer=image/sbl_uart_uniflash_stage1.Release.hs_fs.tiimage
# Points to sbl_uart_uniflash_stage2 binary, which function's as a server to flash one or more files
# Please note this binary is copied to DDR by sbl_uart_uniflash_stage1 and not written to any boot media like flash or eMMC
--file=image/sbl_uart_uniflash_stage2_am62x-sk-lp_r5fss0-0_nortos_ti-arm-clang.appimage.hs_fs --operation=flash --flash-offset=0x0
# Now send one or more files to flash or flashverify as needed. The order of sending files does not matter
# When sending bootloader make sure to flash at offset 0x0. ROM expects bootloader at offset 0x0
--file=image/sbl_ospi_nor_stage1.Release.hs_fs.tiimage --operation=flash --flash-offset=0x0
# DM image is flashed at 0xa00000 or to whatever offset your bootloader is configured for
--file=image/Application.appimage.hs_fs --operation=flash --flash-offset=0xA0000 -----> for R5 core with our application
Is this Cfg file correct to boot multiple cores with app image in OSPI NOR mode?
For rprc generation :
Regards,
Pradeep R