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DRA829J-Q1: PCIe: common mode voltage at SERDES RX

Peter Fritzenschaft
Intellectual 401 points
Part Number: DRA829J-Q1


Tool/software:

We use PCIe (SERDES0 and SERDES2) of DRA829J-Q1 with Gen1, Jacinto is root complex.

AC coupling capacitor is 100nF, placed close to the transmitter.

Measurement shows a common mode voltage of 0V at the Jacinto receiver input.

Despite there is no negative reference connected to Jacinto pins, our expectation is that Jacinto is capable to evaluate the full differential voltage even if one SERDES RX input pin is at negative potential.
Or is the common mode voltage of the SERDES Receiver adjustable via register setting?

Regards, Peter

  • 0
    TI__Prodigy 260 points

    Hi Peter,

    Thank you for taking the time to post these questions. I will look into this and get back to you with a response by the end of this week.

    Regards,

    Jeff

  • +1 in reply to Jeff Saied
    TI__Prodigy 260 points

    Hi Peter,

    Measurement shows a common mode voltage of 0V at the Jacinto receiver input.

    As seen below in the PCI specifications, the receiver DC common mode voltage is nominally 0V. 

    our expectation is that Jacinto is capable to evaluate the full differential voltage even if one SERDES RX input pin is at negative potential.

    Yes, since the input buffers are AC-coupled differential comparators, they respond to the voltage difference between RX_P and RX_N. As long as the swing remains within PCIe compliance levels, they should be able to evaluate the full differential voltage, even if one pin dips below into a negative potential. 

    is the common mode voltage of the SERDES Receiver adjustable via register setting?

    No, the common mode voltage of the receiver is not adjustable via register settings.

    Let me know if you have any other questions!

    Regards,

    Jeff