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DRA829J-Q1: Ramp up of REFCLK Output

Peter Fritzenschaft
Intellectual 431 points

Part Number: DRA829J-Q1

Tool/software:

We use PCIe (SERDES0 and SERDES2) of DRA829J-Q1 with Gen1, Jacinto is root complex.

Our design uses differential PCIE_REFCLK pins in Output REFCLK Mode to clock the end point, as described in SPRACP4A.

External near-side termination to ground (49.9Ohm) is applied. As the end point has an independent supply, additional AC coupling capacitors (10nF) are implemented.

Is it possible to adjust the sequencing of the PCIe RefClk as follows:

  • Is the DC bias output voltage configurable or can only be switched on/off?
  • Is the amplitude of the AC signal configurable or can only be switched on/off?

 

The aim is reduce overshoot at the reference clock inputs of the receiver side during signal activation phase.

Regards, Peter

  • 0
    TI__Prodigy 360 points

    Hi Peter,

    Thank you for taking the time to post these questions. I will look into this and get back to you with a response by the end of this week.

    Regards,

    Jeff

  • 0 in reply to Jeff Saied
    TI__Prodigy 360 points

    Hi Peter,

    Neither the DC bias output voltage of the refclk or the amplitude of the AC signal is configurable. 

    The aim is reduce overshoot at the reference clock inputs of the receiver side during signal activation phase.

    Overshoot at the receiver's reference clock inputs is typically caused by impedance mismatch or transient charging of the AC-coupling capacitors during activation. Ensure that the 49.9 Ohm termination to ground is placed as close to the receiver pins as possible. Also, budget a short delay (~5ms) after the receiver bias rail is valid and stable before enabling the REFCLK driver. This provides sufficient time for the AC-coupling capacitors to charge from 0 V to the receiver bias level and minimize startup transients.

    Let me know if you have any other questions!

    Regards,

    Jeff