TDA4AP-Q1: LPDDR4 Boundary Scan

Hello Ryan,

Can you elaborate on these two points:

1. DDR configurations in the Jacinto processor are not being applied, and so

2. the waveforms are out of specification for the memory chips

Thanks,

Kyle

Hello,

BSDL is typically executed from a non-boot situation.  BSDL is relatively slow and its unlikely it could shift out a stable clock + all the command and data signals to operate a DDR interface properly.  BSDL can do that for non-volatile memories.

You may be able to toggle different pins and see an effect if a fixture is in place.

What type of test with a DDR part is possible using boundary scan?  Perhaps its possible that both the SOC and the DDR part are daisy chained on the same IO ring via JTAG and both ends of the connection can be manipulated.  I've not heard of someone doing that but it seems more in line with how BSDL might traditionally be used.

Richard, 

From your response, it sounds like we may be doing something the wrong way. Our end goal is to be able to verify connection after the assembling the circuit board. Does TI have a recommended method for checking connectivity from the processor to the ram after circuit board assembly? We have been using Boundary Scan for the purpose in the past, but if that is not the recommended method for this processor than I would like to implement the correct method. 

The DDR interface is going to need at speed testing to verify its good.  Presumably you will have other tests around current and other which when taken together give confidence in the interface.  Without a fixture or a defined pin state from the DDR vendor what you get back may be indeterminate.  Probably you can do things like drive a pin read adjacent pins to infer a short (see if others follow the logic level) but even that might be fuzzy if the unclocked, uninitialized DDR part's pins are in indeterminate states.

I would recommend you ask the DDR vendor if there are any guaranteed test states.  Most of the JTAG level tests for DDR I am familiar with load test patterns and leverage the SOCs controller and are not trying to use BSDL atomics.  Some interfaces match up well with simple boundary and others require a fixture or being added to the IO daisy chain to enable reliable levels.

Each of the external parts will have their own properties.   A methodology used for a static flash or sram may not map that well to a DDR.  It might be what you already do can work but you would have to experiment and verify with your memory vendor.

Richard,

It may be that we are talking past each other. You mention the following:

Richard Woodruff said:

Most of the JTAG level tests for DDR I am familiar with load test patterns and leverage the SOCs controller and are not trying to use BSDL atomics.

What are these other JTAG level tests? Could you describe this in more detail, or is there somewhere else I can go to learn about this?

We don't need to use BSDL to test the DDR if there are other options available over JTAG. I think we are just ignorant of what is typically done for this processor family and so we are trying to figure out what the recommended test processes is. This is the same memory that is used on the Jacinto eval boards, so I assume TI has a recommended test method that we could follow. 

Thank you for you patience.