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AM62A7-Q1: AM62A7 SoM not powering ON

VINAYAK M K
Prodigy 30 points
Part Number: AM62A7-Q1
Other Parts Discussed in Thread: AM62A7, SN74LVC1G11, TMUX154E

Tool/software:

Hello Team,

I am working on a custom System-on-Module (SoM) based on the AM62A7 processor, powered by the TPS65931211RWERQ1 PMIC.
The power architecture and sequencing logic have been designed in alignment with the AM62A STARTER KIT EVM reference design.
All power tree and rail configurations follow the TI reference implementation.

Design Overview

  • The nPWRON/ENABLE (Pin 20) of the PMIC is driven by the output of a 3-input AND gate (SN74LVC1G11).

  • One input to this AND gate is connected through a TMUX154E analog switch, which in the TI reference design, allows selection between two enable sources.

  • In my implementation, the TMUX154E SEL pin is tied high using a pull-up resistor, permanently selecting one channel.

  • Apart from this modification, all other circuitry, pull resistors, and power routing are identical to the TI reference schematic.

  • The attached image shows the custom schematic section for the nPWRON/ENABLE path.

Initial Tests and Observations

  1. Input power verification: 5 V is correctly supplied to the TPS565201DDCR buck converter, which generates a stable 3.3 V output.

  2. 3.3 V rail check: All 3.3 V nodes across the board are powered and verified.

  3. PMIC input check: The TPS65931211RWERQ1 receives 3.3 V at all relevant input pins.

  4. nPWRON/ENABLE measurement: The pin reads high (~1.8 V), which matches the expected state per the reference schematic.

  5. Startup behavior: The PMIC does not initiate its power-up sequence — no regulated outputs are observed, and nRSTOUT remains low.

  6. AND gate output: Verified to be high, indicating all input conditions are valid and the enable path is asserted.

Issue Summary

The TPS65931211RWERQ1 PMIC fails to initiate its power-up sequence even though the nPWRON/ENABLE pin is asserted high (logic 1).
No power rails are generated, and nRSTOUT remains low.
The only modification from the TI reference design is that the TMUX154E SEL pin has been tied high, permanently selecting one input channel instead of the circuit in the starter kit.

8547.power.pdf.

  • 0
    TI__Mastermind 23621 points

    Hi,

    Thanks for reaching out. Why is the FB_B3 pin connected to the DDR voltage? The PMIC voltage monitor on FB_B3 must be connected to 3.3 V. If 3.3 V is not connected to FB_B3 when the monitor is enabled then the device goes to the hardware SAFE RECOVERY state, and the processor voltages are disabled. Let us know if this fixes the issue. We can also look at other connections like the CANUART supplies. Here is the link to access the TPS65931211-Q1 users guide which explains how the PMIC analog and digital resources were configured: www.ti.com/.../slvucm3.pdf

    Thanks,

    Brenda

  • 0 in reply to Brenda Diaz
    Prodigy 30 points

    Hello  ,

    Thank you so much for highlighting the Feedback path issue on FB_B3. We have removed this connection and now keep the feedback pin open. But still, the  PMIC is not powering up. Is there a way to disable the monitoring function on the FB_B3 pin to check whether the remaining circuit is okay? 
    What are the other major failure points as per your review here? Could you please help me find out the problem and resolve it? 

  • 0 in reply to VINAYAK M K
    TI__Mastermind 23621 points

    Hi, 

    Was the FB_B3 connected to the 3.3V IO regulator as described in the TPS65931211-Q1 user's guide? www.ti.com/.../slvucm3.pdf 

    Thanks,

    Brenda

  • 0 in reply to Brenda Diaz
    Prodigy 30 points

    Hi,

    No, it was connected to the DDR power line. We have disconnected the connection. If the Pin is Floating, FB_B3 will be actively monitoring or disabled? 

  • 0 in reply to VINAYAK M K
    TI__Mastermind 23621 points

    FB_B3 cannot be left floating. As note in the PMIC user's guide: "FB_B3 must be connected to 3.3 V. If 3.3 V is not connected to FB_B3 when the monitor is enabled then the device goes to the hardware SAFE RECOVERY state, and the processor voltages are disabled".

    Thanks,

    Brenda