SK-AM62-LP: How to change AM62x CPU clock to 1.4Ghz

Hi Seiki-san,

Can you try updating the maximum value in the 'assigned-clock-rates' parameter in the R5 device tree?

https://git.ti.com/cgit/ti-u-boot/ti-u-boot/tree/arch/arm/dts/k3-am62-r5-sk-common.dtsi?h=ti-u-boot-2025.01#n15

Best Regards,

Anshu

Hi Seiki-san,

If what I mentioned before doesn't work, you can try updating the T speed grade frequency here: https://git.ti.com/cgit/ti-u-boot/ti-u-boot/tree/arch/arm/mach-k3/include/mach/am62_hardware.h?h=ti-u-boot-2025.01#n126

Only do this if you know that the supply voltage will consistently 0.85V. 

Thanks,

Anshu

Hi Anshu,

I modified the following codes, and it seems well. 

Is my changes are correct ?

<device tree: k3-am62-r5-sk-common.dtsi>

a53_0: a53@0 {
                compatible = "ti,am654-rproc";
                reg = <0x00 0x00a90000 0x00 0x10>;
                power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
                                <&k3_pds 135 TI_SCI_PD_EXCLUSIVE>,
                                <&k3_pds 166 TI_SCI_PD_EXCLUSIVE>;
                resets = <&k3_reset 135 0>;
                clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
                clock-names = "gtc", "core";
                assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
                assigned-clock-parents = <&k3_clks 61 2>;
                assigned-clock-rates = <200000000>, <1400000000>; 
                ti,sci = <&dmsc>;
                ti,sci-proc-id = <32>;
                ti,sci-host-id = <10>;
                bootph-pre-ram;
        };

<am62_hardware.h>

static inline int k3_get_a53_max_frequency(void)
{
    switch (k3_get_speed_grade()) {
    case 'K':
        return 800000000;
    case 'S':
        return 1000000000;
    case 'T':
        return 1400000000;
    case 'G':
    default:
        return 300000000;
    }
}

<U-boot log>

U-Boot SPL 2025.01-gd2a72467939e-dirty (Oct 31 2025 - 11:44:56 +0900)
SYSFW ABI: 4.0 (firmware rev 0x000b '11.1.2--v11.01.02 (Fancy Rat)')
Changed A53 CPU frequency to 1400000000Hz (T grade) in DT
SPL initial stack usage: 13392 bytes

...

Hi Seiki-san,

The changes seem correct. We're you able to test if its correctly ran the A53 cores are 1.4Ghz?

Thanks,
Anshu