All,
This thread has taken place on internal e2e, moving to external e2e to continue the discussion between TI and the customer.
TI Internal thread is here:
1578643/tda4vm-fails-to-allow-the-a72-cores-to-finish-loading-tispl-bin-to-complete-the-boot-sequence/6091597
Summarizing status and open questions:
- Customer is unable to bootload A72. Originally debugging as software issue
- observing a ~200 us droop on vdd_cpu, which is driven by 3-phase PDN-0C using TPS6542. Waveform snip:

- Disabling AVS allows boot to proceed succesfully.
- Customer has shared logs that show before and after PMIC register dump
diff before.txt after.txt
4c4
< 00: 00 82 13 04 01 2b 20 2b 30 2d 31 2b 31 1b 41 37 .????+ +0-1+1?A7
---
> 00: 00 82 13 04 31 2b 20 2b 30 2d 31 2b 31 1b 37 37 .
- Cusotmer has shared "print" in one code section to show what is programmed to PMIC
addr = 0x4 and value = 0x0
addr = 0xe and value = 0x41
- Writing 0x0 to BUCK1_CTRL will disable the PMIC buck outputs.
- Request to customer is to trace/print all I2C writes to PMIC and correlate with I2C oscope transactions to identify exactly what is being written and when.
- Strong suspicion that there may be two writes - one with 0x0 (as per log) and second with 0x31 (as per before/after I2C dump), and these two writes could explain the triangular "droop"
Regards,
Kyle




