[FAQ] AM67A, AM67 Custom board hardware design – Collaterals to Get started

Hi Board designers, 

FAQs for reference

e2e.ti.com/.../am67a-general-question-of-am67a

e2e.ti.com/.../am67a-die-registers-of-the-am67a

e2e.ti.com/.../am67a-seeking-guidance-for-development-am67a

e2e.ti.com/.../am67a-how-to-increase-the-clock-frequency-of-r5f-mcu-core-in-am67a

e2e.ti.com/.../am67a-purpose-of-the-reset-lines-and-reset-outputs

e2e.ti.com/.../am67a-importance-of-ddrss-register-configuration-tool-for-bring-up-custom-board

e2e.ti.com/.../am69a-i-would-like-to-compare-the-number-of-ip-cameras-that-can-be-connected-simultaneously-number-of-streams-to-am62a-67-a-68-a-and-69-a

e2e.ti.com/.../am62a7-q1-c7x-mma-versions-between-am62a-and-tda4ven

e2e.ti.com/.../am67a-pdn-impedance-requirements

e2e.ti.com/.../am67a-soc-package-delay
e2e.ti.com/.../5812246
e2e.ti.com/.../am67a-layout-questions
e2e.ti.com/.../am67a-minimum-decapling-capacitor-for-vdd_core
e2e.ti.com/.../am67a-am67a-evb-grounds-question

e2e.ti.com/.../am67a-external-reference-clock-requirement-for-serdes-function
e2e.ti.com/.../am67a-trace-requirement-for-pcie-reference-clock
https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1565204/j722sxh01evm-question-for-extenal-clock-source-of-pcie 

e2e.ti.com/.../am67a-pcie-reference-clock
1 - yes AM67A has several errata items related to PCIe and specifically clocks. I can't say is necessary to use external clock - that is dependent on how you are using PCIe and if the errata items will impact you. But certainly some of the work-arounds for the issue(s) involve using an external refclk.
2 - No in-line capacitor is required. LMK3H0102 can be connected directly to AM67 and PCIe connector/peripheral.

e2e.ti.com/.../am67a-can-the-pcie-subsystem-be-used-with-serdes0-or-only-with-serdes1
Yes, I see that figure 12-121 mention wrongly that the PCIe is supported on SERDES0. It is a mistake; only SERDES1 supports PCIe on AM67.

e2e.ti.com/.../am67a-how-to-generate-pcie-reset

e2e.ti.com/.../am67a-implementing-usb_id-on-a-custom-design

e2e.ti.com/.../am67a-partial-io-peripherals

e2e.ti.com/.../am67a-wkup_uart-mcu_uart-usage

e2e.ti.com/.../faq-tda4vm-dra829v-j721e-how-to-enable-ehrpwm-on-j7-evm-using-linux

e2e.ti.com/.../am67a-is-external-rtc-needed

e2e.ti.com/.../am67a-if-not-using-can-jtag-pins-be-left-as-unterminated-nc

e2e.ti.com/.../am67a-what-is-the-value-of-the-pin-pull-up-and-pull-down-resistors

e2e.ti.com/.../am67a-can-t-the-oldi-pins-be-configured-as-gpio

e2e.ti.com/.../am67a-design-guide-xspi-boot-mode-and-lbclk
I got a response from the ROM expert and he confirmed that OSPI0_LBCLK is not configured or used by ROM, so that particular pin can be used for some other config.
Internal reference clock with Taps that the Boot ROM supports with QSPI, OSPI and XSPI(With PHY disabled) boot modes.
For QSPI and OSPI boot, OSPI0_CLK frequency is 50MHz (Where internal reference clock is 200MHz). ROM has a way of learning the optimal tap settings, which is configured during boot.
While for xSPI boot without PHY, OSPI0_CLK frequency is 25MHz.

e2e.ti.com/.../am67a-can-gb-ethernet-be-operated-on-the-r5f-core
The SDK for AM67A supports the controlling the CPSW ethernet switch from a native Linux driver running on A53.
software-dl.ti.com/jacinto7/esd/processor-sdk-linux-am67a/11_00_00/exports/docs/linux/Foundational_Components/Kernel/Kernel_Drivers/Network/CPSW-Ethernet.html
While I did not find specific documentation for AM67A for an example of CPSW Ethernet on R5F core, on AM62P (which also has an R5F core), there are examples of setting up CPSW Ethernet to run on R5F via the MCU+SDK. For example: software-dl.ti.com/.../EXAMPLES_ENET_LWIP_CPSW.html

To my knowledge there is no plan for an MCU+SDK for AM67 so finding examples of Ethernet on R5F directly may not be difficult.

e2e.ti.com/.../am67a-pinctrl-of-gpio-pu-pd-seems-overwritten-when-requesting-the-line-via-gpiod
e2e.ti.com/.../am67a-how-to-connect-the-switch-chip

e2e.ti.com/.../am67a-internal-rgmii-delay

e2e.ti.com/.../am67a-does-am67a-support-four-2mp-30fps-camera-streaming-fish-eye-dewarp-simultaneously

e2e.ti.com/.../am67a-video-audio-requirements-check

e2e.ti.com/.../am67a-are-there-any-differences-between-the-4-csi-camera-ports
www.ti.com/.../spradh2a.pdf

e2e.ti.com/.../faq-am67a-enabling-csi2-sensors-via-fusion-board-on-am6x
e2e.ti.com/.../tda4ven-q1-multi-camera-input-using-mipi-virtual-channel

e2e.ti.com/.../am67a-does-ti-soc-have-plans-to-support-4x8mb-or-1x12mb-camera-sensor-and-usb-3-0

e2e.ti.com/.../am67a-isp-without-lpddr4

e2e.ti.com/.../5692256

 https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1465462/am67a-could-am67a-isp-support-support-4x8m-cmos-image-sensor 

Regards,

Sreenivasa

Hi Board Designers,

FYI

(+) AM67A: Request for Guidance on C7x Core Software Development (AM67A) - Processors forum - Processors - TI E2E support forums

AM67A: Request for Guidance on C7x Core Software Development (AM67A)

Please note that TI doesn`t support Beagle Y AI platform on TI E2E forums. Currently AM67A product is designed for C7x DSP to be used as DL compute accelerators. There is currently no roadmap available to enable C7x to be used as a DSP compute accelerator rather than DL accelerator. I am looping in relevant expert from productline who can indicate if there is future plan to support the platform and offer C7x DSP development option on this platform or if they can provide information for partners who may be able to support you outside of the TI standard offering to port/develop code on this platform.

Regards,

Sreenivasa

Hi Board Designers,

Inputs related to IBIS-AMI model availability 

(+) AM67A: IBIS-AMI model request - Processors forum - Processors - TI E2E support forums

AM67A: IBIS-AMI model request

I understand that the IBIS-AMI models are shared under NDA.

Please reach out to the filed team you are working to take this forward.

Regards,

Sreenivasa