TDA4VM-Q1: Regarding the TDA4VM SR2.0 Patch

0001-C7x-MISR-Update-ES2.0.patch show as below:

From 5230af74bf3ba08a7e1247beba80f376e25b1320 Mon Sep 17 00:00:00 2001
From: Josiitaa RL <j-rl@ti.com>
Date: Mon, 1 Jul 2024 15:08:19 +0530
Subject: [PATCH] C7x MISR Update ES2.0

-Included condition to check for silicon rev 2.0
-Included array with updated C7x MISR value for ES2.0

Signed-off by: <j-rl@ti.com>
---
 src/sdl/lbist/soc/j721e/sdl_soc_lbist.c | 120 +++++++++++++++++++++++-
 1 file changed, 119 insertions(+), 1 deletion(-)

diff --git a/src/sdl/lbist/soc/j721e/sdl_soc_lbist.c b/src/sdl/lbist/soc/j721e/sdl_soc_lbist.c
index 454c19f..d5555f8 100644
--- a/src/sdl/lbist/soc/j721e/sdl_soc_lbist.c
+++ b/src/sdl/lbist/soc/j721e/sdl_soc_lbist.c
@@ -92,6 +92,10 @@
 #define ES1_1_VPAC_MISR_EXP_VAL           (0xf99d3ab7U)
 #define ES1_1_DMPAC_MISR_EXP_VAL          (0xac4cc9c8U)
 
+/*
+ * LBIST expected MISR's for ES2.0 (using parameters above)
+ */
+#define ES2_0_C7X_MISR_EXP_VAL            (0xa95c8410U)
 /*
  * Note: the order for the below must match order of SDL_LBIST_inst
  */
@@ -315,6 +319,116 @@ static SDL_lbistInstInfo SDL_LBIST_InstInfoArray_ES1_1[SDL_LBIST_NUM_INSTANCES]
 
 };
 
+static SDL_lbistInstInfo SDL_LBIST_InstInfoArray_ES2_0[SDL_LBIST_NUM_INSTANCES] =
+{
+ /* Main R5F 0 */
+ {
+  .pLBISTRegs             = (SDL_lbistRegs *)(SDL_MAIN_R5F0_LBIST_BASE),
+  .pLBISTSig              = (uint32_t *)(SDL_MAIN_R5F0_LBIST_SIG),
+  .expectedMISR           = ES1_1_MAIN_R5_MISR_EXP_VAL,    /* Expected signature for main R5 0*/
+  .interruptNumber        = SDLR_MCU_R5FSS0_CORE0_INTR_GLUELOGIC_MAIN_PULSAR0_LBIST_GLUE_DFT_LBIST_BIST_DONE_0, /* BIST DONE interrupt number */
+  .doneFlag               = LBIST_NOT_DONE,                /* Initialize done flag */
+  .LBISTConfig = {
+      .dc_def        = LBIST_DC_DEF,
+      .divide_ratio  = LBIST_DIVIDE_RATIO,
+      .static_pc_def = ES1_1_LBIST_MAIN_R5_STATIC_PC_DEF,
+      .set_pc_def    = LBIST_SET_PC_DEF,
+      .reset_pc_def  = LBIST_RESET_PC_DEF,
+      .scan_pc_def   = ES1_1_LBIST_SCAN_PC_DEF,
+      .prpg_def      = LBIST_PRPG_DEF,
+  },
+ },
+ /* Main R5F 1 */
+ {
+  .pLBISTRegs             = (SDL_lbistRegs *)(SDL_MAIN_R5F1_LBIST_BASE),
+  .pLBISTSig              = (uint32_t *)(SDL_MAIN_R5F1_LBIST_SIG),
+  .expectedMISR           = ES1_1_MAIN_R5_MISR_EXP_VAL,    /* Expected signature Main R5 1*/
+  .interruptNumber        = SDLR_MCU_R5FSS0_CORE0_INTR_GLUELOGIC_MAIN_PULSAR1_LBIST_GLUE_DFT_LBIST_BIST_DONE_0,/* BIST DONE interrupt number */
+  .doneFlag               = LBIST_NOT_DONE,                /* Initialize done flag */
+  .LBISTConfig = {
+      .dc_def        = LBIST_DC_DEF,
+      .divide_ratio  = LBIST_DIVIDE_RATIO,
+      .static_pc_def = ES1_1_LBIST_MAIN_R5_STATIC_PC_DEF,
+      .set_pc_def    = LBIST_SET_PC_DEF,
+      .reset_pc_def  = LBIST_RESET_PC_DEF,
+      .scan_pc_def   = ES1_1_LBIST_SCAN_PC_DEF,
+      .prpg_def      = LBIST_PRPG_DEF,
+  },
+ },
+ /* C7x */
+ {
+  .pLBISTRegs             = (SDL_lbistRegs *)(SDL_C7X_LBIST_BASE),
+  .pLBISTSig              = (uint32_t *)(SDL_C7X_LBIST_SIG),
+  .expectedMISR           = ES2_0_C7X_MISR_EXP_VAL,        /* Expected signature for C7x*/
+  .interruptNumber        = SDLR_MCU_R5FSS0_CORE0_INTR_COMPUTE_CLUSTER0_C7X_4_DFT_LBIST_DFT_LBIST_BIST_DONE_0,/* BIST DONE interrupt number */
+  .doneFlag               = LBIST_NOT_DONE,                /* Initialize done flag */
+  .LBISTConfig = {
+      .dc_def        = LBIST_DC_DEF,
+      .divide_ratio  = LBIST_DIVIDE_RATIO,
+      .static_pc_def = ES1_1_LBIST_C7X_STATIC_PC_DEF,
+      .set_pc_def    = LBIST_SET_PC_DEF,
+      .reset_pc_def  = LBIST_RESET_PC_DEF,
+      .scan_pc_def   = ES1_1_LBIST_SCAN_PC_DEF,
+      .prpg_def      = LBIST_PRPG_DEF,
+  },
+ },
+
+ /* VPAC */
+ {
+  .pLBISTRegs             = (SDL_lbistRegs *)(SDL_VPAC_LBIST_BASE),
+  .pLBISTSig              = (uint32_t *)(SDL_VPAC_LBIST_SIG),
+  .expectedMISR           = ES1_1_VPAC_MISR_EXP_VAL,                     /* Expected signature for C6x*/
+  .interruptNumber        = SDLR_MCU_R5FSS0_CORE0_INTR_GLUELOGIC_VPAC_LBIST_GLUE_DFT_LBIST_BIST_DONE_0,/* BIST DONE interrupt number */
+  .doneFlag               = LBIST_NOT_DONE,                              /* Initialize done flag */
+  .LBISTConfig = {
+      .dc_def        = LBIST_DC_DEF,
+      .divide_ratio  = LBIST_DIVIDE_RATIO,
+      .static_pc_def = ES1_1_LBIST_VPAC_STATIC_PC_DEF,
+      .set_pc_def    = LBIST_SET_PC_DEF,
+      .reset_pc_def  = LBIST_RESET_PC_DEF,
+      .scan_pc_def   = ES1_1_LBIST_SCAN_PC_DEF,
+      .prpg_def      = LBIST_PRPG_DEF,
+  },
+ },
+
+ /* DMPAC */
+ {
+  .pLBISTRegs             = (SDL_lbistRegs *)(SDL_DMPAC_LBIST_BASE),
+  .pLBISTSig              = (uint32_t *)(SDL_DMPAC_LBIST_SIG),
+  .expectedMISR           = ES1_1_DMPAC_MISR_EXP_VAL,                     /* Expected signature for C6x*/
+  .interruptNumber        = SDLR_MCU_R5FSS0_CORE0_INTR_GLUELOGIC_DMPAC_LBIST_GLUE_DFT_LBIST_BIST_DONE_0,/* BIST DONE interrupt number */
+  .doneFlag               = LBIST_NOT_DONE,                               /* Initialize done flag */
+  .LBISTConfig = {
+      .dc_def        = LBIST_DC_DEF,
+      .divide_ratio  = LBIST_DIVIDE_RATIO,
+      .static_pc_def = LBIST_DMPAC_STATIC_PC_DEF,
+      .set_pc_def    = LBIST_SET_PC_DEF,
+      .reset_pc_def  = LBIST_RESET_PC_DEF,
+      .scan_pc_def   = ES1_1_LBIST_SCAN_PC_DEF,
+      .prpg_def      = LBIST_PRPG_DEF,
+  },
+ },
+
+ /* A72 */
+ {
+  .pLBISTRegs             = (SDL_lbistRegs *)(SDL_A72_LBIST_BASE),
+  .pLBISTSig              = (uint32_t *)(SDL_A72_LBIST_SIG),
+  .expectedMISR           = ES1_1_A72_MISR_EXP_VAL,        /* Expected signature for A72 */
+  .interruptNumber        = SDLR_MCU_R5FSS0_CORE0_INTR_COMPUTE_CLUSTER0_ARM0_DFT_LBIST_DFT_LBIST_BIST_DONE_0,/* BIST DONE interrupt number */
+  .doneFlag               = LBIST_NOT_DONE,                /* Initialize done flag */
+  .LBISTConfig = {
+      .dc_def        = LBIST_DC_DEF,
+      .divide_ratio  = LBIST_DIVIDE_RATIO,
+      .static_pc_def = ES1_1_LBIST_A72_STATIC_PC_DEF,
+      .set_pc_def    = LBIST_SET_PC_DEF,
+      .reset_pc_def  = LBIST_RESET_PC_DEF,
+      .scan_pc_def   = ES1_1_LBIST_SCAN_PC_DEF,
+      .prpg_def      = LBIST_PRPG_DEF,
+  },
+ },
+
+};
+
 SDL_lbistInstInfo * SDL_LBIST_getInstInfo(uint32_t index)
 {
     SDL_lbistInstInfo *handle;
@@ -324,10 +438,14 @@ SDL_lbistInstInfo * SDL_LBIST_getInstInfo(uint32_t index)
     siliconRev = SDL_REG32_FEXT((SDL_WKUP_CTRL_MMR0_CFG0_BASE +
                                 SDL_WKUP_CTRL_MMR_CFG0_JTAGID),
                                 WKUP_CTRL_MMR_CFG0_JTAGID_VARIANT);
-    if ((uint32_t)0U != siliconRev)
+    if ((uint32_t)1U == siliconRev)
     {
         handle = SDL_LBIST_InstInfoArray_ES1_1;
     }
+    if ((uint32_t)2U == siliconRev)
+    {
+        handle = SDL_LBIST_InstInfoArray_ES2_0;
+    }
     else
     {
         handle = SDL_LBIST_InstInfoArray_ES1_0;
-- 
2.34.1

0001-arm-mach-k3-common-reorder-removal-of-firewalls.PATCH show as below:

From f12789770928cd42cda3a20128257c3c1df25966 Mon Sep 17 00:00:00 2001
From: Diwakar Dhyani <d-dhyani@ti.com>
Date: Tue, 6 Aug 2024 10:27:57 +0530
Subject: [PATCH] arm: mach-k3: common: reorder removal of firewalls K3 devices
 have some firewalls set up by ROM that we usually remove so that the
 development is easy in HS devices.

While removing the firewalls disabling a background region before
disabling the foreground regions keeps the firewall in a state where all
the transactions will be blacklisted until all the regions are disabled.
This causes a race for some other entity trying to access that memory
region before all the firewalls are disabled and causes an exception.

Since there is no guarantee on where the background regions lie based on
ROM configurations or no guarantee if the background regions will allow
all transactions across the memory spaces, iterate the loop twice removing
the foregrounds first and then backgrounds.
---
 arch/arm/mach-k3/common.c | 53 ++++++++++++++++++++++++---------------
 arch/arm/mach-k3/common.h |  7 ++++++
 2 files changed, 40 insertions(+), 20 deletions(-)

diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c
index 37384047f2..6aee757433 100644
--- a/arch/arm/mach-k3/common.c
+++ b/arch/arm/mach-k3/common.c
@@ -530,36 +530,49 @@ void disable_linefill_optimization(void)
 }
 #endif
 
-void remove_fwl_configs(struct fwl_data *fwl_data, size_t fwl_data_size)
+static void remove_fwl_regions(struct fwl_data fwl_data, size_t num_regions,
+                enum k3_firewall_region_type fwl_type)
 {
-	struct ti_sci_msg_fwl_region region;
 	struct ti_sci_fwl_ops *fwl_ops;
 	struct ti_sci_handle *ti_sci;
-	size_t i, j;
+        struct ti_sci_msg_fwl_region region;
+        size_t j;
 
 	ti_sci = get_ti_sci_handle();
 	fwl_ops = &ti_sci->ops.fwl_ops;
-	for (i = 0; i < fwl_data_size; i++) {
-		for (j = 0; j <  fwl_data[i].regions; j++) {
-			region.fwl_id = fwl_data[i].fwl_id;
-			region.region = j;
-			region.n_permission_regs = 3;
-
-			fwl_ops->get_fwl_region(ti_sci, &region);
-
-			if (region.control != 0) {
-				pr_debug("Attempting to disable firewall %5d (%25s)\n",
-					 region.fwl_id, fwl_data[i].name);
-				region.control = 0;
-
-				if (fwl_ops->set_fwl_region(ti_sci, &region))
-					pr_err("Could not disable firewall %5d (%25s)\n",
-					       region.fwl_id, fwl_data[i].name);
-			}
+
+        for (j = 0; j < fwl_data.regions; j++) {
+        region.fwl_id = fwl_data.fwl_id;
+        region.region = j;
+        region.n_permission_regs = 3;
+
+        fwl_ops->get_fwl_region(ti_sci, &region);
+
+        /* Don't disable the background regions */
+         if (region.control != 0 &&
+             ((region.control >> K3_FIREWALL_BACKGROUND_BIT) & 1) == fwl_type) {
+                 debug("Attempting to disable firewall %5d (%25s)\n",
+                       region.fwl_id, fwl_data.name);
+                 region.control = 0;
+                 if (fwl_ops->set_fwl_region(ti_sci, &region))
+                         pr_err("Could not disable firewall %5d (%25s)\n",
+                                region.fwl_id, fwl_data.name);
 		}
 	}
 }
 
+void remove_fwl_configs(struct fwl_data *fwl_data, size_t fwl_data_size)
+{
+       size_t i;
+
+       for (i = 0; i < fwl_data_size; i++) {
+               remove_fwl_regions(fwl_data[i], fwl_data[i].regions,
+                                  K3_FIREWALL_REGION_FOREGROUND);
+               remove_fwl_regions(fwl_data[i], fwl_data[i].regions,
+                                  K3_FIREWALL_REGION_BACKGROUND);
+       }
+}
+
 void spl_enable_dcache(void)
 {
 #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
diff --git a/arch/arm/mach-k3/common.h b/arch/arm/mach-k3/common.h
index 8f38fcef7f..ed86ebeef2 100644
--- a/arch/arm/mach-k3/common.h
+++ b/arch/arm/mach-k3/common.h
@@ -12,12 +12,18 @@
 #define J721E  0xbb64
 #define J7200  0xbb6d
 
+#define K3_FIREWALL_BACKGROUND_BIT (8)
+
 struct fwl_data {
 	const char *name;
 	u16 fwl_id;
 	u16 regions;
 };
 
+enum k3_firewall_region_type {
+        K3_FIREWALL_REGION_FOREGROUND,
+        K3_FIREWALL_REGION_BACKGROUND
+};
 enum k3_device_type {
 	K3_DEVICE_TYPE_BAD,
 	K3_DEVICE_TYPE_GP,
@@ -30,6 +36,7 @@ enum k3_device_type {
 void setup_k3_mpu_regions(void);
 int early_console_init(void);
 void disable_linefill_optimization(void);
+int set_fwls(const struct ti_sci_msg_fwl_region *fwl_data, size_t fwl_data_size);
 void remove_fwl_configs(struct fwl_data *fwl_data, size_t fwl_data_size);
 int load_firmware(char *name_fw, char *name_loadaddr, u32 *loadaddr);
 void k3_sysfw_print_ver(void);
-- 
2.34.1

HI Liu,

Liu Hawayi said:

For the patch 0001-arm-mach-k3-common-reorder-removal-of-firewalls.PATCH, can it be shared between SR1.1 and SR2.0?

Yes, it can be shared.

For the second question, let me loop the safety expert on this.

Regards
Diwakar

Hi Liu,

Liu Hawayi said:

For the patch 0001-C7x-MISR-Update-ES2.0.patch, the file {rtos}/sdl/src/sdl/lbist/soc/j721e/sdl_soc_lbist.c cannot be found in SDK 8.0, nor can the function SDL_LBIST_getInstInfo be located. This makes the patch impossible to merge. How should this patch be handled?

This patch is meant to update the C7x MISR value as per HW validation on SR 2.0. The Software Diagnostics Library (SDL) was introduced in SDK 8.1 and contains LBIST tests. So this patch is applicable for SDK 8.1 and onwards.

Are you testing LBIST in your application? If yes, is it using SDL APIs?

Regards,

Josiitaa

Hi Josiitaa,

Our mass production projects use SDK 8.0, I can't find SDL directory, so the LBIST tests can't be supported on SDK8.0?

Regards,

Hawayi

SDK 8.0 is not a safety complete release and is outside of the support window for TI (SDK release + 1 year bug fix + 1 year support) as this release was available in Aug 2021. 

We have incrementally implemented additional SDL functions to provide ECC and LBIST coverage in the later SDK (with newer TI Clang toolchain) and have safety certified the SDL offering. Customers can refer to newer SDL implementation and do the backporting to their production baseline and certify their products. We will not be able to provide these new SDLs with the older production baseline. If you see any concerns, please contact your local TI sales team.

TI can also recommend partners who may be able to help with the backporting if you are not able to upgrade to the new SDK baseline.

Thanks and Regards,

Rahul Prabhu 

Hi,Rahul Prabhu:

Our product has been in continuous production for several years, and we don't want major changes. This is a chip iteration upgrade, and we only want to make minimal modifications to adapt the SR2.0 SOC on the SDK 8.0.

Regards,

Hawayi

Hi Keerthy,

The image has been generated, but it hasn't undergone detailed testing yet. Let's first theoretically verify whether this patch integration approach is correct.

Best Regards,

Hawayi