TDA4VPE-Q1: Pin muxing issues

sadeed muhammed

Part Number: TDA4VPE-Q1

we are designing SOM and Baseboard for TDA4APE6T5AANDRQ1

below is the screenshot of Pin mux tool for PCIe:


below is the screenshot of Pin mux tool for SGMII:

below is the screenshot of Pin mux tool for USB:


Below are the queries:
1. for PCIe1 upto 2L can be configured, 4 lanes not possible(showing error), can we split PCIe1 into
two individual lanes (1 lane forNvme ssd and another lane for PCIe to dual sata bridge)?

note: usb 3.0 all signals are muxed.

2. In SGMII5, TX lines are not showing even if pin mux tool is started fresh. How to find tx lines.

PCIe Devices we have are as below:
1. M.2 nvme ssd with PCIe gen 3 x1

2. PCIe to dual sata with PCIe gen 2 x 1

4 months ago

0 Takuma Fujiwara 4 months ago

TI__Guru 58723 points

Hi Sadeed,

TDA4VPE is a cut down of TDA4VP and has a reduced number of serdes instances. TDA4VPE does not support SERDES2, which is the serdes instance that has the SGMII5 lane, so it is not supported.

How each serdes instance can be muxed can be found in this dts file for reference: https://git.ti.com/cgit/ti-linux-kernel/ti-linux-kernel/tree/include/dt-bindings/mux/ti-serdes.h?h=ti-linux-6.12.y

Limitation of serdes block can be found here, including the limitation that "A single SERDES can support either one protocol (connects to one Peripheral IP) or two protocols (connects to multiple Peripheral IP) at the same time.": https://software-dl.ti.com/jacinto7/esd/j742s2-processor-linux-sdk/11_01_00_03/exports/docs/linux/Foundational_Components/Kernel/Kernel_Drivers/SERDES/SERDES.html. We do not have support for 2x PCIe and 1x SGMII on a single serdes instance, but if split between multiple serdes, it is supported.

Regards,

Takuma

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TDA4VPE-Q1: Pin muxing issues