[FAQ] AM62D-Q1: Understanding MCASP Audio Pipeline Latency(MCU PLUS SDK) - Buffer Priming and Pipeline Delays

Latency Components Overview

Audio latency in MCASP-based RTOS systems comes from several sources:

1. Buffer Priming Latency - Initial startup delay from priming NUM_BUFS buffers with zeros before audio processing begins
2. MCASP/DMA Pipeline Latency - Steady-state delay from the buffer queuing mechanism in the MCASP and DMA pipeline
3. Processing Framework Latency - Additional delay from any audio processing framework (depends on the software design)
4. ADC/DAC Conversion Latency - Hardware conversion time (typically tens to hundreds of microseconds)

Why Does This Latency Exist?

Our MCU PLUS SDK mcasp driver use a buffered DMA method for efficient data transfer. This architecture requires:
- Multiple buffers in the pipeline at the startup to maintain continuous audio flow without gaps or underruns
- Callback-driven processing where buffers are queued and processed sequentially

Detailed Latency Calculation

Example Buffer Configuration:

Block size: 16 samples
Sampling rate: 48 KHz
Time per buffer: 16 / 48000 = 0.333 ms
NUM_BUFS: 3 (typical priming count)


i) Latency due to Buffer Priming:

At system startup, the MCASP driver primes NUM_BUFS buffers with zeros before audio processing begins. This is done in 'mcasp_setup' to ensure the pipeline is full and ready for continuous operation. This introduces an initial offset:

Priming latency = NUM_BUFS × (Block size / Sampling rate)
                = 3 × (16 / 48000)
                = 3 × 0.333 ms
                = 1.0 ms(approx)

Note: NUM_BUFS can be confugured in the MCASP setup. Common values are 3 or 4 buffers. More buffers provide additional safety margin against underruns but increase startup latency.

ii) Latency in the Pipeline (Steady State):

At steady state, there is inherent latency from the MCASP/DMA buffer queuing mechanism:

MCASP/DMA Pipeline Delay:

When audio data is received at T=0:
1. Data is stored in the RX buffer
2. When the first callback occurs (at T=0.33 ms), the data is submitted to the TX queue
3. Multiple buffers are already queued in the TX pipeline
4. The buffer must wait for preceding buffers to be transmitted before it can be output

This creates a multi-buffer delay through the pipeline. 

MCASP/DMA Pipeline latency = NUM_BUFS × (Block size / Sampling rate)
                            = 3 × (16 / 48000)
                            = 3 × 0.333 ms
                            = 1.0 ms

Pipeline Visualization:

T=0:         RX Buffer receives input data
T=0.33ms:    First callback - data submitted to TX queue (Position: 3rd in queue)
T=0.67ms:    Second callback - data moves up in queue (Position: 2nd in queue)
T=1.00ms:    Third callback - data is transmitted (Output)

General Formula for MCASP Pipeline Latency

For any MCASP-based audio system, the baseline pipeline latency can be calculated as:

Base MCASP Latency = NUM_PIPELINE_BUFS × (Block_Size / Sample_Rate)

Where:
- NUM_PIPELINE_BUFS = 3
- Block_Size = Number of samples per buffer
- Sample_Rate = Audio sampling frequency (Hz)

Thanks,
Shreyansh