Part Number: AM62D-Q1
I am working on AM62D and attempting self-hosted debug where MCU R5F halts/resumes execution pipelines of A53 and C7x cores without using JTAG, etc. After going through the available documentation, I used CoreSight CTI and CPU debug registers to achieve the same.
For example (Planned Approach), to halt A53 from R5F: Compute Cluster, A53 core registers, and DebugSS are enabled via TISCI, and A53 debug/CTI address space that is mapped to R5F using RAT (AddrTranslateP) using which I attempted to halt A53 core 0.
RAT accesses do not cause faults, but A53 debug registers are not readable or writable. Therefore I am unable to halt A53 from R5F.
Am I missing some steps?
Should I use some other mechanism to trigger a halt/resume event on A53 from R5F?
Thanks in advance for any pointers!